RubyGems - udb - Versions diffs - 0.1.0 → 0.1.2 - Mend

udb 0.1.0 → 0.1.2

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Files changed (288) hide show

data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml CHANGED Viewed

@@ -84,7 +84,7 @@ operation(): |
   XReg virtual_address = X[xs1];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/lr.w.yaml CHANGED Viewed

@@ -84,7 +84,7 @@ operation(): |
   XReg virtual_address = X[xs1];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/sc.SIZE.AQRL.layout CHANGED Viewed

@@ -184,7 +184,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<<%= current_size[:align_bits] %>>(virtual_address)) {
+  if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -202,7 +202,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<<%= current_size[:operation_bits] %>>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(<%= current_size[:operation_bits] %>, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aq.yaml CHANGED Viewed

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml CHANGED Viewed

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.rl.yaml CHANGED Viewed

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.yaml CHANGED Viewed

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aq.yaml CHANGED Viewed

@@ -143,7 +143,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -161,7 +161,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(32, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aqrl.yaml CHANGED Viewed

@@ -143,7 +143,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -161,7 +161,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(32, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.w.rl.yaml CHANGED Viewed

@@ -143,7 +143,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -161,7 +161,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(32, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.w.yaml CHANGED Viewed

@@ -143,7 +143,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -161,7 +161,7 @@ operation(): |
     }
   }
-  Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(32, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zcb/c.lbu.yaml CHANGED Viewed

@@ -36,7 +36,7 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  X[creg2reg(xd)] = read_memory<8>(virtual_address, $encoding);
+  X[creg2reg(xd)] = read_memory(8, virtual_address, $encoding);
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zcb/c.lh.yaml CHANGED Viewed

@@ -37,7 +37,7 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  X[creg2reg(xd)] = sext(read_memory<16>(virtual_address, $encoding), 16);
+  X[creg2reg(xd)] = sext(read_memory(16, virtual_address, $encoding), 16);
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zcb/c.lhu.yaml CHANGED Viewed

@@ -37,7 +37,7 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  X[creg2reg(xd)] = read_memory<16>(virtual_address, $encoding);
+  X[creg2reg(xd)] = read_memory(16, virtual_address, $encoding);
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zcb/c.sb.yaml CHANGED Viewed

@@ -36,4 +36,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  write_memory<8>(virtual_address, X[creg2reg(xs2)][7:0], $encoding);
+  write_memory(8, virtual_address, X[creg2reg(xs2)][7:0], $encoding);

data/.data/spec/std/isa/inst/Zcb/c.sh.yaml CHANGED Viewed

@@ -37,4 +37,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  write_memory<16>(virtual_address, X[creg2reg(xs2)][15:0], $encoding);
+  write_memory(16, virtual_address, X[creg2reg(xs2)][15:0], $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fld.yaml CHANGED Viewed

@@ -38,4 +38,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  f[fd] = sext(read_memory<64>(virtual_address, $encoding), 64);
+  f[fd] = sext(read_memory(64, virtual_address, $encoding), 64);

data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml CHANGED Viewed

@@ -39,4 +39,4 @@ operation(): |
   XReg virtual_address = X[2] + imm;
-  f[fd] = read_memory<64>(virtual_address, $encoding);
+  f[fd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fsd.yaml CHANGED Viewed

@@ -38,4 +38,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  write_memory<64>(virtual_address, X[creg2reg(fs2)], $encoding);
+  write_memory(64, virtual_address, X[creg2reg(fs2)], $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml CHANGED Viewed

@@ -39,4 +39,4 @@ operation(): |
   XReg virtual_address = X[2] + imm;
-  write_memory<64>(virtual_address, f[fs2][63:0], $encoding);
+  write_memory(64, virtual_address, f[fs2][63:0], $encoding);

data/.data/spec/std/isa/inst/Zcf/c.flw.yaml CHANGED Viewed

@@ -38,4 +38,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  X[creg2reg(fd)] = sext(read_memory<32>(virtual_address, $encoding), 32);
+  X[creg2reg(fd)] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml CHANGED Viewed

@@ -39,4 +39,4 @@ operation(): |
   XReg virtual_address = X[2] + imm;
-  f[fd] = read_memory<32>(virtual_address, $encoding);
+  f[fd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml CHANGED Viewed

@@ -38,4 +38,4 @@ operation(): |
   XReg virtual_address = X[creg2reg(xs1)] + imm;
-  write_memory<32>(virtual_address, X[creg2reg(fs2)][31:0], $encoding);
+  write_memory(32, virtual_address, X[creg2reg(fs2)][31:0], $encoding);

data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml CHANGED Viewed

@@ -39,4 +39,4 @@ operation(): |
   XReg virtual_address = X[2] + imm;
-  write_memory<32>(virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, f[fs2][31:0], $encoding);

data/.data/spec/std/isa/inst/Zcmt/cm.jalt.yaml CHANGED Viewed

@@ -53,9 +53,9 @@ operation(): |
   access_check(result.paddr, xlen(), $pc, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode());
   if (xlen() == 32) {
-    addr = read_physical_memory<32>(result.paddr);
+    addr = read_physical_memory(32, result.paddr);
   } else {
-    addr = read_physical_memory<64>(result.paddr);
+    addr = read_physical_memory(64, result.paddr);
   }  # Ensure low-order bit is clear
   addr = addr & $signed(2'b10);

data/.data/spec/std/isa/inst/Zcmt/cm.jt.yaml CHANGED Viewed

@@ -47,9 +47,9 @@ operation(): |
   access_check(result.paddr, xlen(), $pc, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode());
   if (xlen() == 32) {
-    addr = read_physical_memory<32>(result.paddr);
+    addr = read_physical_memory(32, result.paddr);
   } else {
-    addr = read_physical_memory<64>(result.paddr);
+    addr = read_physical_memory(64, result.paddr);
   }
   # Ensure low-order bit is clear

data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml CHANGED Viewed

@@ -47,9 +47,9 @@ operation(): |
       if ((sp_value & 0x00400000) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = nan_box<16, FLEN>(HP_CANONICAL_NAN);
+      f[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0x1F, 0 ));
+      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
@@ -58,7 +58,7 @@ operation(): |
     # is OR-red with the sticky
     Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
     if ((exp | frac16) == 0) {
-      f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0, 0 ));
+      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
       assert(false, "TODO: implement roundPackToF16");
       # f[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);

data/.data/spec/std/isa/inst/Zfh/flh.yaml CHANGED Viewed

@@ -37,9 +37,9 @@ operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
-  Bits<16> hp_value = read_memory<16>(virtual_address, $encoding);
+  Bits<16> hp_value = read_memory(16, virtual_address, $encoding);
-  f[fd] = nan_box<16, FLEN>(hp_value);
+  f[fd] = nan_box(16, FLEN, hp_value);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml CHANGED Viewed

@@ -33,7 +33,7 @@ operation(): |
   Bits<16> hp_value = X[xs1][15:0];
-  f[fd] = nan_box<16, FLEN>(hp_value);
+  f[fd] = nan_box(16, FLEN, hp_value);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fsh.yaml CHANGED Viewed

@@ -42,7 +42,7 @@ operation(): |
   Bits<16> hp_value = f[fs2][15:0];
-  write_memory<16>(virtual_address, hp_value, $encoding);
+  write_memory(16, virtual_address, hp_value, $encoding);
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/isa/builtin_functions.idl CHANGED Viewed

@@ -406,9 +406,8 @@ generated function invalidate_translations {
 }
 function read_physical_memory {
-  template U32 len
-  returns Bits<len>
-  arguments XReg paddr
+  returns XReg
+  arguments U32 len, XReg paddr
   description {
     Read from physical memory.
   }
@@ -460,8 +459,7 @@ builtin function read_physical_memory_64 {
 }
 function write_physical_memory {
-  template U32 len
-  arguments XReg paddr, Bits<len> value
+  arguments U32 len, XReg paddr, XReg value
   description {
     Write to physical memory.
   }

data/.data/spec/std/isa/isa/fetch.idl CHANGED Viewed

@@ -22,7 +22,7 @@ function fetch_memory_aligned_16 {
     # may raise an exception
     access_check(result.paddr, 16, virtual_address, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode());
-    return read_physical_memory<16>(result.paddr);
+    return read_physical_memory(16, result.paddr);
   }
 }
@@ -45,7 +45,7 @@ function fetch_memory_aligned_32 {
     # may raise an exception
     access_check(result.paddr, 32, virtual_address, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode());
-    return read_physical_memory<32>(result.paddr);
+    return read_physical_memory(32, result.paddr);
   }
 }

data/.data/spec/std/isa/isa/fp.idl CHANGED Viewed

@@ -116,15 +116,14 @@ function mark_f_state_dirty {
 }
 function nan_box {
-  template U32 FROM_SIZE, U32 TO_SIZE
-  returns Bits<TO_SIZE>
-  arguments Bits<FROM_SIZE> from_value
+  returns XReg
+  arguments U32 FROM_SIZE, U32 TO_SIZE, XReg from_value
   description {
     Produces a properly NaN-boxed floating-point value from a floating-point value
     of smaller size by adding all 1's to the upper bits.
   }
   body {
-    assert(FROM_SIZE < TO_SIZE, "Bad template arguments; FROM_SIZE must be less than TO_SIZE");
+    assert(FROM_SIZE < TO_SIZE, "Bad arguments; FROM_SIZE must be less than TO_SIZE");
     return {{TO_SIZE - FROM_SIZE{1'b1}}, from_value};
   }
@@ -470,7 +469,7 @@ function softfloat_normSubnormalF16Sig {
     normalize subnormal half-precision value
   }
   body {
-    Bits<8> shift_dist = count_leading_zeros<16>(hp_value);
+    Bits<8> shift_dist = count_leading_zeros(16, hp_value);
     return 1 - shift_dist, hp_value << shift_dist;
   }
 }
@@ -535,7 +534,7 @@ function softfloat_normRoundPackToF32 {
     Normalize, round, and pack into a 32-bit floating point value
   }
   body {
-    Bits<8> shiftDist = count_leading_zeros<32>(sig) - 1;
+    Bits<8> shiftDist = count_leading_zeros(32, sig) - 1;
     exp = exp - shiftDist;
     if ((7 <= shiftDist) && (exp < 0xFD)) {
       return packToF32UI(sign, (sig != 0) ? exp : 0, sig << (shiftDist - 7));
@@ -843,7 +842,7 @@ function softfloat_subMagsF32 {
         sigDiff = -32'sh1 * sigDiff;
       }
-      shiftDist = count_leading_zeros<32>(sigDiff) - 8;
+      shiftDist = count_leading_zeros(32, sigDiff) - 8;
       expZ = expA - shiftDist;
       if (expZ < 0) {
@@ -1096,7 +1095,7 @@ function softfloat_normRoundPackToF32_no_flag {
     No flags to be set
   }
   body {
-    Bits<8> shiftDist = count_leading_zeros<32>(sig) - 1;
+    Bits<8> shiftDist = count_leading_zeros(32, sig) - 1;
     exp = exp - shiftDist;
     if ((7 <= shiftDist) && (exp < 0xFD)) {
       return packToF32UI(sign, (sig != 0) ? exp : 0, sig << (shiftDist - 7));