udb 0.1.0 → 0.1.2

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -35,7 +35,7 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<32>(virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lb.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<8>(virtual_address, $encoding), 8);
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lbu.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<8>(virtual_address, $encoding);
+  X[xd] = read_memory(8, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -53,7 +53,7 @@ operation(): |
 
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zilsd)) {
-      Bits<64> data = read_memory<64>(virtual_address, $encoding);
+      Bits<64> data = read_memory(64, virtual_address, $encoding);
 
       X[xd] = data[31:0];
       X[xd+1] = data[63:32];
@@ -61,7 +61,7 @@ operation(): |
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   } else {
-    X[xd] = read_memory<64>(virtual_address, $encoding);
+    X[xd] = read_memory(64, virtual_address, $encoding);
   }
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/I/lh.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<16>(virtual_address, $encoding), 16);
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lhu.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<16>(virtual_address, $encoding);
+  X[xd] = read_memory(16, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lw.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<32>(virtual_address, $encoding), 32);
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lwu.yaml

@@ -34,7 +34,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<32>(virtual_address, $encoding);
+  X[xd] = read_memory(32, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sb.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<8>(virtual_address, X[xs2][7:0], $encoding);
+  write_memory(8, virtual_address, X[xs2][7:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -59,7 +59,7 @@ operation(): |
     data = X[xs2];
   }
 
-  write_memory<64>(virtual_address, data, $encoding);
+  write_memory(64, virtual_address, data, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sh.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<16>(virtual_address, X[xs2][15:0], $encoding);
+  write_memory(16, virtual_address, X[xs2][15:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sw.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<32>(virtual_address, X[xs2][31:0], $encoding);
+  write_memory(32, virtual_address, X[xs2][31:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/V/vle8.v.yaml

@@ -36,7 +36,7 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + 7;
     v[vd] = {
       v[vd][VLEN-1:end_bit_pos + 1],
-      sext(read_memory<8>(virtual_address, $encoding), 8),
+      sext(read_memory(8, virtual_address, $encoding), 8),
       v[vd][start_bit_pos-1:0]
     };
     virtual_address = virtual_address + 1;

data/.data/spec/std/isa/inst/V/vse8.v.yaml

@@ -34,7 +34,7 @@ operation(): |
   for (U32 i = 0; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = (CSR[vstart].VALUE + i) * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-    write_memory<8>(virtual_address, v[vs3][end_bit_pos:start_bit_pos], $encoding);
+    write_memory(8, virtual_address, v[vs3][end_bit_pos:start_bit_pos], $encoding);
     virtual_address = virtual_address + 1;
   }
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout

@@ -78,7 +78,7 @@ operation(): |
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Add, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Add, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aq.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aqrl.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.rl.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout

@@ -78,7 +78,7 @@ operation(): |
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::And, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::And, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoand.d.aq.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoand.d.aqrl.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoand.d.rl.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoand.d.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoand.w.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amoand.w.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoand.w.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amoand.w.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout

@@ -78,7 +78,7 @@ operation(): |
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Max, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Max, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amomax.d.aq.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomax.d.aqrl.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomax.d.rl.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomax.d.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomax.w.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomax.w.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomax.w.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomax.w.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout

@@ -78,7 +78,7 @@ operation(): |
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Maxu, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Maxu, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.aq.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.aqrl.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.rl.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout

@@ -78,7 +78,7 @@ operation(): |
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Min, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Min, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amomin.d.aq.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomin.d.aqrl.yaml

@@ -46,7 +46,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomin.d.rl.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomin.d.yaml

@@ -44,7 +44,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomin.w.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zaamo/amomin.w.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomin.w.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zaamo/amomin.w.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>