udb 0.1.0 → 0.1.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mienter.nest.yaml +21 -21
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mienter.yaml +21 -21
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mileaveret.yaml +19 -19
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lb.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lbu.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lh.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lhu.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lw.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sb.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sh.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sw.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrb.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrbu.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrh.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrhu.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrw.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lwm.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lwmi.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.setwm.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.setwmi.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srb.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srh.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srw.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.swm.yaml +1 -1
- data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.swmi.yaml +1 -1
- data/.data/spec/schemas/README.adoc +6 -3
- data/.data/spec/schemas/csr_schema.json +1 -5
- data/.data/spec/std/isa/csr/Smrnmi/mnstatus.yaml +0 -11
- data/.data/spec/std/isa/csr/hstatus.yaml +0 -2
- data/.data/spec/std/isa/csr/mconfigptr.yaml +0 -3
- data/.data/spec/std/isa/csr/misa.yaml +0 -4
- data/.data/spec/std/isa/csr/mstatus.yaml +0 -13
- data/.data/spec/std/isa/csr/schema.adoc +0 -6
- data/.data/spec/std/isa/inst/C/c.ld.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.lw.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.lwsp.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.sd.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.sdsp.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.sw.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.swsp.yaml +1 -1
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lb.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lbu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/ld.yaml +2 -2
- data/.data/spec/std/isa/inst/I/lh.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lhu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lwu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sb.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sd.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sh.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sw.yaml +1 -1
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -1
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoand.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomax.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomaxu.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amomin.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amominu.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoor.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoswap.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.d.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.d.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.d.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.d.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.w.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.w.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.w.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zaamo/amoxor.w.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoadd.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoand.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomax.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amomin.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amominu.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoor.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.aq.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.aqrl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.rl.yaml +1 -1
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zalrsc/lr.SIZE.AQRL.layout +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.aq.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.aqrl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.rl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.aq.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.SIZE.AQRL.layout +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.d.aq.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.d.rl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.d.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.w.aq.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.w.aqrl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.w.rl.yaml +2 -2
- data/.data/spec/std/isa/inst/Zalrsc/sc.w.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.lbu.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcb/c.lh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcb/c.lhu.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcb/c.sb.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcb/c.sh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fsd.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.flw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmt/cm.jalt.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmt/cm.jt.yaml +2 -2
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +3 -3
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +2 -2
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +1 -1
- data/.data/spec/std/isa/isa/builtin_functions.idl +3 -5
- data/.data/spec/std/isa/isa/fetch.idl +2 -2
- data/.data/spec/std/isa/isa/fp.idl +7 -8
- data/.data/spec/std/isa/isa/globals.isa +123 -118
- data/.data/spec/std/isa/isa/util.idl +6 -8
- data/lib/udb/cfg_arch.rb +36 -7
- data/lib/udb/doc_link.rb +16 -13
- data/lib/udb/idl/condition_to_udb.rb +7 -7
- data/lib/udb/obj/extension.rb +106 -67
- data/lib/udb/version.rb +2 -1
- data/lib/udb/yaml/yaml_resolver.rb +1 -1
- metadata +2 -27
- data/.data/spec/std/isa/ext/Xmock.yaml +0 -30
- data/.data/spec/std/isa/param/MOCK_1_BIT_INT.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_25_BIT_INT.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_2_BIT_INT.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_32_BIT_INT.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_64_BIT_INT.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_ARRAY_BOOL_ARRAY_OF_8_FIRST_2_FALSE.yaml +0 -22
- data/.data/spec/std/isa/param/MOCK_ARRAY_INT_ENUM.yaml +0 -23
- data/.data/spec/std/isa/param/MOCK_ARRAY_MAX_ONLY.yaml +0 -21
- data/.data/spec/std/isa/param/MOCK_ARRAY_MIN_ONLY.yaml +0 -21
- data/.data/spec/std/isa/param/MOCK_ARRAY_STRING_ENUM1.yaml +0 -21
- data/.data/spec/std/isa/param/MOCK_ARRAY_STRING_ENUM2.yaml +0 -21
- data/.data/spec/std/isa/param/MOCK_BOOL_1.yaml +0 -15
- data/.data/spec/std/isa/param/MOCK_BOOL_2.yaml +0 -15
- data/.data/spec/std/isa/param/MOCK_ENUM_2_INTS.yaml +0 -18
- data/.data/spec/std/isa/param/MOCK_ENUM_2_STRINGS.yaml +0 -18
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_0_TO_1023.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_0_TO_127.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_0_TO_128.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_0_TO_2.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_0_TO_999.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_1000_TO_2048.yaml +0 -17
- data/.data/spec/std/isa/param/MOCK_INT_RANGE_1_TO_128.yaml +0 -17
- data/.data/spec/std/isa/proc_cert_class/MockProcessor.yaml +0 -13
- data/.data/spec/std/isa/profile_family/Mock.yaml +0 -24
checksums.yaml
CHANGED
|
@@ -1,7 +1,7 @@
|
|
|
1
1
|
---
|
|
2
2
|
SHA256:
|
|
3
|
-
metadata.gz:
|
|
4
|
-
data.tar.gz:
|
|
3
|
+
metadata.gz: 030b2114165b983357479c5b9f5c278ddcb859f6b89a529b2c632eb7227749dc
|
|
4
|
+
data.tar.gz: e2be4d1bec8e2fc90c32b96f457b8ebb2cef0390d9a0b9f431ed34803d87f55f
|
|
5
5
|
SHA512:
|
|
6
|
-
metadata.gz:
|
|
7
|
-
data.tar.gz:
|
|
6
|
+
metadata.gz: cadc118ddaa3396e17d89c5d3b89e754bed287c50285f7b6711ad63f5ecc305e00de02de3e5abf7b58e39b38989f2b24f94c022209c7f2b4185e9599fcde33e9
|
|
7
|
+
data.tar.gz: b1026028c8bd8a0c51fe497653b580fdc0af7c7e30878920a85aec71b6cc41c83e3b99bc84abbe63c6e7e8bb04371fe6cda49112245ce83de09ccca8a696f427
|
|
@@ -32,29 +32,29 @@ operation(): |
|
|
|
32
32
|
XReg qc_mcause_val = CSR[qc.mcause].sw_read();
|
|
33
33
|
XReg reserved_val = 0;
|
|
34
34
|
if (CSR[mnstatus].NMIE == 1'b1) {
|
|
35
|
-
write_memory
|
|
35
|
+
write_memory(32, virtual_address - 4, mepc_val, $encoding);
|
|
36
36
|
} else {
|
|
37
|
-
write_memory
|
|
37
|
+
write_memory(32, virtual_address - 4, mnepc_val, $encoding);
|
|
38
38
|
}
|
|
39
|
-
write_memory
|
|
40
|
-
write_memory
|
|
41
|
-
write_memory
|
|
42
|
-
write_memory
|
|
43
|
-
write_memory
|
|
44
|
-
write_memory
|
|
45
|
-
write_memory
|
|
46
|
-
write_memory
|
|
47
|
-
write_memory
|
|
48
|
-
write_memory
|
|
49
|
-
write_memory
|
|
50
|
-
write_memory
|
|
51
|
-
write_memory
|
|
52
|
-
write_memory
|
|
53
|
-
write_memory
|
|
54
|
-
write_memory
|
|
55
|
-
write_memory
|
|
56
|
-
write_memory
|
|
57
|
-
write_memory
|
|
39
|
+
write_memory(32, virtual_address - 8, X[ 8][31:0], $encoding);
|
|
40
|
+
write_memory(32, virtual_address - 12, qc_mcause_val, $encoding);
|
|
41
|
+
write_memory(32, virtual_address - 16, X[ 1][31:0], $encoding);
|
|
42
|
+
write_memory(32, virtual_address - 20, reserved_val, $encoding);
|
|
43
|
+
write_memory(32, virtual_address - 24, X[ 5][31:0], $encoding);
|
|
44
|
+
write_memory(32, virtual_address - 28, X[ 6][31:0], $encoding);
|
|
45
|
+
write_memory(32, virtual_address - 32, X[ 7][31:0], $encoding);
|
|
46
|
+
write_memory(32, virtual_address - 36, X[10][31:0], $encoding);
|
|
47
|
+
write_memory(32, virtual_address - 40, X[11][31:0], $encoding);
|
|
48
|
+
write_memory(32, virtual_address - 44, X[12][31:0], $encoding);
|
|
49
|
+
write_memory(32, virtual_address - 48, X[13][31:0], $encoding);
|
|
50
|
+
write_memory(32, virtual_address - 52, X[14][31:0], $encoding);
|
|
51
|
+
write_memory(32, virtual_address - 56, X[15][31:0], $encoding);
|
|
52
|
+
write_memory(32, virtual_address - 60, X[16][31:0], $encoding);
|
|
53
|
+
write_memory(32, virtual_address - 64, X[17][31:0], $encoding);
|
|
54
|
+
write_memory(32, virtual_address - 68, X[28][31:0], $encoding);
|
|
55
|
+
write_memory(32, virtual_address - 72, X[29][31:0], $encoding);
|
|
56
|
+
write_memory(32, virtual_address - 76, X[30][31:0], $encoding);
|
|
57
|
+
write_memory(32, virtual_address - 80, X[31][31:0], $encoding);
|
|
58
58
|
X[8] = X[2];
|
|
59
59
|
X[2] = X[2] - 96;
|
|
60
60
|
CSR[mstatus].MIE = 1'b1;
|
|
@@ -32,28 +32,28 @@ operation(): |
|
|
|
32
32
|
XReg qc_mcause_val = CSR[qc.mcause].sw_read();
|
|
33
33
|
XReg reserved_val = 0;
|
|
34
34
|
if (CSR[mnstatus].NMIE == 1'b1) {
|
|
35
|
-
write_memory
|
|
35
|
+
write_memory(32, virtual_address - 4, mepc_val, $encoding);
|
|
36
36
|
} else {
|
|
37
|
-
write_memory
|
|
37
|
+
write_memory(32, virtual_address - 4, mnepc_val, $encoding);
|
|
38
38
|
}
|
|
39
|
-
write_memory
|
|
40
|
-
write_memory
|
|
41
|
-
write_memory
|
|
42
|
-
write_memory
|
|
43
|
-
write_memory
|
|
44
|
-
write_memory
|
|
45
|
-
write_memory
|
|
46
|
-
write_memory
|
|
47
|
-
write_memory
|
|
48
|
-
write_memory
|
|
49
|
-
write_memory
|
|
50
|
-
write_memory
|
|
51
|
-
write_memory
|
|
52
|
-
write_memory
|
|
53
|
-
write_memory
|
|
54
|
-
write_memory
|
|
55
|
-
write_memory
|
|
56
|
-
write_memory
|
|
57
|
-
write_memory
|
|
39
|
+
write_memory(32, virtual_address - 8, X[ 8][31:0], $encoding);
|
|
40
|
+
write_memory(32, virtual_address - 12, qc_mcause_val, $encoding);
|
|
41
|
+
write_memory(32, virtual_address - 16, X[ 1][31:0], $encoding);
|
|
42
|
+
write_memory(32, virtual_address - 20, reserved_val, $encoding);
|
|
43
|
+
write_memory(32, virtual_address - 24, X[ 5][31:0], $encoding);
|
|
44
|
+
write_memory(32, virtual_address - 28, X[ 6][31:0], $encoding);
|
|
45
|
+
write_memory(32, virtual_address - 32, X[ 7][31:0], $encoding);
|
|
46
|
+
write_memory(32, virtual_address - 36, X[10][31:0], $encoding);
|
|
47
|
+
write_memory(32, virtual_address - 40, X[11][31:0], $encoding);
|
|
48
|
+
write_memory(32, virtual_address - 44, X[12][31:0], $encoding);
|
|
49
|
+
write_memory(32, virtual_address - 48, X[13][31:0], $encoding);
|
|
50
|
+
write_memory(32, virtual_address - 52, X[14][31:0], $encoding);
|
|
51
|
+
write_memory(32, virtual_address - 56, X[15][31:0], $encoding);
|
|
52
|
+
write_memory(32, virtual_address - 60, X[16][31:0], $encoding);
|
|
53
|
+
write_memory(32, virtual_address - 64, X[17][31:0], $encoding);
|
|
54
|
+
write_memory(32, virtual_address - 68, X[28][31:0], $encoding);
|
|
55
|
+
write_memory(32, virtual_address - 72, X[29][31:0], $encoding);
|
|
56
|
+
write_memory(32, virtual_address - 76, X[30][31:0], $encoding);
|
|
57
|
+
write_memory(32, virtual_address - 80, X[31][31:0], $encoding);
|
|
58
58
|
X[8] = X[2];
|
|
59
59
|
X[2] = X[2] - 96;
|
|
@@ -27,30 +27,30 @@ encoding:
|
|
|
27
27
|
operation(): |
|
|
28
28
|
XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
|
|
29
29
|
XReg virtual_address = virtual_address_sp + 96;
|
|
30
|
-
XReg prev_retpc = read_memory
|
|
31
|
-
XReg qc_mcause_val = read_memory
|
|
30
|
+
XReg prev_retpc = read_memory(32, virtual_address - 4, $encoding);
|
|
31
|
+
XReg qc_mcause_val = read_memory(32, virtual_address - 12, $encoding);
|
|
32
32
|
Bits<1> nmie_val = CSR[mnstatus].NMIE;
|
|
33
33
|
XReg qc_mcause_prev_val = CSR[qc.mcause].sw_read();
|
|
34
34
|
XReg qc_mcause_nmip_excp_mask = (32'b1 << 24) | (32'b1 << 25);
|
|
35
35
|
XReg qc_mcause_new_val = (qc_mcause_val & ~qc_mcause_nmip_excp_mask) | (qc_mcause_prev_val & qc_mcause_nmip_excp_mask);
|
|
36
36
|
CSR[qc.mcause].sw_write(qc_mcause_new_val);
|
|
37
|
-
X[ 8] = read_memory
|
|
38
|
-
X[ 1] = read_memory
|
|
39
|
-
X[ 5] = read_memory
|
|
40
|
-
X[ 6] = read_memory
|
|
41
|
-
X[ 7] = read_memory
|
|
42
|
-
X[10] = read_memory
|
|
43
|
-
X[11] = read_memory
|
|
44
|
-
X[12] = read_memory
|
|
45
|
-
X[13] = read_memory
|
|
46
|
-
X[14] = read_memory
|
|
47
|
-
X[15] = read_memory
|
|
48
|
-
X[16] = read_memory
|
|
49
|
-
X[17] = read_memory
|
|
50
|
-
X[28] = read_memory
|
|
51
|
-
X[29] = read_memory
|
|
52
|
-
X[30] = read_memory
|
|
53
|
-
X[31] = read_memory
|
|
37
|
+
X[ 8] = read_memory(32, virtual_address - 8, $encoding);
|
|
38
|
+
X[ 1] = read_memory(32, virtual_address - 16, $encoding);
|
|
39
|
+
X[ 5] = read_memory(32, virtual_address - 24, $encoding);
|
|
40
|
+
X[ 6] = read_memory(32, virtual_address - 28, $encoding);
|
|
41
|
+
X[ 7] = read_memory(32, virtual_address - 32, $encoding);
|
|
42
|
+
X[10] = read_memory(32, virtual_address - 36, $encoding);
|
|
43
|
+
X[11] = read_memory(32, virtual_address - 40, $encoding);
|
|
44
|
+
X[12] = read_memory(32, virtual_address - 44, $encoding);
|
|
45
|
+
X[13] = read_memory(32, virtual_address - 48, $encoding);
|
|
46
|
+
X[14] = read_memory(32, virtual_address - 52, $encoding);
|
|
47
|
+
X[15] = read_memory(32, virtual_address - 56, $encoding);
|
|
48
|
+
X[16] = read_memory(32, virtual_address - 60, $encoding);
|
|
49
|
+
X[17] = read_memory(32, virtual_address - 64, $encoding);
|
|
50
|
+
X[28] = read_memory(32, virtual_address - 68, $encoding);
|
|
51
|
+
X[29] = read_memory(32, virtual_address - 72, $encoding);
|
|
52
|
+
X[30] = read_memory(32, virtual_address - 76, $encoding);
|
|
53
|
+
X[31] = read_memory(32, virtual_address - 80, $encoding);
|
|
54
54
|
X[2] = X[2] + 96;
|
|
55
55
|
if (nmie_val == 1'b1) {
|
|
56
56
|
XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12);
|
|
@@ -41,6 +41,6 @@ operation(): |
|
|
|
41
41
|
XReg num_words = X[rs2][4:0];
|
|
42
42
|
raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + num_words) > 32);
|
|
43
43
|
for (U32 i = 0; i < num_words; i++) {
|
|
44
|
-
X[rd + i] = read_memory
|
|
44
|
+
X[rd + i] = read_memory(32, vaddr, $encoding);
|
|
45
45
|
vaddr = vaddr + 4;
|
|
46
46
|
}
|
|
@@ -40,6 +40,6 @@ operation(): |
|
|
|
40
40
|
XReg vaddr = X[rs1] + imm;
|
|
41
41
|
raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + length) > 32);
|
|
42
42
|
for (U32 i = 0; i < length; i++) {
|
|
43
|
-
X[rd + i] = read_memory
|
|
43
|
+
X[rd + i] = read_memory(32, vaddr, $encoding);
|
|
44
44
|
vaddr = vaddr + 4;
|
|
45
45
|
}
|
|
@@ -41,6 +41,6 @@ operation(): |
|
|
|
41
41
|
XReg num_words = X[rs2][4:0];
|
|
42
42
|
raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + num_words) > 32);
|
|
43
43
|
for (U32 i = 0; i < num_words; i++) {
|
|
44
|
-
write_memory
|
|
44
|
+
write_memory(32, vaddr, X[rs3 + i], $encoding);
|
|
45
45
|
vaddr = vaddr + 4;
|
|
46
46
|
}
|
|
@@ -40,6 +40,6 @@ operation(): |
|
|
|
40
40
|
XReg vaddr = X[rs1] + imm;
|
|
41
41
|
raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + length) > 32);
|
|
42
42
|
for (U32 i = 0; i < length; i++) {
|
|
43
|
-
write_memory
|
|
43
|
+
write_memory(32, vaddr, X[rs3 + i], $encoding);
|
|
44
44
|
vaddr = vaddr + 4;
|
|
45
45
|
}
|
|
@@ -33,8 +33,11 @@ published as GitHub releases under the tag `schemas/<schema_name>/<version>`.
|
|
|
33
33
|
|===
|
|
34
34
|
| Version | Published URL
|
|
35
35
|
|
|
36
|
-
| 0.1 (current)
|
|
37
|
-
| https://riscv.github.io/riscv-unified-db/schemas/
|
|
36
|
+
| 0.1 (current for all schemas except csr_schema.json)
|
|
37
|
+
| https://riscv.github.io/riscv-unified-db/schemas/ext_schema.json/v0.1/ext_schema.json (example)
|
|
38
|
+
|
|
39
|
+
| 0.2 (current for csr_schema.json)
|
|
40
|
+
| https://riscv.github.io/riscv-unified-db/schemas/csr_schema.json/v0.2/csr_schema.json
|
|
38
41
|
|===
|
|
39
42
|
|
|
40
43
|
== Schema Identification (`$id`)
|
|
@@ -43,7 +46,7 @@ Every schema file contains a top-level `$id` key whose value is the version
|
|
|
43
46
|
string (e.g. `v0.1`). Source data files reference schemas using the bare
|
|
44
47
|
filename (e.g. `csr_schema.json#`). When data files are resolved, the
|
|
45
48
|
`$schema` field is rewritten to include the version prefix
|
|
46
|
-
(e.g. `v0.
|
|
49
|
+
(e.g. `v0.2/csr_schema.json#`) so that the resolved file records the exact
|
|
47
50
|
schema version used.
|
|
48
51
|
|
|
49
52
|
[source,json]
|
|
@@ -1,6 +1,6 @@
|
|
|
1
1
|
{
|
|
2
2
|
"$schema": "http://json-schema.org/draft-07/schema#",
|
|
3
|
-
"$id": "v0.
|
|
3
|
+
"$id": "v0.2",
|
|
4
4
|
"title": "CSR description",
|
|
5
5
|
"description": "A CSR register specification",
|
|
6
6
|
"$defs": {
|
|
@@ -57,10 +57,6 @@
|
|
|
57
57
|
"sw_write_ast": {
|
|
58
58
|
"type": "object"
|
|
59
59
|
},
|
|
60
|
-
"legal?(csr_value)": {
|
|
61
|
-
"type": "string",
|
|
62
|
-
"description": "Function that returns whether or not an attempted value for the field is legal. The csr_value parameter is the *entire* attempted CSR write value. Fields within the attempted write value can be accessed with a dot operator (e.g., csr_value.SXL, csr_value.VGEIN, ...)"
|
|
63
|
-
},
|
|
64
60
|
"description": {
|
|
65
61
|
"$ref": "schema_defs.json#/$defs/spec_text",
|
|
66
62
|
"description": "Function of the field"
|
|
@@ -50,17 +50,6 @@ fields:
|
|
|
50
50
|
} else {
|
|
51
51
|
return csr_value.MNPP;
|
|
52
52
|
}
|
|
53
|
-
legal?(csr_value): |
|
|
54
|
-
if (csr_value.MNPP == 2'b01 && !implemented?(ExtensionName::S)) {
|
|
55
|
-
return false;
|
|
56
|
-
} else if (csr_value.MNPP == 2'b00 && !implemented?(ExtensionName::U)) {
|
|
57
|
-
return false;
|
|
58
|
-
} else if (csr_value.MNPP == 2'b10) {
|
|
59
|
-
# never a valid value
|
|
60
|
-
return false;
|
|
61
|
-
} else {
|
|
62
|
-
return true;
|
|
63
|
-
}
|
|
64
53
|
MNPELP:
|
|
65
54
|
location: 9
|
|
66
55
|
description: |
|
|
@@ -145,8 +145,6 @@ fields:
|
|
|
145
145
|
return CsrFieldType::RWR;
|
|
146
146
|
}
|
|
147
147
|
reset_value: UNDEFINED_LEGAL
|
|
148
|
-
legal?(csr_value): |
|
|
149
|
-
return csr_value.VGEIN <= NUM_EXTERNAL_GUEST_INTERRUPTS;
|
|
150
148
|
sw_write(csr_value): |
|
|
151
149
|
if (csr_value.VGEIN <= NUM_EXTERNAL_GUEST_INTERRUPTS) {
|
|
152
150
|
return csr_value.VGEIN;
|
|
@@ -109,8 +109,6 @@ fields:
|
|
|
109
109
|
|
|
110
110
|
# fall-through; write the intended value
|
|
111
111
|
return csr_value.F;
|
|
112
|
-
legal?(csr_value): |
|
|
113
|
-
return !(csr_value.F == 0 && csr_value.D == 1);
|
|
114
112
|
G:
|
|
115
113
|
location: 6
|
|
116
114
|
description: |
|
|
@@ -195,8 +193,6 @@ fields:
|
|
|
195
193
|
|
|
196
194
|
# fall-through; write the intended value
|
|
197
195
|
return csr_value.Q;
|
|
198
|
-
legal?(csr_value): |
|
|
199
|
-
return !(csr_value.Q == 1 && csr_value.D == 0);
|
|
200
196
|
S:
|
|
201
197
|
location: 18
|
|
202
198
|
description: |
|
|
@@ -433,17 +433,6 @@ fields:
|
|
|
433
433
|
} else {
|
|
434
434
|
return csr_value.MPP;
|
|
435
435
|
}
|
|
436
|
-
legal?(csr_value): |
|
|
437
|
-
if (csr_value.MPP == 2'b01 && !implemented?(ExtensionName::S)) {
|
|
438
|
-
return false;
|
|
439
|
-
} else if (csr_value.MPP == 2'b00 && !implemented?(ExtensionName::U)) {
|
|
440
|
-
return false;
|
|
441
|
-
} else if (csr_value.MPP == 2'b10) {
|
|
442
|
-
# never a valid value
|
|
443
|
-
return false;
|
|
444
|
-
} else {
|
|
445
|
-
return true;
|
|
446
|
-
}
|
|
447
436
|
VS:
|
|
448
437
|
location: 10-9
|
|
449
438
|
long_name: Vector context Status
|
|
@@ -524,8 +513,6 @@ fields:
|
|
|
524
513
|
} else {
|
|
525
514
|
return csr_value.SPP;
|
|
526
515
|
}
|
|
527
|
-
legal?(csr_value): |
|
|
528
|
-
return csr_value.SPP != 2'b10;
|
|
529
516
|
MPIE:
|
|
530
517
|
location: 7
|
|
531
518
|
long_name: M-mode Previous Interrupt Enable
|
|
@@ -212,12 +212,6 @@ Custom Write Function::
|
|
|
212
212
|
| *description* | Function implementing custom write behavior for the CSR. The csr_value parameter is the *entire* attempted CSR write value. Fields within the attempted write value can be accessed with a dot operator (e.g., csr_value.SXL, csr_value.VGEIN, ...)
|
|
213
213
|
|===
|
|
214
214
|
|
|
215
|
-
|===
|
|
216
|
-
| *key* | legal?(csr_value)
|
|
217
|
-
| *value type* | String of IDL code that returns whether or not an attempted write is legal
|
|
218
|
-
| *description* | Function that returns whether or not an attempted value for the field is legal. The csr_value parameter is the *entire* attempted CSR write value. Fields within the attempted write value can be accessed with a dot operator (e.g., csr_value.SXL, csr_value.VGEIN, ...)
|
|
219
|
-
|===
|
|
220
|
-
|
|
221
215
|
Alias::
|
|
222
216
|
|
|
223
217
|
Some fields are aliases for another field, often in a different CSR. THe `alias` key is used to indicate that this field just points somewhere else.
|
|
@@ -56,7 +56,7 @@ operation(): |
|
|
|
56
56
|
|
|
57
57
|
if (xlen() == 32) {
|
|
58
58
|
if (implemented?(ExtensionName::Zclsd)) {
|
|
59
|
-
Bits<64> val = read_memory
|
|
59
|
+
Bits<64> val = read_memory(64, X[creg2reg(xs1)] + imm, $encoding);
|
|
60
60
|
X[creg2reg(xd)] = val[31:0];
|
|
61
61
|
X[creg2reg(xd + 1)] = val[63:32];
|
|
62
62
|
} else {
|
|
@@ -64,7 +64,7 @@ operation(): |
|
|
|
64
64
|
}
|
|
65
65
|
} else {
|
|
66
66
|
XReg virtual_address = X[creg2reg(xs1)] + imm;
|
|
67
|
-
X[creg2reg(xd)] = sext(read_memory
|
|
67
|
+
X[creg2reg(xd)] = sext(read_memory(64, virtual_address, $encoding), 64);
|
|
68
68
|
}
|
|
69
69
|
|
|
70
70
|
# SPDX-SnippetBegin
|
|
@@ -38,7 +38,7 @@ operation(): |
|
|
|
38
38
|
|
|
39
39
|
XReg virtual_address = X[creg2reg(xs1)] + imm;
|
|
40
40
|
|
|
41
|
-
X[creg2reg(xd)] = sext(read_memory
|
|
41
|
+
X[creg2reg(xd)] = sext(read_memory(32, virtual_address, $encoding), 32);
|
|
42
42
|
|
|
43
43
|
# SPDX-SnippetBegin
|
|
44
44
|
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
|
|
@@ -58,10 +58,10 @@ operation(): |
|
|
|
58
58
|
if (xlen() == 32) {
|
|
59
59
|
if (implemented?(ExtensionName::Zclsd)) {
|
|
60
60
|
Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]};
|
|
61
|
-
write_memory
|
|
61
|
+
write_memory(64, virtual_address, data, $encoding);
|
|
62
62
|
} else {
|
|
63
63
|
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
64
64
|
}
|
|
65
65
|
} else {
|
|
66
|
-
write_memory
|
|
66
|
+
write_memory(64, virtual_address, X[creg2reg(xs2)], $encoding);
|
|
67
67
|
}
|
|
@@ -54,10 +54,10 @@ operation(): |
|
|
|
54
54
|
if (xlen() == 32) {
|
|
55
55
|
if (implemented?(ExtensionName::Zclsd)) {
|
|
56
56
|
Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]};
|
|
57
|
-
write_memory
|
|
57
|
+
write_memory(64, virtual_address, data, $encoding);
|
|
58
58
|
} else {
|
|
59
59
|
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
60
60
|
}
|
|
61
61
|
} else {
|
|
62
|
-
write_memory
|
|
62
|
+
write_memory(64, virtual_address, X[creg2reg(xs2)], $encoding);
|
|
63
63
|
}
|
|
@@ -35,10 +35,10 @@ operation(): |
|
|
|
35
35
|
|
|
36
36
|
XReg virtual_address = X[xs1] + $signed(imm);
|
|
37
37
|
|
|
38
|
-
Bits<32> sp_value = read_memory
|
|
38
|
+
Bits<32> sp_value = read_memory(32, virtual_address, $encoding);
|
|
39
39
|
|
|
40
40
|
if (implemented?(ExtensionName::D)) {
|
|
41
|
-
f[fd] = nan_box
|
|
41
|
+
f[fd] = nan_box(32, 64, sp_value);
|
|
42
42
|
} else {
|
|
43
43
|
f[fd] = sp_value;
|
|
44
44
|
}
|