soc_maker 0.1.1

data/spec/core_inst_spec.rb

@@ -0,0 +1,169 @@
+###############################################################
+#   
+#  File:      core_inst_spec.rb
+#
+#  Author:    Christian Hättich
+#
+#  Project:   System-On-Chip Maker
+#
+#  Target:    Linux / Windows / Mac
+#
+#  Language:  ruby
+#
+#
+###############################################################
+#
+#
+#   Copyright (C) 2014  Christian Hättich  - feddischson [ at ] opencores.org
+#
+#   This program is free software: you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation, either version 3 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#
+###############################################################
+#
+#   Description:
+#
+#
+#
+#
+###############################################################
+require_relative( 'spec_helper' )
+
+
+describe SOCMaker::CoreInst do
+
+
+  before( :each ) do
+
+    p1 = SOCMaker::IfcPort.new( "p1", 12 )
+    @core = SOCMaker::CoreDef.new( "mycore", "mycore,rel1", "core_top",
+        "interfaces"      => { "my_ifc" =>  SOCMaker::IfcDef.new( "i1", "i1,v1", 0, { m_p1: p1 } ) },
+        "inst_parameters" => { "param1".to_sym => SOCMaker::Parameter.new( "integer" )             } )
+
+
+    ifc_spc = SOCMaker::IfcSpc.new( "Ifc 1", "i1,v1", 'ports' => { p1:{dir:1} } )
+    SOCMaker::lib.add_ifc( ifc_spc )
+    SOCMaker::lib.add_core( @core )
+  end
+
+  after( :each ) do
+    SOCMaker::lib.clear
+  end
+
+
+  describe "#initialize" do
+
+    it "raises an error, if the type is nil" do 
+       # add with nil type
+       expect{  SOCMaker::CoreInst.new( nil, { "aparameter".to_sym => 4 } ) } .
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    context "creates an instance" do
+       # add with mycore,rel1 type
+       subject{ SOCMaker::CoreInst.new( "mycore,rel1", { "aparameter".to_sym => 4 } ) }
+       its( :class ) { should == SOCMaker::CoreInst }
+       its( :type  ) { should == :"mycore,rel1" }
+    end
+
+    it "raises an error, if parameters are not given as hash" do
+       expect{  SOCMaker::CoreInst.new( "mycorerel1", "not a hash"  ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+
+    it "raises an error, if parameters are given, which doesn't exist in the definition" do
+       expect{ inst = SOCMaker::CoreInst.new( "mycore,rel1", { "aparameter".to_sym => 4 } )
+               inst.consistence_check }.
+        to raise_error( SOCMaker::ERR::ConsistenceError )
+    end
+
+    it "auto-completes generics with default values" do
+
+       inst = SOCMaker::CoreInst.new( "mycore,rel1", {}  )
+       inst.consistence_check
+       expect( inst.params[ :param1 ] ).to be == 0
+    end
+  end
+
+  describe "object handling, en-decoding:" do
+
+    it "should be possible to encode and decode a core instance" do
+      o1 = SOCMaker::CoreInst.new( "mycore,rel1", {}  )
+      yaml_str = o1.to_yaml
+      o2 = YAML::load( yaml_str )
+      expect( o1 ).to eq( o2 )
+    end
+
+    it "should return false for two non-equal objects" do
+      o1 = SOCMaker::CoreInst.new( "mycore,rel1" )
+      o1.consistence_check
+      o2 = Marshal::load(Marshal.dump(o1))
+      o2.type = ( o2.type.to_s + "X" ).to_sym
+      expect( o2 == o1 ).to eq( false )
+      o2 = Marshal::load(Marshal.dump(o1))
+      o2.params[ :param1 ] = 1
+      expect( o2 == o1 ).to eq( false )
+    end
+  end
+
+
+
+  describe "#consistence_check" do
+    it "raises an error, if a core def doesn't exist" do
+      expect{ SOCMaker::CoreInst.new( "mycore,rel2", {} ).consistence_check }
+        .to raise_error( SOCMaker::ERR::ConsistenceError ) 
+    end
+  end
+
+
+  describe "#core_definition" do
+    before( :each ) do
+      @soc = SOCMaker::SOCDef.new( "mysoc", "mysoc,v1", "soc_top" )
+      SOCMaker::lib.add_core( @soc )
+      @inst = SOCMaker::CoreInst.new( "mycore,rel1", {}  )
+      @inst.consistence_check
+    end
+  end
+
+
+
+  describe "#port_length" do
+    before( :each ) do
+      p1 = SOCMaker::IfcPort.new( "p1", 21 )
+
+      @inst1 = SOCMaker::CoreInst.new( "mycore,rel1", {}  )
+      @soc = SOCMaker::SOCDef.new( "mysoc", "mysoc,v1", "soc_top",
+        "interfaces"      => { "my_ifc" =>  SOCMaker::IfcDef.new( "i1", "i1,v1", 0, { m_p1: p1 } ) }, 
+        "cores"           => { core_inst: @inst1 } )
+
+      SOCMaker::lib.add_core( @soc )
+
+      @inst2 = SOCMaker::CoreInst.new( "mysoc,v1", {}  )
+      @inst2.consistence_check
+    end
+
+    it "returns the correct port length" do
+      expect( @inst1.port_length( "my_ifc", :p1 ) ).to be( 12 )
+    end
+
+  end
+
+
+
+end
+
+
+
+# vim: noai:ts=2:sw=2

data/spec/hdl_file_spec.rb

@@ -0,0 +1,154 @@
+###############################################################
+#   
+#  File:      hdl_file_spec.rb
+#
+#  Author:    Christian Hättich
+#
+#  Project:   System-On-Chip Maker
+#
+#  Target:    Linux / Windows / Mac
+#
+#  Language:  ruby
+#
+#
+###############################################################
+#
+#
+#   Copyright (C) 2014  Christian Hättich  - feddischson [ at ] opencores.org
+#
+#   This program is free software: you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation, either version 3 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#
+###############################################################
+#
+#   Description:
+#     Test specification for SOCMaker::HDLFile
+#
+#
+#
+###############################################################
+require_relative( 'spec_helper' )
+
+require "yaml_examples.rb"
+
+
+
+describe SOCMaker::HDLFile do
+
+  include_context "yaml examples"
+
+  describe "#initialize" do
+
+    context "with the minimum number of input argumnets" do
+      subject{ SOCMaker::HDLFile.new( "./path/to/file.vhd" ) }
+       its( :class )        { should == SOCMaker::HDLFile }
+       its( :use_syn )      { should == true }
+       its( :use_mod_sim )  { should == true }
+       its( :use_sys_sim )  { should == true }
+    end
+
+
+    it "raise an error, if an invalid file type is provided" do
+       expect { SOCMaker::HDLFile.new( "./path/to/invalid_file.vhx" ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if no path is given (empty string)" do
+       expect { SOCMaker::HDLFile.new( "" ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if no path is given (nil)" do
+       expect { SOCMaker::HDLFile.new( nil ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if path is not a string" do
+       expect { SOCMaker::HDLFile.new( 3 ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if use_syn is not boolean" do
+       expect { SOCMaker::HDLFile.new( "./path/to/file.vhd", "use_syn" => "not boolean" ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if use_sys_sim is not boolean" do
+       expect { SOCMaker::HDLFile.new( "./path/to/file.vhd", "use_sys_sim" => "not boolean" ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "raise an error, if use_mod_sim is not boolean" do
+       expect { SOCMaker::HDLFile.new( "./path/to/file.vhd", "use_mod_sim" => "not boolean" ) }.
+       to raise_error( SOCMaker::ERR::InitError )
+    end
+
+    it "auto-detect verilog files" do
+       o = SOCMaker::HDLFile.new( "./path/to/file.v" )
+       expect( o.type ).to eq( "verilog" )
+    end
+
+    it "auto-detect vhdl files" do
+       o = SOCMaker::HDLFile.new( "./path/to/file.vhd" )
+       expect( o.type ).to  eq( "vhdl" )
+    end
+
+    %w[ use_syn use_sys_sim use_mod_sim  ].each do |m|
+      it "raise an error if #{m} is not false or true" do
+        expect { SOCMaker::HDLFile.new( "./path/to/file.vhd", { m => 4 } ) }.
+        to raise_error( SOCMaker::ERR::InitError )
+      end
+    end
+
+
+  end
+
+  describe "object handling" do
+    describe "via SOCMaker::from_s" do
+      it "raise an error, if the HDL file info is nil" do
+         expect { SOCMaker::from_s( @F_MIN_YAML_FIlE_NIL ) }.
+         to raise_error( SOCMaker::ERR::InitError )
+      end
+
+      it "raise an error, if an invalid file type is given" do
+         expect { SOCMaker::from_s( @F_YAML_FILE_TYPE ) }.
+         to raise_error( SOCMaker::ERR::InitError )
+      end
+    end
+
+
+    it "return false for two non-equal objects" do
+      o1 = SOCMaker::HDLFile.new( "./path/to/file.vhd" )
+      o2 = Marshal::load(Marshal.dump(o1))
+      o2.use_syn = !o2.use_syn
+      expect( o2 == o1 ).to be( false )
+    end
+
+    it "be possible to encode and decode a HDL file object" do
+      o1 = SOCMaker::HDLFile.new( "./path/to/file.vhd", 
+          'use_syn' => false,
+          'use_mod_sim' => false,
+          'use_sys_sim' => false )
+      yaml_str = o1.to_yaml
+      o2 = YAML::load( yaml_str )
+      expect( o1 ).to eq( o2 )
+    end
+  end
+
+
+end                                        
+
+
+# vim: noai:ts=2:sw=2
+

data/spec/hdl_parser_spec.rb

@@ -0,0 +1,201 @@
+###############################################################
+#   
+#  File:      hd_parser_spec.rb
+#
+#  Author:    Christian Hättich
+#
+#  Project:   System-On-Chip Maker
+#
+#  Target:    Linux / Windows / Mac
+#
+#  Language:  ruby
+#
+#
+###############################################################
+#
+#
+#   Copyright (C) 2015  Christian Hättich  - feddischson [ at ] opencores.org
+#
+#   This program is free software: you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation, either version 3 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#
+###############################################################
+#
+#   Description:
+#     Test specification for SOCMaker::HDLFile
+#
+#
+#
+###############################################################
+require_relative( 'spec_helper' )
+
+
+
+
+describe SOCMaker::HDLParser do
+
+  before( :each ){ @inst = SOCMaker::HDLParser.instance }
+
+
+  describe "#get_extension" do
+    it "returns '.vhd' for a vhdl file" do
+      expect( @inst.get_extension( "./some/file.vhd" ) ).to eq( ".vhd")
+    end
+    it "returns '.v' for a verilog file" do
+      expect( @inst.get_extension( "./some/file.v" ) ).to eq( ".v")
+    end
+  end
+
+
+  describe "#parse_core" do
+    it "should return a string" do
+      result = SOCMaker::HDLParser.instance.parse_core( 
+          "spec/test_soc_lib/cores/core_A_rel1/core_a.vhd",
+          "spec/test_soc_lib/cores/core_A_rel1/*.vhd"  )  
+      expect( result ).to be_a( String )
+    end
+  end
+
+
+end
+
+
+describe SOCMaker::VHDLParser do
+
+  before( :each ){ 
+    @inst = SOCMaker::VHDLParser.instance 
+    @example = "
+ entity mux is
+    generic(
+        w1 : natural := 4;
+        w2 : natural := 4;
+        wx : std_logic_vector( 123-1 downto 0 )
+        );
+    port (
+        din_0   :in  std_logic_vector( 4-1 downto 0 ); -- first input
+        din_1   :in  std_logic_vector( w1-1 downto 0 ); -- second input
+        sel     :in  std_logic;-- Select input 1
+        mux_out :out std_logic_vector( 4-1-3+2+1 downto 0 ); -- Mux output
+        sel2    :    std_logic;                   -- Select input 2 (unused at the moment)
+        sel3    :    std_logic_vector( 3 to 5 )   -- Select input 3 (unused at the moment)
+    );
+  end entity;
+
+architecture behavior of mux is
+
+begin
+    with (sel) select
+    mux_out <= din_0 when '0',
+               din_1 when others;
+end architecture; "
+
+  }
+
+  describe "#parse_toplevel" do
+
+    it "returns extracts all necessary information" do
+
+      result = @inst.parse_toplevel( @example )
+      expect( result ).to eq(
+          {  :name    =>"mux", 
+             :generic => { 
+      "w1"     => { :type=>"natural",          :name=>"w1", :default=>"4"},
+      "w2"     => { :type=>"natural",          :name=>"w2", :default=>"4"}, 
+      "wx"     => { :type=>"std_logic_vector", :name=>"wx", :range=>" 123-1 downto 0 "}
+      }, 
+             :port    => 
+  { "din_0"  => { :name=>"din_0",   :type=>"std_logic_vector", :direction=>"in",  :range=>" 4-1 downto 0 "}, 
+    "din_1"  => { :name=>"din_1",   :type=>"std_logic_vector", :direction=>"in",  :range=>" w1-1 downto 0 "}, 
+    "sel"    => { :name=>"sel",     :type=>"std_logic",        :direction=>"in"  }, 
+    "sel2"   => { :name=>"sel2",    :type=>"std_logic",        :direction=>"in"  }, 
+    "mux_out"=> { :name=>"mux_out", :type=>"std_logic_vector", :direction=>"out", :range=>" 4-1-3+2+1 downto 0 "},
+   "sel3"    => { :name=>"sel3",    :type=>"std_logic_vector", :direction=>"in",  :range=>" 3 to 5 "}  } } )
+
+    end
+
+    it "should extract the length information" do
+
+      result = @inst.parse_toplevel( @example )
+      result = @inst.extract_length( result )
+
+      expect( result[ :port][ "din_0" ][ :length ]  ).to equal( 4 )
+      expect( result[ :port][ "din_1" ][ :length ]  ).to eq( "w1" )
+      expect( result[ :port][ "sel" ][ :length ]  ).to equal( 1 )
+      expect( result[ :port][ "sel2" ][ :length ]  ).to equal( 1 )
+      expect( result[ :port][ "sel3" ][ :length ]  ).to equal( 3 )
+      expect( result[ :port][ "mux_out" ]  [ :length ]  ).to equal( 4 )
+
+    end
+
+  end
+
+end
+
+describe SOCMaker::VerilogParser do
+
+  before( :each ){ 
+    @inst = SOCMaker::VerilogParser.instance 
+    @example = "
+
+module  mux( din_0,  din_1,  sel, mux_out );
+ parameter w1 = 4;
+ parameter w2 = 4;
+ input   [4-1 : 0]   din_0; 
+ input   [w1-1 : 0]    din_1;
+ input                sel;
+ input                sel2;
+ input   [4:3]        sel3;
+ output  [4-1:0]      mux_out;
+
+ wire                 mux_out;
+ assign mux_out = (sel) ? din_1 : din_0;
+ endmodule "
+  }
+
+    it "returns extracts all necessary information" do
+
+      result = @inst.parse_toplevel( @example )
+      expect( result ).to eq(
+      {   :name    => "mux", 
+          :generic => {  
+      "w1"  => { :name    =>"w1", :default =>"4", :type=>"integer"}, 
+      "w2"  => { :name    =>"w2", :default =>"4", :type=>"integer"} }, 
+          :port=>{ "din_0"   => { :name=>"din_0", :dir=>"in", :range=>"4-1 : 0" }, 
+                   "din_1"   => { :name=>"din_1", :dir=>"in", :range=>"w1-1 : 0"  }, 
+                   "sel"     => { :name=>"sel",  :dir=>"in"}, 
+                   "sel2"    => { :name=>"sel2", :dir=>"in"}, 
+                   "sel3"    => { :name=>"sel3", :dir=>"in", :range=>"4:3"}, 
+                   "mux_out" => { :name=>"mux_out", :dir=>"out", :range=>"4-1:0"} } } )
+    end
+
+
+
+
+    it "should extract the length information" do
+
+      result = @inst.parse_toplevel( @example )
+      result = @inst.extract_length( result )
+
+
+      expect( result[ :port][ "din_0" ][ :length ]  ).to equal( 4 )
+      expect( result[ :port][ "din_1" ][ :length ]  ).to eq( "w1" )
+      expect( result[ :port][ "sel" ][ :length ]  ).to equal( 1 )
+      expect( result[ :port][ "sel2" ][ :length ]  ).to equal( 1 )
+      expect( result[ :port][ "sel3" ][ :length ]  ).to equal( 2 )
+      expect( result[ :port][ "mux_out" ]  [ :length ]  ).to equal( 4 )
+
+    end
+
+
+end