soc_maker 0.1.1

data/lib/soc_maker/hdl_file.rb

@@ -0,0 +1,166 @@
+###############################################################
+#   
+#  File:      hdl_file.rb
+#
+#  Author:    Christian Hättich
+#
+#  Project:   System-On-Chip Maker
+#
+#  Target:    Linux / Windows / Mac
+#
+#  Language:  ruby
+#
+#
+###############################################################
+#
+#
+#   Copyright (C) 2014  Christian Hättich  - feddischson [ at ] opencores.org
+#
+#   This program is free software: you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation, either version 3 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#
+###############################################################
+#
+#   Description:
+#
+#
+#
+#
+###############################################################
+
+module SOCMaker
+
+
+
+
+# A small classes, used to group information
+# and to verify, auto-correct and auto-complete
+# this information:
+# The class represents an high-level-description (HDL) file.
+# The two supported file-types are *.vhdl and *.v, whose information
+# is stored in #type ('verilog' or 'vhdl').
+# A #path is mandatory and defines, where the file is located.
+# In addition, is is used for auto-detecting the file-type (if not given).
+# There are three flags:
+# - #use_syn      (use in synthesis)
+# - #use_sys_sim  (use in system simulation)
+# - #use_mod_sim  (use in module simulation)
+# These flags are not used at the moment and reserved for 
+# future implementation.
+class HDLFile
+  include ERR
+
+  # file path of the HDL file
+  attr_accessor :path 
+
+  # synthesis flag
+  attr_accessor :use_syn 
+
+  # system simulation flag (reserved and not used)
+  attr_accessor :use_sys_sim 
+
+  # modul simulation flag (reserved and not used)
+  attr_accessor :use_mod_sim
+
+  # type of this hdl file: 'vhdl' or 'verilog'
+  attr_accessor :type
+
+  # The constructor gets the path as mandatory argument.
+  # Everything else can be passed with optional arguments
+  def initialize( path, optional = {} )
+    init_with( { 'path' => path }.merge( optional ) )
+  end
+
+  # 
+  # Encoder method (to yaml)
+  #
+  # +coder+:: An instance of the Psych::Coder to encode this class to a YAML file
+  #
+  def encode_with( coder )
+    init_error_if !coder.is_a?( Psych::Coder ), 
+                'coder is not given as Psych::Coder'
+    %w[ path use_syn use_sys_sim use_mod_sim type ].
+      each { |v| coder[ v ] = instance_variable_get "@#{v}" }
+  end
+
+  #
+  # Initialization method (from yaml)
+  #
+  # +coder+:: An instance of the Psych::Coder to init this class from a YAML file
+  #
+  #
+  def init_with( coder )
+
+    init_error_if !( coder.is_a?( Hash ) || coder.is_a?( Psych::Coder ) ), 
+                'coder is not given as Hash neither as Psych::Coder'
+
+    # check path
+    init_error 'no filepath specified' if coder[ 'path' ] == nil
+    @path = coder[ 'path' ]
+    init_error 'path must be of type string' if !@path.is_a?( String )
+
+    # auto-complete to 'true'
+    @use_syn      = coder[ 'use_syn'     ] || true
+    @use_sys_sim  = coder[ 'use_sys_sim' ] || true
+    @use_mod_sim  = coder[ 'use_mod_sim' ] || true
+
+    # ensure, that the thee use... fields are boolean
+    init_error 'use_syn field must be true of false' if !!@use_syn != @use_syn
+    init_error 'use_sys_sim field must be true of false' if !!@use_sys_sim != @use_sys_sim
+    init_error 'use_mod_sim field must be true of false' if !!@use_mod_sim != @use_mod_sim 
+
+    # if the file-type is not given, we try to auto-detect it
+    #   *.vhd  ->  vhdl
+    #   *.v    ->  verilog
+    #   (see conf[ :vhdl_file_regex ] and 
+    #        conf[ :verilog_file_regex ] )
+    if  coder[ 'type' ] == nil 
+      if @path =~ SOCMaker::conf[ :vhdl_file_regex ]
+        SOCMaker::logger.warn "Auto-detected vhdl file type for #{ @path }"
+        @type = 'vhdl'
+      elsif @path =~ SOCMaker::conf[ :verilog_file_regex ]
+        SOCMaker::logger.warn "Auto-detected verilog file type for #{ @path }"
+        @type = 'verilog'
+      else
+        init_error "Cant auto-detect file type for #{path}" 
+      end
+    else
+      # if the file-type is given, ensure, that it is either 'vhdl' or 'verilog'
+      init_error  "The type must be 'vhdl' or 'verilog'",
+        instance: @path,
+        field:    'type' if !SOCMaker::conf[ :hdl_type_regex ].match( coder[ 'type' ] )
+      @type = coder[ 'type' ]
+    end
+
+  end
+
+
+
+  #
+  # Equality operator
+  #
+  def ==(o)
+    o.class           == self.class         &&
+    o.path            == self.path          &&
+    o.use_syn         == self.use_syn       &&
+    o.use_sys_sim     == self.use_sys_sim   &&
+    o.use_mod_sim     == self.use_mod_sim   &&
+    o.type            == self.type         
+  end
+
+end
+end
+
+# vim: noai:ts=2:sw=2
+

data/lib/soc_maker/hdl_parser.rb

@@ -0,0 +1,431 @@
+###############################################################
+#   
+#  File:      hdl_parser.rb
+#
+#  Author:    Christian Hättich
+#
+#  Project:   System-On-Chip Maker
+#
+#  Target:    Linux / Windows / Mac
+#
+#  Language:  ruby
+#
+#
+###############################################################
+#
+#
+#   Copyright (C) 2015  Christian Hättich  - feddischson [ at ] opencores.org
+#
+#   This program is free software: you can redistribute it and/or modify
+#   it under the terms of the GNU General Public License as published by
+#   the Free Software Foundation, either version 3 of the License, or
+#   (at your option) any later version.
+#
+#   This program is distributed in the hope that it will be useful,
+#   but WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#   GNU General Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License
+#   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#
+###############################################################
+#
+#   Description:
+#   
+#
+#
+###############################################################
+
+
+require 'singleton'
+require 'pathname'
+
+module SOCMaker
+
+class HDLParser
+
+
+  include ERR
+
+  # to organize it as singleton
+  #
+  include Singleton
+
+
+  def initialize
+
+  end
+
+
+  def get_content( file )
+    return File.open( file, "r"){ |f| f.read }
+  end
+
+
+  def get_extension( file )
+    return File.extname( file )
+  end
+
+  def get_all_hdl_files( files )
+    hdl_files = []
+    files.each { |f|   hdl_files += Dir[f] }
+    return hdl_files
+  end
+
+
+
+
+  def parse_core( top_file, files, package_file = nil )
+
+    files = [ files ] if not files.kind_of?( Array )
+
+    #
+    # read and parse toplevel file
+    #
+    content = get_content( top_file )
+    if get_extension( top_file ) == ".v" 
+      toplevel = VerilogParser.instance.parse_toplevel( content )
+      toplevel = VerilogParser.instance.extract_length( toplevel )
+    elsif get_extension( top_file ) == ".vhd"
+      toplevel = VHDLParser.instance.parse_toplevel( content )
+      toplevel = VHDLParser.instance.extract_length( toplevel )
+    end
+
+    #
+    # read and parse package file
+    #
+    #   -> not yet supported
+    # 
+    if package_file != nil
+      content = get_content( package_file )
+      if get_extension( package_file ) == ".v"
+        package = VerilogParser.instance.parse_package( content )
+      elsif get_extension( top_file ) == ".vhd"
+        package = VerilogParser.instance.parse_package( content )
+      end
+    else
+      package = {}
+    end
+
+
+    #
+    # get all HDL files
+    #
+    hdl_files = get_all_hdl_files( files )
+
+
+
+    #
+    # Prepare options and ports hashes
+    #
+    options = { 'inst_parameters' => {},
+                'hdlfiles'        => {},
+                'interfaces'      => {} }
+
+    if toplevel.has_key?( :generic )
+      toplevel[ :generic ].values.each do | v |
+        options[ 'inst_parameters' ][ v[:name] ] = Parameter.new( v[ :type ], default: v[ :default ] )
+      end
+    end
+
+    ports = {}
+    if toplevel.has_key?( :port )
+      toplevel[ :port ].values.each do | v |
+        ports[ v[ :name ] ] = IfcPort.new( v[:name], v[:length]  )
+      end
+    end
+
+    ifc_name = toplevel[:name].to_s + '_ifc'
+    ifc_id   = ifc_name + ",v1"
+    options[ 'interfaces'][ ifc_name ] = IfcDef.new( ifc_name, ifc_id, 0, ports )
+
+    hdl_files.each do | f |
+      f_opts = {}
+      name = Pathname.new( f ).basename( ".*" ).to_s
+      if name.include? "sim"
+        f_opts[ 'use_syn'     => false ]
+        f_opts[ 'use_mod_sim' => true  ]
+      else
+        f_opts[ 'use_syn'     => true  ]
+        f_opts[ 'use_mod_sim' => false ]
+      end
+      options[ 'hdlfiles' ][ name ] = HDLFile.new( f, f_opts )
+    end
+
+    #
+    # create new core
+    #
+    d = CoreDef.new( toplevel[ :name ], 
+                     toplevel[ :name ]+",v1",
+                     toplevel[ :name ], options)
+
+
+
+    # dump the result
+    return SOCMaker::to_yaml_s( d )
+
+  end
+
+
+end
+
+
+class VerilogParser < HDLParser
+
+  include ERR
+
+  # to organize it as singleton
+  #
+  include Singleton
+
+
+  def initialize
+
+  end
+
+  def parse_toplevel( data )
+    # remove all newlines
+    data = data.gsub( "\n", " " )
+
+    # empty result hash
+    result = {}
+
+    module_regex    = /\s*module\s+(\w+)*\s*\(.*?\);/
+    port_regex      = /(input|output)\s*(\[([\d\w\-\:\s]*)\s*\])?\s*(\w*);/
+    parameter_regex = /parameter\s*(\w*)\s*=\s(.*?);/
+
+
+    # extract module name
+    if m = module_regex.match( data )
+      result[ :name ] = m[1]
+    else
+      result[ :name ] = "unknown"
+    end
+
+    #
+    # extract parameteters
+    #
+    parameters = data.scan( parameter_regex )
+    result[ :generic ] = {}
+    parameters.each do |port|
+
+      result[ :generic ][ port[0] ] = { name: port[0], default: port[1], type: "integer" }
+
+    end
+
+    #
+    # extract ports
+    #
+    ports = data.scan( port_regex )
+    result[ :port ] = {}
+    ports.each do |port|
+      result[ :port ][ port[3] ] = { name: port[3] }
+
+
+      if port[0] 
+        if port[0] == "input"
+          result[ :port ][ port[3] ][ :dir ] = "in"
+        elsif port[0] == "output"
+          result[ :port ][ port[3] ][ :dir ] = "out"
+        else
+          result[ :port ][ port[3] ][ :dir ] = "in"
+        end
+      end
+
+
+      if port[ 2 ]
+        result[ :port ][ port[ 3 ] ][ :range ] = port[ 2 ]
+      end
+
+    end
+
+    return result
+  end
+
+  def extract_length( content )
+
+    numeric_regex   = /^\s*([0-9+\-\s]+):([0-9+\-\s]+)/
+    parameter_regex = /^\s*(\D[\D\d]+)\s*-\s*1\s*:\s*0/
+
+
+    content[ :port ].values.each do |port|
+      if port[ :range ]
+        if m = numeric_regex.match( port[ :range ] )
+          tmp = " ( #{ m[1] } ) - ( #{ m[ 2 ] }  ) + 1 "
+          begin
+            port[ :length ] =  eval( tmp )
+          rescue Exception
+            port[:length] = 'UNKNOWN'
+          end
+
+        elsif m = parameter_regex.match( port[ :range ] )
+            port[:length] = m[1]
+        end
+      else
+        port[ :length ] = 1
+      end
+    end
+    return content
+  end
+
+  def parse_package( data )
+    result = {}
+   #data.split("\n").each do |line|
+   #end
+    return result
+  end
+
+
+end
+
+
+
+class VHDLParser < HDLParser
+
+  include ERR
+
+  # to organize it as singleton
+  #
+  include Singleton
+
+  def initialize
+
+  end
+
+
+
+  def parse_toplevel( data )
+
+    # remove all newlines
+    data = data.gsub( "\n", " " )
+
+    # empty result hash
+    result = {}
+
+    # thee expressions to parse the entity header
+    entity_regex = /
+       entity\s+(\S+)\s+is\s+                           #   entity   <name>    is
+       (generic\s*\(\s*(.*?)\s*\)\s*;)?\s*              #   generic   (   <generic-infos>   )  ;  --> optional
+       (port\s*\(\s*(.*?)\s*\)\s*;)?\s*                 #   port (   <port-info>  )   ;           --> optional
+        end\s*(entity)?\s*(\S*)\s*;                     #   end  <entity-name --> optional>  ;
+       /x
+
+    generic_regex = /\s*(\S+)\s*:\s*(\w+)\s*(\((.*?)\))?\s*(:\s*=\s([\d\w]+))?/
+    port_regex    = /\s*(\S+)\s*:\s*(in|out)?\s*(\w+)\s*(\((.*?)\))?\s*/
+
+
+
+    # match the whole entity header, 
+    #     -> extract name
+    #     -> extract generics
+    #     -> extract ports
+    if m = entity_regex.match( data )
+
+
+      result[ :name ] = m[1]
+
+
+      # if there are generics:
+      #      -> process each
+      if m[3]
+        result[ :generic ] = {}
+
+        m[3].split(";").each do |x|
+          if match = generic_regex.match( x )
+
+            result[ :generic ][ match[1] ] = { 
+                type:     match[2],
+                name:     match[1]
+            }
+            if( match[3])
+              result[ :generic ][ match[1] ][ :range ] = match[4]
+            end
+            if( match[5])
+              result[ :generic ][ match[1] ][ :default ] = match[6]
+            end
+          end
+        end
+      end
+
+      # if there are ports
+      #   -> process each
+      #
+      if m[5]
+        result[ :port ] = {}
+        m[5].split(";").each do |x|
+          if port_match = port_regex.match( x )
+            result[ :port ][ port_match[ 1 ] ] = {
+              name: port_match[1],
+              type: port_match[3]
+            }
+            if( port_match[2])
+              result[ :port ][ port_match[1] ][ :direction] =  port_match[2]
+            else
+              result[ :port ][ port_match[1] ][ :direction] =  "in"
+            end
+
+
+            if( port_match[ 4 ])
+              result[ :port ][ port_match[1] ][ :range] =  port_match[5]
+            end
+
+          end
+        end
+      end
+    end
+    return result;
+  end
+
+  def extract_length( content )
+
+    content[ :port ].values.each do |v|
+
+      v[:length ] = 'UNKNOWN'
+
+      if v[:range]
+
+        numeric_regex     = /^\s*([0-9+\-\s]+)(to|downto+)([0-9+\-\s]+)/i
+        parameter_regex   = /^\s*(\D[\D\d]+)\s*-\s*1\s*(to|downto+)\s+0/i
+
+        if m = numeric_regex.match( v[:range] )
+
+          if( m[2].downcase == "downto")
+            tmp = "(" + m[1]  + ") - ( "  + m[3] + ") + 1" 
+          else
+            tmp = "(" + m[3]  + ") - ( "  + m[1] + ") + 1" 
+          end
+          begin
+            v[ :length ] =  eval( tmp )
+          rescue Exception
+            v[:length] = 'UNKNOWN'
+          end
+
+        elsif m = parameter_regex.match( v[ :range ] )
+          v[:length] = m[1]
+        end
+      else
+        v[ :length ] = 1
+      end
+    end
+    return content
+  end
+
+
+  def parse_package( data )
+    result = {}
+   #const_regex = /^\s*constant\s*(\S+)\s*:\s*(\w+)\s*(\(.*?\))?\s*:\s*=\s*"?([\d\w]+)"?/i
+   #data.split("\n").each do |line|
+   #end
+    return result
+  end
+
+end
+
+
+
+end
+
+
+