seal 0.1.0

data/mpg123/src/libmpg123/synth_stereo_neon_s32.S

@@ -0,0 +1,247 @@
+/*
+	synth_stereo_neon_s32: ARM NEON optimized synth (stereo specific, 32-bit output version)
+
+	copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
+	see COPYING and AUTHORS files in distribution or http://mpg123.org
+	initially written by Taihei Monma
+*/
+
+#include "mangle.h"
+
+#define WINDOW r0
+#define B0L r1
+#define B0R r2
+#define SAMPLES r3
+
+/*
+	int synth_1to1_s32_s_neon_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
+	return value: number of clipped samples
+*/
+
+	.text
+	.globl ASM_NAME(synth_1to1_s32_s_neon_asm)
+	ALIGN4
+ASM_NAME(synth_1to1_s32_s_neon_asm):
+	push		{r4-r7, lr}
+	vpush		{q4-q7}
+	ldr			r4, [sp, #84]
+	mov			r7, sp
+	sub			sp, sp, #16
+	bic			sp, #0xff
+	
+	add			WINDOW, WINDOW, #64
+	sub			WINDOW, WINDOW, r4, lsl #2
+
+	mov			r4, #4
+	mov			r5, #128
+	mov			r6, #64
+.Loop_start_1:
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vmul.f32	q12, q0, q4
+	vmul.f32	q13, q0, q6
+	vmul.f32	q14, q2, q8
+	vmul.f32	q15, q2, q10
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	sub			WINDOW, WINDOW, #96
+	sub			B0L, B0L, #32
+	sub			B0R, B0R, #32
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]!
+	vld1.32		{q10,q11}, [B0R, :128]!
+	vmla.f32	q12, q0, q4
+	vmla.f32	q13, q0, q6
+	vmla.f32	q14, q2, q8
+	vmla.f32	q15, q2, q10
+	add			WINDOW, WINDOW, #96
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vpadd.f32	d26, d28, d29
+	vpadd.f32	d27, d30, d31
+	vmvn.i32	q14, #0xb9000000
+	vld1.32		{q15}, [sp, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vacgt.f32	q14, q12, q14
+	vcvt.s32.f32	q13, q12, #16
+	vshr.u32	q14, q14, #31
+	vst1.32		{q13}, [SAMPLES]!
+	vadd.i32	q14, q14, q15
+	vst1.32		{q14}, [sp, :128]
+	vmul.f32	q12, q0, q4
+	vmul.f32	q13, q0, q6
+	vmul.f32	q14, q2, q8
+	vmul.f32	q15, q2, q10
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	sub			WINDOW, WINDOW, #96
+	sub			B0L, B0L, #32
+	sub			B0R, B0R, #32
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]!
+	vld1.32		{q10,q11}, [B0R, :128]!
+	vmla.f32	q12, q0, q4
+	vmla.f32	q13, q0, q6
+	vmla.f32	q14, q2, q8
+	vmla.f32	q15, q2, q10
+	add			WINDOW, WINDOW, #96
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vpadd.f32	d26, d28, d29
+	vpadd.f32	d27, d30, d31
+	vmvn.i32	q14, #0xb9000000
+	vld1.32		{q15}, [sp, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vacgt.f32	q14, q12, q14
+	vcvt.s32.f32	q13, q12, #16
+	vshr.u32	q14, q14, #31
+	vst1.32		{q13}, [SAMPLES]!
+	vadd.i32	q14, q14, q15
+	vst1.32		{q14}, [sp, :128]
+
+	subs		r4, r4, #1
+	bne			.Loop_start_1
+
+	mov			r4, #4
+	mov			r6, #-64
+.Loop_start_2:
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vmul.f32	q12, q0, q4
+	vmul.f32	q13, q0, q6
+	vmul.f32	q14, q2, q8
+	vmul.f32	q15, q2, q10
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	sub			WINDOW, WINDOW, #96
+	add			B0L, B0L, #96
+	add			B0R, B0R, #96
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vmla.f32	q12, q0, q4
+	vmla.f32	q13, q0, q6
+	vmla.f32	q14, q2, q8
+	vmla.f32	q15, q2, q10
+	add			WINDOW, WINDOW, #96
+	sub			B0L, B0L, #96
+	sub			B0R, B0R, #96
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vpadd.f32	d26, d28, d29
+	vpadd.f32	d27, d30, d31
+	vmvn.i32	q14, #0xb9000000
+	vld1.32		{q15}, [sp, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vacgt.f32	q14, q12, q14
+	vcvt.s32.f32	q13, q12, #16
+	vshr.u32	q14, q14, #31
+	vst1.32		{q13}, [SAMPLES]!
+	vadd.i32	q14, q14, q15
+	vst1.32		{q14}, [sp, :128]
+	vmul.f32	q12, q0, q4
+	vmul.f32	q13, q0, q6
+	vmul.f32	q14, q2, q8
+	vmul.f32	q15, q2, q10
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	sub			WINDOW, WINDOW, #96
+	add			B0L, B0L, #96
+	add			B0R, B0R, #96
+	vld1.32		{q0,q1}, [WINDOW], r5
+	vld1.32		{q2,q3}, [WINDOW]
+	vld1.32		{q4,q5}, [B0L, :128], r6
+	vld1.32		{q6,q7}, [B0R, :128], r6
+	vld1.32		{q8,q9}, [B0L, :128]
+	vld1.32		{q10,q11}, [B0R, :128]
+	vmla.f32	q12, q0, q4
+	vmla.f32	q13, q0, q6
+	vmla.f32	q14, q2, q8
+	vmla.f32	q15, q2, q10
+	add			WINDOW, WINDOW, #96
+	sub			B0L, B0L, #96
+	sub			B0R, B0R, #96
+	vmla.f32	q12, q1, q5
+	vmla.f32	q13, q1, q7
+	vmla.f32	q14, q3, q9
+	vmla.f32	q15, q3, q11
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vpadd.f32	d26, d28, d29
+	vpadd.f32	d27, d30, d31
+	vmvn.i32	q14, #0xb9000000
+	vld1.32		{q15}, [sp, :128]
+	vpadd.f32	d24, d24, d25
+	vpadd.f32	d25, d26, d27
+	vacgt.f32	q14, q12, q14
+	vcvt.s32.f32	q13, q12, #16
+	vshr.u32	q14, q14, #31
+	vst1.32		{q13}, [SAMPLES]!
+	vadd.i32	q14, q14, q15
+	vst1.32		{q14}, [sp, :128]
+
+	subs		r4, r4, #1
+	bne			.Loop_start_2
+
+	vld1.32		{q0}, [sp, :128]
+	vpadd.i32	d0, d0, d1
+	vpadd.i32	d0, d0, d0
+	vmov.32		r0, d0[0]
+
+	mov			sp, r7
+	vpop		{q4-q7}
+	pop			{r4-r7, pc}

data/mpg123/src/libmpg123/synth_stereo_sse_accurate.S

@@ -0,0 +1,508 @@
+/*
+	synth_stereo_sse_accurate: SSE optimized synth (stereo specific, MPEG-compliant 16bit output version)
+
+	copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
+	see COPYING and AUTHORS files in distribution or http://mpg123.org
+	initially written by Taihei Monma
+*/
+
+#include "mangle.h"
+
+/* real *window; */
+#define WINDOW %ebx
+/* real *b0l; */
+#define B0L %edx
+/* real *b0r; */
+#define B0R %esi
+/* real *samples; */
+#define SAMPLES %edi
+
+#define TEMP(n) (12+16*n)(%esp)
+#define MMREG_CLIP %mm7
+
+/*
+	int synth_1to1_s_sse_accurate_asm(real *window, real *b0l, real *b0r, short *samples, int bo1);
+	return value: number of clipped samples
+*/
+
+#ifndef __APPLE__
+	.section	.rodata
+#else
+	.data
+#endif
+	ALIGN32
+ASM_NAME(maxmin_s16):
+	.long   1191181824 /* 32767.0 */
+	.long   1191181824
+	.long   1191181824
+	.long   1191181824
+	.long   -956301312 /* -32768.0 */
+	.long   -956301312
+	.long   -956301312
+	.long   -956301312
+	.text
+	ALIGN16
+.globl ASM_NAME(synth_1to1_s_sse_accurate_asm)
+ASM_NAME(synth_1to1_s_sse_accurate_asm):
+	pushl		%ebp
+	movl		%esp, %ebp
+	andl		$-16, %esp
+	subl		$128, %esp
+	pushl		%ebx
+	pushl		%esi
+	pushl		%edi
+	
+	pxor		MMREG_CLIP, MMREG_CLIP
+	
+	movl		8(%ebp), WINDOW
+	movl		12(%ebp), B0L
+	movl		16(%ebp), B0R
+	movl		20(%ebp), SAMPLES
+	movl		24(%ebp), %eax
+	shll		$2, %eax
+	
+	leal		64(WINDOW), WINDOW
+	subl		%eax, WINDOW
+
+	movl		$4, %ecx
+	
+	ALIGN16
+Loop_start_1:
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(0)
+	movaps		%xmm4, TEMP(4)
+	
+	leal		128(WINDOW), WINDOW
+	leal		64(B0L), B0L
+	leal		64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(1)
+	movaps		%xmm4, TEMP(5)
+	
+	leal		128(WINDOW), WINDOW
+	leal		64(B0L), B0L
+	leal		64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(2)
+	movaps		%xmm4, TEMP(6)
+	
+	leal		128(WINDOW), WINDOW
+	leal		64(B0L), B0L
+	leal		64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, %xmm7
+	movaps		%xmm4, TEMP(7)
+	
+	leal		128(WINDOW), WINDOW
+	leal		64(B0L), B0L
+	leal		64(B0R), B0R
+	
+	movaps		TEMP(0), %xmm4
+	movaps		TEMP(1), %xmm5
+	movaps		TEMP(2), %xmm6
+	movaps		%xmm4, %xmm0
+	movaps		%xmm6, %xmm1
+	unpcklps	%xmm5, %xmm4
+	unpcklps	%xmm7, %xmm6
+	unpckhps	%xmm5, %xmm0
+	unpckhps	%xmm7, %xmm1
+	movaps		%xmm4, %xmm2
+	movaps		%xmm0, %xmm3
+	movlhps		%xmm6, %xmm4
+	movhlps		%xmm2, %xmm6
+	movlhps		%xmm1, %xmm0
+	movhlps		%xmm3, %xmm1
+	subps		%xmm6, %xmm4
+	subps		%xmm1, %xmm0
+	addps		%xmm4, %xmm0
+	movaps		%xmm0, %xmm2
+	
+	movaps		TEMP(4), %xmm4
+	movaps		TEMP(5), %xmm5
+	movaps		TEMP(6), %xmm6
+	movaps		TEMP(7), %xmm7
+	movaps		%xmm4, %xmm0
+	movaps		%xmm6, %xmm1
+	unpcklps	%xmm5, %xmm4
+	unpcklps	%xmm7, %xmm6
+	unpckhps	%xmm5, %xmm0
+	unpckhps	%xmm7, %xmm1
+	movaps		%xmm2, %xmm5
+	movaps		%xmm4, %xmm2
+	movaps		%xmm0, %xmm3
+	movlhps		%xmm6, %xmm4
+	movhlps		%xmm2, %xmm6
+	movlhps		%xmm1, %xmm0
+	movhlps		%xmm3, %xmm1
+	subps		%xmm6, %xmm4
+	subps		%xmm1, %xmm0
+	addps		%xmm4, %xmm0
+	
+	movaps		%xmm5, %xmm1
+	movaps		%xmm5, %xmm2
+	movaps		%xmm0, %xmm3
+	movaps		%xmm0, %xmm4
+	cmpnleps	ASM_NAME(maxmin_s16), %xmm1
+	cmpltps		ASM_NAME(maxmin_s16)+16, %xmm2
+	cmpnleps	ASM_NAME(maxmin_s16), %xmm3
+	cmpltps		ASM_NAME(maxmin_s16)+16, %xmm4
+	cvtps2pi	%xmm5, %mm0
+	cvtps2pi	%xmm0, %mm1
+	movhlps		%xmm5, %xmm5
+	movhlps		%xmm0, %xmm0
+	cvtps2pi	%xmm5, %mm2
+	cvtps2pi	%xmm0, %mm3
+	packssdw	%mm2, %mm0
+	packssdw	%mm3, %mm1
+	movq		%mm0, %mm2
+	punpcklwd	%mm1, %mm0
+	punpckhwd	%mm1, %mm2
+	movq		%mm0, (SAMPLES)
+	movq		%mm2, 8(SAMPLES)
+	
+	cvtps2pi	%xmm1, %mm2
+	cvtps2pi	%xmm3, %mm3
+	movhlps		%xmm1, %xmm1
+	movhlps		%xmm3, %xmm3
+	cvtps2pi	%xmm1, %mm4
+	cvtps2pi	%xmm3, %mm5
+	packssdw	%mm4, %mm2
+	packssdw	%mm5, %mm3
+	psrlw		$15, %mm2
+	psrlw		$15, %mm3
+	cvtps2pi	%xmm2, %mm0
+	cvtps2pi	%xmm4, %mm1
+	movhlps		%xmm2, %xmm2
+	movhlps		%xmm4, %xmm4
+	cvtps2pi	%xmm2, %mm4
+	cvtps2pi	%xmm4, %mm5
+	packssdw	%mm4, %mm0
+	packssdw	%mm5, %mm1
+	psrlw		$15, %mm0
+	psrlw		$15, %mm1
+	paddw		%mm3, %mm2
+	paddw		%mm1, %mm0
+	paddw		%mm2, %mm0
+	paddw		%mm0, MMREG_CLIP
+	
+	leal		16(SAMPLES), SAMPLES
+	decl		%ecx
+	jnz			Loop_start_1
+	
+	movl		$4, %ecx
+	
+	ALIGN16
+Loop_start_2:
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(0)
+	movaps		%xmm4, TEMP(4)
+	
+	leal		128(WINDOW), WINDOW
+	leal		-64(B0L), B0L
+	leal		-64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(1)
+	movaps		%xmm4, TEMP(5)
+	
+	leal		128(WINDOW), WINDOW
+	leal		-64(B0L), B0L
+	leal		-64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, TEMP(2)
+	movaps		%xmm4, TEMP(6)
+	
+	leal		128(WINDOW), WINDOW
+	leal		-64(B0L), B0L
+	leal		-64(B0R), B0R
+	
+	movups		(WINDOW), %xmm0
+	movups		16(WINDOW), %xmm1
+	movups		32(WINDOW), %xmm2
+	movups		48(WINDOW), %xmm3
+	movaps		%xmm0, %xmm4
+	movaps		%xmm1, %xmm5
+	movaps		%xmm2, %xmm6
+	movaps		%xmm3, %xmm7
+	mulps		0(B0L), %xmm0
+	mulps		16(B0L), %xmm1
+	mulps		32(B0L), %xmm2
+	mulps		48(B0L), %xmm3
+	mulps		0(B0R), %xmm4
+	mulps		16(B0R), %xmm5
+	mulps		32(B0R), %xmm6
+	mulps		48(B0R), %xmm7
+	addps		%xmm1, %xmm0
+	addps		%xmm3, %xmm2
+	addps		%xmm5, %xmm4
+	addps		%xmm7, %xmm6
+	addps		%xmm2, %xmm0
+	addps		%xmm6, %xmm4
+	movaps		%xmm0, %xmm7
+	movaps		%xmm4, TEMP(7)
+	
+	leal		128(WINDOW), WINDOW
+	leal		-64(B0L), B0L
+	leal		-64(B0R), B0R
+	
+	movaps		TEMP(0), %xmm4
+	movaps		TEMP(1), %xmm5
+	movaps		TEMP(2), %xmm6
+	movaps		%xmm4, %xmm0
+	movaps		%xmm6, %xmm1
+	unpcklps	%xmm5, %xmm4
+	unpcklps	%xmm7, %xmm6
+	unpckhps	%xmm5, %xmm0
+	unpckhps	%xmm7, %xmm1
+	movaps		%xmm4, %xmm2
+	movaps		%xmm0, %xmm3
+	movlhps		%xmm6, %xmm4
+	movhlps		%xmm2, %xmm6
+	movlhps		%xmm1, %xmm0
+	movhlps		%xmm3, %xmm1
+	addps		%xmm6, %xmm4
+	addps		%xmm1, %xmm0
+	addps		%xmm4, %xmm0
+	movaps		%xmm0, %xmm2
+	
+	movaps		TEMP(4), %xmm4
+	movaps		TEMP(5), %xmm5
+	movaps		TEMP(6), %xmm6
+	movaps		TEMP(7), %xmm7
+	movaps		%xmm4, %xmm0
+	movaps		%xmm6, %xmm1
+	unpcklps	%xmm5, %xmm4
+	unpcklps	%xmm7, %xmm6
+	unpckhps	%xmm5, %xmm0
+	unpckhps	%xmm7, %xmm1
+	movaps		%xmm2, %xmm5
+	movaps		%xmm4, %xmm2
+	movaps		%xmm0, %xmm3
+	movlhps		%xmm6, %xmm4
+	movhlps		%xmm2, %xmm6
+	movlhps		%xmm1, %xmm0
+	movhlps		%xmm3, %xmm1
+	addps		%xmm6, %xmm4
+	addps		%xmm1, %xmm0
+	addps		%xmm4, %xmm0
+	
+	movaps		%xmm5, %xmm1
+	movaps		%xmm5, %xmm2
+	movaps		%xmm0, %xmm3
+	movaps		%xmm0, %xmm4
+	cmpnleps	ASM_NAME(maxmin_s16), %xmm1
+	cmpltps		ASM_NAME(maxmin_s16)+16, %xmm2
+	cmpnleps	ASM_NAME(maxmin_s16), %xmm3
+	cmpltps		ASM_NAME(maxmin_s16)+16, %xmm4
+	cvtps2pi	%xmm5, %mm0
+	cvtps2pi	%xmm0, %mm1
+	movhlps		%xmm5, %xmm5
+	movhlps		%xmm0, %xmm0
+	cvtps2pi	%xmm5, %mm2
+	cvtps2pi	%xmm0, %mm3
+	packssdw	%mm2, %mm0
+	packssdw	%mm3, %mm1
+	movq		%mm0, %mm2
+	punpcklwd	%mm1, %mm0
+	punpckhwd	%mm1, %mm2
+	movq		%mm0, (SAMPLES)
+	movq		%mm2, 8(SAMPLES)
+	
+	cvtps2pi	%xmm1, %mm2
+	cvtps2pi	%xmm3, %mm3
+	movhlps		%xmm1, %xmm1
+	movhlps		%xmm3, %xmm3
+	cvtps2pi	%xmm1, %mm4
+	cvtps2pi	%xmm3, %mm5
+	packssdw	%mm4, %mm2
+	packssdw	%mm5, %mm3
+	psrlw		$15, %mm2
+	psrlw		$15, %mm3
+	cvtps2pi	%xmm2, %mm0
+	cvtps2pi	%xmm4, %mm1
+	movhlps		%xmm2, %xmm2
+	movhlps		%xmm4, %xmm4
+	cvtps2pi	%xmm2, %mm4
+	cvtps2pi	%xmm4, %mm5
+	packssdw	%mm4, %mm0
+	packssdw	%mm5, %mm1
+	psrlw		$15, %mm0
+	psrlw		$15, %mm1
+	paddw		%mm3, %mm2
+	paddw		%mm1, %mm0
+	paddw		%mm2, %mm0
+	paddw		%mm0, MMREG_CLIP
+	
+	leal		16(SAMPLES), SAMPLES
+	decl		%ecx
+	jnz			Loop_start_2
+	
+	pshufw		$0xee, MMREG_CLIP, %mm0
+	paddw		MMREG_CLIP, %mm0
+	pshufw		$0x55, %mm0, %mm1
+	paddw		%mm1, %mm0
+	movd		%mm0, %eax
+	andl		$0xffff, %eax
+	
+	popl		%edi
+	popl		%esi
+	popl		%ebx
+	movl		%ebp, %esp
+	popl		%ebp
+	
+	emms
+	
+	ret
+
+NONEXEC_STACK