ruby-vpi 19.0.0 → 20.0.0

data/lib/ruby-vpi/runner_boot_loader.rb

@@ -20,18 +20,27 @@ rescue LoadError
 end
 
 require 'ruby-vpi'
-require 'ruby-vpi/util'
 require 'ruby-vpi/core'
 
+# copy Ruby output into simulator's log file
+  [STDOUT, STDERR].each do |stream|
+    class << stream #:nodoc:
+      alias __write__ write
 
-designName = ENV['RUBYVPI_BOOT_TARGET']
+      def write aString
+        s = aString.to_s
+
+        VPI.vpi_printf(s)
+        return s.length
+      end
+    end
+  end
 
 # set up code coverage analysis
   if RubyVPI::USE_COVERAGE
     require 'ruby-vpi/rcov'
 
-    outFile = "#{designName}_coverage.txt"
-
+    outFile = "coverage.txt"
     RubyVPI::Coverage.attach do |analysis|
       begin
         File.open(outFile, 'w') do |f|
@@ -75,10 +84,7 @@ designName = ENV['RUBYVPI_BOOT_TARGET']
   if RubyVPI::USE_PROFILER
     require 'ruby-prof'
 
-    RubyProf.start
-
-    outFile = "#{designName}_profile.txt"
-
+    outFile = "profile.txt"
     at_exit do
       result = RubyProf.stop
       printer = RubyProf::GraphPrinter.new(result)
@@ -88,60 +94,12 @@ designName = ENV['RUBYVPI_BOOT_TARGET']
       end
     end
 
+    RubyProf.start
     RubyVPI.say "performance analysis is enabled; results stored in #{outFile}"
   end
 
-# load the design under test
-  class Object
-    include VPI
-  end
-
-  unless designHandle = vpi_handle_by_name(designName, nil)
-    raise "cannot access the design under test: #{designName.inspect}"
-  end
-
-  # create a module to wrap the DUT, so that inner classes and modules
-  # and constants defined in the design.rb and proto.rb files are
-  # accessible in spec.rb through the namespace resolution operator (::)
-  design = Module.new do
-    @@design = designHandle
-
-    # delegate all instance methods to the DUT
-    instance_eval do
-      def method_missing(*a, &b) #:nodoc:
-        @@design.__send__(*a, &b)
-      end
-
-      # pass these methods to method_missing
-      undef to_s
-      undef inspect
-      undef type
-      undef respond_to?
-    end
-
-    # make module parameters available as constants
-    @@design[VpiParameter, VpiLocalParam].each do |var|
-      const_set(var.name.to_ruby_const_name, var.get_value(VpiIntVal))
-    end
-
-    # methods in design.rb & proto.rb must execute on the DUT
-    @@design.extend(self)
-  end
-
-  Kernel.const_set(designName.to_ruby_const_name, design)
-
-# load the user's test bench
-  RubyVPI::Scheduler.start
-
-  # design file
-  f = "#{designName}_design.rb"
-  design.module_eval(File.read(f), f) if File.exist? f
-
-  # prototype file
+# set up the prototyping environment
   if RubyVPI::USE_PROTOTYPE
-    f = "#{designName}_proto.rb"
-    design.module_eval(File.read(f), f) if File.exist? f
-
     VPI.module_eval do
       def vpi_register_cb *args #:nodoc:
         warn "vpi_register_cb: callbacks are ignored when prototype is enabled"
@@ -151,5 +109,11 @@ designName = ENV['RUBYVPI_BOOT_TARGET']
     RubyVPI.say 'prototype is enabled'
   end
 
-  # specification file
-  require "#{designName}_spec.rb"
+# make VPI functions available globally
+  class Object
+    include VPI
+  end
+
+# load the user-defined test loader
+  RubyVPI::Scheduler.start
+  require $0

data/lib/ruby-vpi/runner_proxy.rb

@@ -13,11 +13,7 @@
 
 # invoke each test runner with the command-line args
   at_exit do
-    FileList['**/*.rake'].each do |path|
-      parent, runner = File.dirname(path), File.basename(path)
-
-      cd parent do
-        sh 'rake', '-f', runner, *ARGV
-      end
+    FileList['**/*.rake'].each do |runner|
+      sh 'rake', '-f', runner, *ARGV
     end
   end

data/lib/ruby-vpi.rb

@@ -4,25 +4,67 @@
 # See the file named LICENSE for details.
 
 module RubyVPI
-  PROJECT_ID      = 'ruby-vpi'
-  PROJECT_NAME    = 'Ruby-VPI'
-  PROJECT_URL     = "http://#{PROJECT_ID}.rubyforge.org"
-  PROJECT_SUMMARY = "Ruby interface to IEEE 1364-2005 Verilog VPI"
-  PROJECT_DETAIL  = "#{PROJECT_NAME} is a #{PROJECT_SUMMARY} and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby."
+  Project = {
+    :name    => 'ruby-vpi',
+    :version => '20.0.0',
+    :release => '2008-01-27',
+    :website => "http://ruby-vpi.rubyforge.org",
+    :home    => File.expand_path(File.join(File.dirname(__FILE__), '..'))
+  }
 
-  Simulator = Struct.new(:name, :compiler_args, :linker_args)
+  Simulator = Struct.new(:id, :name, :compiler_args, :linker_args)
 
   # List of supported Verilog simulators.
-  SIMULATORS = {
-    :cver   => Simulator.new('GPL Cver',        '-DPRAGMATIC_CVER',   ''),
-    :ivl    => Simulator.new('Icarus Verilog',  '-DICARUS_VERILOG',   ''),
-    :vcs    => Simulator.new('Synopsys VCS',    '-DSYNOPSYS_VCS',     ''),
-    :vsim   => Simulator.new('Mentor Modelsim', '-DMENTOR_MODELSIM',  ''),
-    :ncsim  => Simulator.new('Cadence NC-Sim',  '-DCADENCE_NCSIM',    ''),
-  }
+  SIMULATORS = [
+    Simulator.new(:cver,  'GPL Cver',        '-DPRAGMATIC_CVER',  ''),
+    Simulator.new(:ivl,   'Icarus Verilog',  '-DICARUS_VERILOG',  ''),
+    Simulator.new(:ncsim, 'Cadence NC-Sim',  '-DCADENCE_NCSIM',   ''),
+    Simulator.new(:vcs,   'Synopsys VCS',    '-DSYNOPSYS_VCS',    ''),
+    Simulator.new(:vsim,  'Mentor Modelsim', '-DMENTOR_MODELSIM', ''),
+  ]
+
+  # Returns the Simulator object corresponding to the given ID.
+  def SIMULATORS.find_by_id aSimId
+    @id2sim ||= inject({}) {|h,s| h[s.id] = s; h}
+    @id2sim[aSimId]
+  end
 
   # Speaks the given message using printf().
   def RubyVPI.say fmt, *args #:nodoc:
-    VPI.vpi_printf("#{PROJECT_NAME}: #{fmt}\n", *args)
+    VPI.vpi_printf("#{Project[:name]}: #{fmt}\n", *args)
+  end
+
+  # Loads a test to exercise a design (the given VPI handle).
+  #
+  # 1. Creates a sandbox (an anonymous module).
+  #
+  # 2. Defines a constant named "DUT" (which points
+  #    to the given VPI handle) inside the sandbox.
+  #
+  # 3. Loads the given test files into the sandbox.
+  #
+  # 4. Returns the sandbox.
+  #
+  # aDesignHandleOrPath:: either a VPI handle or a path to an
+  #                       object in the Verilog simulation
+  #
+  def RubyVPI.load_test aDesignHandleOrPath, *aTestFilePaths
+    design =
+      if aDesignHandleOrPath.is_a? VPI::Handle
+        aDesignHandleOrPath
+      else
+        VPI.vpi_handle_by_name(aDesignHandleOrPath.to_s, nil)
+      end
+
+    raise ArgumentError, "cannot access the design under test: #{aDesignHandleOrPath.inspect}" unless design
+
+    sandbox = Module.new
+    sandbox.const_set :DUT, design
+
+    aTestFilePaths.flatten.compact.uniq.each do |path|
+      sandbox.module_eval(File.read(path), path)
+    end
+
+    sandbox
   end
 end