ruby-vpi 19.0.0 → 20.0.0

data/examples/counter/RSpec/counter_design.rb

@@ -1,15 +1,15 @@
-
 # Simulates the design under test for one clock cycle.
-def cycle!
-  clock.high!
+def DUT.cycle!
+  clock.t!
   advance_time
-  clock.low!
+
+  clock.f!
   advance_time
 end
 
 # Brings the design under test into a blank state.
-def reset!
-  reset.high!
+def DUT.reset!
+  reset.t!
   cycle!
-  reset.low!
+  reset.f!
 end

data/examples/counter/RSpec/counter_loader.rb

@@ -0,0 +1 @@
+RubyVPI.load_test("counter", "counter_design.rb", "counter_proto.rb", "counter_spec.rb")

data/examples/counter/RSpec/counter_proto.rb

@@ -1,9 +1,11 @@
-always do
-  wait until clock.posedge?
+if RubyVPI::USE_PROTOTYPE
+  always do
+    wait until DUT.clock.posedge?
 
-  if reset.high?
-    count.intVal = 0
-  else
-    count.intVal += 1
+    if DUT.reset.t?
+      DUT.count.intVal = 0
+    else
+      DUT.count.intVal += 1
+    end
   end
 end

data/examples/counter/RSpec/counter_runner.rake

@@ -1,3 +1,8 @@
+# Path to a Ruby script that will be invoked before the Verilog
+# simulation begins.  This script shall then load the appropriate
+# tests to exercise the desired designs in the Verilog simulation.
+TEST_LOADER = "counter_loader.rb"
+
 # Array of paths and shell globs (see the Dir.glob method's documentation for
 # details) to source files and directories that contain source files.  These
 # source files will be loaded by the simulator before the simulation begins.
@@ -20,14 +25,14 @@ SIMULATOR_ARGUMENTS = {
   # Icarus Verilog
   :ivl => "",
 
+  # Cadence NC-Sim
+  :ncsim => "",
+
   # Synopsys VCS
   :vcs => "",
 
   # Mentor Modelsim
-  :vsim => "",
-
-  # Cadence NC-Sim
-  :ncsim => "",
+  :vsim => "counter",
 
 }
 

data/examples/counter/RSpec/counter_spec.rb

@@ -1,39 +1,39 @@
 require 'spec'
 
 # lowest upper bound of counter's value
-LIMIT = 2 ** Counter::Size
+LIMIT = 2 ** DUT.Size.intVal
 
 # maximum allowed value for a counter
 MAX = LIMIT - 1
 
-describe "A resetted counter's value" do
+describe "A #{DUT.name} after being reset" do
   setup do
-    Counter.reset!
+    DUT.reset! # reset the counter
   end
 
   it "should be zero" do
-    Counter.count.intVal.should == 0
+    DUT.count.intVal.should == 0
   end
 
-  it "should increment upon each rising clock edge" do
+  it "should increment upon each subsequent posedge" do
     LIMIT.times do |i|
-      Counter.count.intVal.should == i
-      Counter.cycle! # increment the counter
+      DUT.count.intVal.should == i
+      DUT.cycle! # increment the counter
     end
   end
 end
 
-describe "A counter with the maximum value" do
+describe "A #{DUT.name} with the maximum value" do
   setup do
-    Counter.reset!
+    DUT.reset! # reset the counter
 
     # increment the counter to maximum value
-    MAX.times { Counter.cycle! }
-    Counter.count.intVal.should == MAX
+    MAX.times { DUT.cycle! }
+    DUT.count.intVal.should == MAX
   end
 
   it "should overflow upon increment" do
-    Counter.cycle! # increment the counter
-    Counter.count.intVal.should == 0
+    DUT.cycle! # increment the counter
+    DUT.count.intVal.should == 0
   end
 end

data/examples/counter/xUnit/counter_design.rb

@@ -1,15 +1,16 @@
 
 # Simulates the design under test for one clock cycle.
-def cycle!
-  clock.high!
+def DUT.cycle!
+  clock.t!
   advance_time
-  clock.low!
+
+  clock.f!
   advance_time
 end
 
 # Brings the design under test into a blank state.
-def reset!
-  reset.high!
+def DUT.reset!
+  reset.t!
   cycle!
-  reset.low!
+  reset.f!
 end

data/examples/counter/xUnit/counter_loader.rb

@@ -0,0 +1 @@
+RubyVPI.load_test("counter", "counter_design.rb", "counter_proto.rb", "counter_spec.rb")

data/examples/counter/xUnit/counter_proto.rb

@@ -1,9 +1,11 @@
-always do
-  wait until clock.posedge?
+if RubyVPI::USE_PROTOTYPE
+  always do
+    wait until DUT.clock.posedge?
 
-  if reset.high?
-    count.intVal = 0
-  else
-    count.intVal += 1
+    if DUT.reset.t?
+      DUT.count.intVal = 0
+    else
+      DUT.count.intVal += 1
+    end
   end
 end

data/examples/counter/xUnit/counter_runner.rake

@@ -1,3 +1,8 @@
+# Path to a Ruby script that will be invoked before the Verilog
+# simulation begins.  This script shall then load the appropriate
+# tests to exercise the desired designs in the Verilog simulation.
+TEST_LOADER = "counter_loader.rb"
+
 # Array of paths and shell globs (see the Dir.glob method's documentation for
 # details) to source files and directories that contain source files.  These
 # source files will be loaded by the simulator before the simulation begins.
@@ -20,14 +25,14 @@ SIMULATOR_ARGUMENTS = {
   # Icarus Verilog
   :ivl => "",
 
+  # Cadence NC-Sim
+  :ncsim => "",
+
   # Synopsys VCS
   :vcs => "",
 
   # Mentor Modelsim
-  :vsim => "",
-
-  # Cadence NC-Sim
-  :ncsim => "",
+  :vsim => "counter",
 
 }
 

data/examples/counter/xUnit/counter_spec.rb

@@ -1,39 +1,39 @@
 require 'test/unit'
 
 # lowest upper bound of counter's value
-LIMIT = 2 ** Counter::Size
+LIMIT = 2 ** DUT.Size.intVal
 
 # maximum allowed value for a counter
 MAX = LIMIT - 1
 
-class ResettedCounterValue < Test::Unit::TestCase
+class A_counter_after_being_reset < Test::Unit::TestCase
   def setup
-    Counter.reset!
+    DUT.reset! # reset the counter
   end
 
-  def test_zero
-    assert_equal( 0, Counter.count.intVal )
+  def test_should_be_zero
+    assert_equal( 0, DUT.count.intVal )
   end
 
-  def test_increment
+  def test_should_increment_upon_each_subsequent_posedge
     LIMIT.times do |i|
-      assert_equal( i, Counter.count.intVal )
-      Counter.cycle! # increment the counter
+      assert_equal( i, DUT.count.intVal )
+      DUT.cycle! # increment the counter
     end
   end
 end
 
-class MaximumCounterValue < Test::Unit::TestCase
+class A_counter_with_the_maximum_value < Test::Unit::TestCase
   def setup
-    Counter.reset!
+    DUT.reset! # reset the counter
 
     # increment the counter to maximum value
-    MAX.times { Counter.cycle! }
-    assert_equal( MAX, Counter.count.intVal )
+    MAX.times { DUT.cycle! }
+    assert_equal( MAX, DUT.count.intVal )
   end
 
-  def test_overflow
-    Counter.cycle! # increment the counter
-    assert_equal( 0, Counter.count.intVal )
+  def test_should_overflow_upon_increment
+    DUT.cycle! # increment the counter
+    assert_equal( 0, DUT.count.intVal )
   end
 end

data/examples/pipelined_alu/hw5_unit_design.rb

@@ -1,19 +1,20 @@
 # Simulates the design under test for one clock cycle.
-def cycle!
-  clk.high!
+def DUT.cycle!
+  clk.t!
   advance_time
-  clk.low!
+
+  clk.f!
   advance_time
 end
 
 # Brings the design under test into a blank state.
-def reset!
-  reset.high!
+def DUT.reset!
+  reset.t!
   5.times { cycle! }
-  reset.low!
+  reset.f!
 end
 
-OPERATIONS = (OP_NOP .. OP_MULT).to_a
+OPERATIONS = (DUT.OP_NOP.intVal .. DUT.OP_MULT.intVal).to_a
 
 # Represents an ALU operation.
 class Operation
@@ -31,13 +32,13 @@ class Operation
   # Computes the result of this operation.
   def compute
     case @type
-      when OP_ADD
+      when DUT.OP_ADD.intVal
         @arg1 + @arg2
 
-      when OP_SUB
+      when DUT.OP_SUB.intVal
         @arg1 - @arg2
 
-      when OP_MULT
+      when DUT.OP_MULT.intVal
         @arg1 * @arg2
     end
   end

data/examples/pipelined_alu/hw5_unit_loader.rb

@@ -0,0 +1 @@
+RubyVPI.load_test("hw5_unit", "hw5_unit_design.rb", "hw5_unit_proto.rb", "hw5_unit_spec.rb")

data/examples/pipelined_alu/hw5_unit_proto.rb

@@ -1,2 +1,4 @@
-warn "Woe is me! Nobody implemented a Ruby prototype for this design. :-("
-exit
+if RubyVPI::USE_PROTOTYPE
+  warn "Woe is me! Nobody implemented a Ruby prototype for this design. :-("
+  exit
+end

data/examples/pipelined_alu/hw5_unit_runner.rake

@@ -1,3 +1,8 @@
+# Path to a Ruby script that will be invoked before the Verilog
+# simulation begins.  This script shall then load the appropriate
+# tests to exercise the desired designs in the Verilog simulation.
+TEST_LOADER = "hw5_unit_loader.rb"
+
 # Array of paths and shell globs (see the Dir.glob method's documentation for
 # details) to source files and directories that contain source files.  These
 # source files will be loaded by the simulator before the simulation begins.
@@ -19,14 +24,14 @@ SIMULATOR_ARGUMENTS = {
   # Icarus Verilog
   :ivl => "",
 
+  # Cadence NC-Sim
+  :ncsim => "",
+
   # Synopsys VCS
   :vcs => "",
 
   # Mentor Modelsim
-  :vsim => "",
-
-  # Cadence NC-Sim
-  :ncsim => "",
+  :vsim => "hw5_unit",
 
 }
 

data/examples/pipelined_alu/hw5_unit_spec.rb

@@ -1,19 +1,19 @@
 require 'test/unit'
 require 'int_gen'
 
-class Hw5_unit_spec < Test::Unit::TestCase
+class A_hw5_unit_when_reset < Test::Unit::TestCase
   # Number of input sequences to test.
   NUM_TESTS = 4000
 
   # Bitmask capable of capturing ALU result.
-  ALU_RESULT_MASK = (2 ** Hw5_unit::WIDTH) - 1
+  ALU_RESULT_MASK = (2 ** DUT.WIDTH.intVal) - 1
 
   # Upper limit of values allowed for an operation's tag.
-  OPERATION_TAG_LIMIT = 2 ** Hw5_unit::DATABITS
+  OPERATION_TAG_LIMIT = 2 ** DUT.DATABITS.intVal
 
   def setup
-    Hw5_unit.reset!
-    @intGen = IntegerGenerator.new(Hw5_unit::WIDTH)
+    DUT.reset!
+    @intGen = IntegerGenerator.new(DUT.WIDTH.intVal)
   end
 
   def test_pipeline
@@ -23,37 +23,37 @@ class Hw5_unit_spec < Test::Unit::TestCase
     until numVerified == NUM_TESTS
       # issue a new operation
       if numIssued < NUM_TESTS
-        op = Hw5_unit::Operation.new(
-          Hw5_unit::OPERATIONS[rand(Hw5_unit::OPERATIONS.size)],
+        op = Operation.new(
+          OPERATIONS[rand(OPERATIONS.size)],
           numIssued % OPERATION_TAG_LIMIT,
           @intGen.random,
           @intGen.random
         )
 
-        Hw5_unit.a.intVal           = op.arg1
-        Hw5_unit.b.intVal           = op.arg2
-        Hw5_unit.in_op.intVal       = op.type
-        Hw5_unit.in_databits.intVal = op.tag
+        DUT.a.intVal           = op.arg1
+        DUT.b.intVal           = op.arg2
+        DUT.in_op.intVal       = op.type
+        DUT.in_databits.intVal = op.tag
 
         issuedOps << op
         numIssued += 1
       end
 
-      Hw5_unit.cycle!
+      DUT.cycle!
 
       # verify result of finished operation
-      unless Hw5_unit.out_databits.x?
-        finishedOp = Hw5_unit::Operation.new(
-          Hw5_unit.out_op.intVal,
-          Hw5_unit.out_databits.intVal
+      unless DUT.out_databits.x?
+        finishedOp = Operation.new(
+          DUT.out_op.intVal,
+          DUT.out_databits.intVal
         )
-        finishedOp.result = Hw5_unit.res.intVal & ALU_RESULT_MASK
+        finishedOp.result = DUT.res.intVal & ALU_RESULT_MASK
 
         expectedOp = issuedOps.shift
         assert_equal expectedOp.type, finishedOp.type, "incorrect operation"
         assert_equal expectedOp.tag, finishedOp.tag, "incorrect tag"
 
-        unless finishedOp.type == Hw5_unit::OP_NOP
+        unless finishedOp.type == DUT.OP_NOP.intVal
           assert_equal expectedOp.compute & ALU_RESULT_MASK, finishedOp.result, "incorrect result"
         end
 

data/examples/register_file/register_file_design.rb

@@ -1,10 +1,10 @@
 # Simulates the design under test for one clock cycle.
-def cycle!
+def DUT.cycle!
   advance_time
 end
 
 # Brings the design under test into a blank state.
-def reset!
+def DUT.reset!
   register.each_memoryWord do |word|
     word.x!
   end

data/examples/register_file/register_file_loader.rb

@@ -0,0 +1 @@
+RubyVPI.load_test("register_file", "register_file_design.rb", "register_file_proto.rb", "register_file_spec.rb")

data/examples/register_file/register_file_proto.rb

@@ -1,11 +1,18 @@
-always do
-  wait until rdReg.change? or wtReg.change? or rw.change? or enable.change?
+if RubyVPI::USE_PROTOTYPE
+  always do
+    wait until
+      DUT.rdReg.change? or
+      DUT.wtReg.change? or
+      DUT.rw.change? or
+      DUT.enable.change?
 
-  if rw.low?
-    targetReg        = register.memoryWord_a[rdReg.intVal]
-    outBus.intVal    = targetReg.intVal
-  elsif enable.high?
-    targetReg        = register.memoryWord_a[wtReg.intVal]
-    targetReg.intVal = inBus.intVal
+    if DUT.rw.f?
+      target            = DUT.register.memoryWord_a[DUT.rdReg.intVal]
+      DUT.outBus.intVal = target.intVal
+
+    elsif DUT.enable.t?
+      target            = DUT.register.memoryWord_a[DUT.wtReg.intVal]
+      target.intVal     = DUT.inBus.intVal
+    end
   end
 end

data/examples/register_file/register_file_runner.rake

@@ -1,3 +1,8 @@
+# Path to a Ruby script that will be invoked before the Verilog
+# simulation begins.  This script shall then load the appropriate
+# tests to exercise the desired designs in the Verilog simulation.
+TEST_LOADER = "register_file_loader.rb"
+
 # Array of paths and shell globs (see the Dir.glob method's documentation for
 # details) to source files and directories that contain source files.  These
 # source files will be loaded by the simulator before the simulation begins.
@@ -19,14 +24,14 @@ SIMULATOR_ARGUMENTS = {
   # Icarus Verilog
   :ivl => "",
 
+  # Cadence NC-Sim
+  :ncsim => "",
+
   # Synopsys VCS
   :vcs => "",
 
   # Mentor Modelsim
-  :vsim => "",
-
-  # Cadence NC-Sim
-  :ncsim => "",
+  :vsim => "register_file",
 
 }
 

data/examples/register_file/register_file_spec.rb

@@ -1,39 +1,39 @@
 require 'spec'
 
 module RegisterInterface
-  NUM_REGS = Register_file.register.size
+  NUM_REGS = DUT.register.size
 
   def set_registers(vals)
     raise ArgumentError if vals.length > NUM_REGS
 
-    Register_file.rw.intVal = 1
+    DUT.rw.intVal = 1
 
     vals.each_with_index do |val, i|
-      Register_file.wtReg.intVal = i
-      Register_file.inBus.intVal = val
-      Register_file.cycle!
+      DUT.wtReg.intVal = i
+      DUT.inBus.intVal = val
+      DUT.cycle!
     end
   end
 
   def expect_registers(vals)
     raise ArgumentError if vals.length > NUM_REGS
 
-    Register_file.rw.intVal = 0
+    DUT.rw.intVal = 0
 
     vals.each_with_index do |val, i|
-      Register_file.rdReg.intVal = i
-      Register_file.cycle!
-      Register_file.outBus.intVal.should == val
+      DUT.rdReg.intVal = i
+      DUT.cycle!
+      DUT.outBus.intVal.should == val
     end
   end
 end
 
-describe "An enabled register file" do
+describe "A #{DUT.name}, when enabled" do
   include RegisterInterface
 
   before do
-    Register_file.reset!
-    Register_file.enable.intVal = 1
+    DUT.reset!
+    DUT.enable.intVal = 1
   end
 
   it "should be able to write and then read registers" do
@@ -44,12 +44,12 @@ describe "An enabled register file" do
   end
 end
 
-describe "A disabled register file" do
+describe "A #{DUT.name}, when disabled" do
   include RegisterInterface
 
   before do
-    Register_file.reset!
-    Register_file.enable.intVal = 0
+    DUT.reset!
+    DUT.enable.intVal = 0
   end
 
   it "should not write new values" do

data/ext/main.c

@@ -30,15 +30,15 @@ void main_init() {
 
 
   char* bootLoader = getenv("RUBYVPI_BOOT_LOADER");
-  char* bootTarget = getenv("RUBYVPI_BOOT_TARGET");
+  char* testLoader = getenv("RUBYVPI_TEST_LOADER");
 
-  if (bootLoader != NULL && bootTarget != NULL) {
-    ruby_script(bootTarget);
+  if (bootLoader != NULL && testLoader != NULL) {
+    ruby_script(testLoader);
     rb_load_file(bootLoader);
     ruby_run();
   }
   else {
-    common_printf("error: the RUBYVPI_BOOT_LOADER and RUBYVPI_BOOT_TARGET environment variables are not initialized.");
+    common_printf("error: the RUBYVPI_BOOT_LOADER and RUBYVPI_TEST_LOADER environment variables must be defined.");
     exit(EXIT_FAILURE);
   }
 }

data/lib/ruby-vpi/core/edge-methods.rb

@@ -0,0 +1,32 @@
+# Defines methods for detecting all possible value changes.
+#--
+# Copyright 2007 Suraj N. Kurapati
+# See the file named LICENSE for details.
+
+module RubyVPI
+  class EdgeClass #:nodoc:
+    DETECTION_METHODS = []
+    Meth = Struct.new :name, :info, :body
+
+    vals  = %w[1 0 X Z H L t f]
+    edges = vals.map {|a| vals.map {|b| a + b}}.flatten
+
+    edges.each do |edge|
+      name = "change_#{edge.downcase}?"
+      old, new = edge.tr('tf', '10').split(//).map {|s| 'Vpi' + s}
+
+      info = "Tests if the logic value of this handle has changed from #{old} (in the previous time step) to #{new} (in the current time step)."
+
+      body = %{
+        def #{name}
+          old = @__edge__prev_val
+          new = get_value(VpiScalarVal)
+
+          old == #{old} && new == #{new}
+        end
+      }
+
+      DETECTION_METHODS << Meth.new(name, info, body)
+    end
+  end
+end