ruby-vpi 15.0.2 → 16.0.0

data/ref/ruby/fr_method_index.html

@@ -20,59 +20,59 @@
 <div id="index">
   <h1 class="section-bar">Methods</h1>
   <div id="index-entries">
-    <a href="classes/Vpi/Handle.html#M000046">[] (Vpi::Handle)</a><br />
-    <a href="classes/Vpi.html#M000032">advance_time (Vpi)</a><br />
-    <a href="classes/FileUtils.html#M000028">collect_args (FileUtils)</a><br />
-    <a href="classes/Integer.html#M000017">ensure_max (Integer)</a><br />
-    <a href="classes/Integer.html#M000016">ensure_min (Integer)</a><br />
-    <a href="classes/Integer.html#M000020">extend_sign (Integer)</a><br />
-    <a href="classes/Vpi/Handle.html#M000044">get_value (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000043">get_value_wrapper (Vpi::Handle)</a><br />
-    <a href="classes/RubyVpi.html#M000029">init_bench (RubyVpi)</a><br />
+    <a href="classes/Vpi/Handle.html#M000045">[] (Vpi::Handle)</a><br />
+    <a href="classes/Vpi.html#M000030">advance_time (Vpi)</a><br />
+    <a href="classes/Vpi/Handle.html#M000048">cbValueChange (Vpi::Handle)</a><br />
+    <a href="classes/FileUtils.html#M000026">collect_args (FileUtils)</a><br />
+    <a href="classes/Integer.html#M000018">extend_sign (Integer)</a><br />
+    <a href="classes/Vpi/Handle.html#M000043">get_value (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000042">get_value_wrapper (Vpi::Handle)</a><br />
+    <a href="classes/RubyVpi.html#M000027">init_bench (RubyVpi)</a><br />
     <a href="classes/VerilogParser/Module/Port.html#M000004">input? (VerilogParser::Module::Port)</a><br />
-    <a href="classes/Vpi/Handle.html#M000047">inspect (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000046">inspect (Vpi::Handle)</a><br />
     <a href="classes/Vpi/S_vpi_time.html#M000050">integer (Vpi::S_vpi_time)</a><br />
     <a href="classes/Vpi/S_vpi_time.html#M000051">integer= (Vpi::S_vpi_time)</a><br />
     <a href="classes/Integer.html#M000009">length (Integer)</a><br />
     <a href="classes/Integer.html#M000010">limit (Integer)</a><br />
     <a href="classes/Integer.html#M000008">log2 (Integer)</a><br />
-    <a href="classes/Float.html#M000022">mantissa (Float)</a><br />
+    <a href="classes/Float.html#M000020">mantissa (Float)</a><br />
     <a href="classes/Integer.html#M000012">mask (Integer)</a><br />
     <a href="classes/Integer.html#M000014">max (Integer)</a><br />
     <a href="classes/Vpi/Handle.html#M000049">method_missing (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000042">negedge? (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000041">negedge? (Vpi::Handle)</a><br />
     <a href="classes/VerilogParser.html#M000001">new (VerilogParser)</a><br />
+    <a href="classes/VerilogParser/Module/Parameter.html#M000007">new (VerilogParser::Module::Parameter)</a><br />
+    <a href="classes/Vpi.html#M000032">new (Vpi)</a><br />
+    <a href="classes/ERB.html#M000024">new (ERB)</a><br />
     <a href="classes/VerilogParser/Module/Port.html#M000003">new (VerilogParser::Module::Port)</a><br />
     <a href="classes/VerilogParser/Module.html#M000002">new (VerilogParser::Module)</a><br />
-    <a href="classes/VerilogParser/Module/Parameter.html#M000007">new (VerilogParser::Module::Parameter)</a><br />
-    <a href="classes/ERB.html#M000026">new (ERB)</a><br />
     <a href="classes/VerilogParser/Module/Port.html#M000005">output? (VerilogParser::Module::Port)</a><br />
-    <a href="classes/Integer.html#M000018">pack (Integer)</a><br />
-    <a href="classes/Vpi/Handle.html#M000041">posedge? (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000045">put_value (Vpi::Handle)</a><br />
+    <a href="classes/Integer.html#M000016">pack (Integer)</a><br />
+    <a href="classes/Vpi/Handle.html#M000040">posedge? (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000044">put_value (Vpi::Handle)</a><br />
     <a href="classes/VerilogParser/Module/Port.html#M000006">reg? (VerilogParser::Module::Port)</a><br />
-    <a href="classes/FileUtils.html#M000027">sh (FileUtils)</a><br />
-    <a href="classes/Vpi.html#M000031">simulate (Vpi)</a><br />
-    <a href="classes/Vpi.html#M000033">simulation_time (Vpi)</a><br />
-    <a href="classes/Integer.html#M000021">split (Integer)</a><br />
-    <a href="classes/Vpi/S_vpi_value.html#M000035">to_f (Vpi::S_vpi_value)</a><br />
-    <a href="classes/String.html#M000023">to_f (String)</a><br />
+    <a href="classes/FileUtils.html#M000025">sh (FileUtils)</a><br />
+    <a href="classes/Vpi.html#M000029">simulate (Vpi)</a><br />
+    <a href="classes/Vpi.html#M000031">simulation_time (Vpi)</a><br />
+    <a href="classes/Integer.html#M000019">split (Integer)</a><br />
+    <a href="classes/Vpi/S_vpi_value.html#M000034">to_f (Vpi::S_vpi_value)</a><br />
+    <a href="classes/String.html#M000021">to_f (String)</a><br />
     <a href="classes/Vpi/S_vpi_time.html#M000052">to_i (Vpi::S_vpi_time)</a><br />
-    <a href="classes/Vpi/S_vpi_value.html#M000034">to_i (Vpi::S_vpi_value)</a><br />
+    <a href="classes/Vpi/S_vpi_value.html#M000033">to_i (Vpi::S_vpi_value)</a><br />
     <a href="classes/Integer.html#M000011">to_limit (Integer)</a><br />
     <a href="classes/Integer.html#M000013">to_mask (Integer)</a><br />
     <a href="classes/Integer.html#M000015">to_max (Integer)</a><br />
-    <a href="classes/String.html#M000025">to_ruby_const_name (String)</a><br />
-    <a href="classes/Vpi/Handle.html#M000048">to_s (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/S_vpi_value.html#M000036">to_s (Vpi::S_vpi_value)</a><br />
-    <a href="classes/Integer.html#M000019">unpack (Integer)</a><br />
+    <a href="classes/String.html#M000023">to_ruby_const_name (String)</a><br />
+    <a href="classes/Vpi/Handle.html#M000047">to_s (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/S_vpi_value.html#M000035">to_s (Vpi::S_vpi_value)</a><br />
+    <a href="classes/Integer.html#M000017">unpack (Integer)</a><br />
     <a href="classes/RDoc.html#M000053">usage_from_file (RDoc)</a><br />
-    <a href="classes/String.html#M000024">verilog_to_ruby (String)</a><br />
-    <a href="classes/Vpi.html#M000030">vpi_register_cb (Vpi)</a><br />
-    <a href="classes/Vpi/Handle.html#M000038">x! (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000037">x? (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000040">z! (Vpi::Handle)</a><br />
-    <a href="classes/Vpi/Handle.html#M000039">z? (Vpi::Handle)</a><br />
+    <a href="classes/String.html#M000022">verilog_to_ruby (String)</a><br />
+    <a href="classes/Vpi.html#M000028">vpi_register_cb (Vpi)</a><br />
+    <a href="classes/Vpi/Handle.html#M000037">x! (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000036">x? (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000039">z! (Vpi::Handle)</a><br />
+    <a href="classes/Vpi/Handle.html#M000038">z? (Vpi::Handle)</a><br />
   </div>
 </div>
 </body>

data/samp/counter/counter_rspec_runner.rake

@@ -33,6 +33,10 @@ SIMULATOR_ARGUMENTS = {
 
   # Mentor Modelsim
   :vsim => '',
+
+  # Cadence NC-Sim
+  :ncsim => '',
+
 }
 
 # This task is invoked _before_ the simulator runs.

data/samp/counter/counter_xunit_runner.rake

@@ -33,6 +33,10 @@ SIMULATOR_ARGUMENTS = {
 
   # Mentor Modelsim
   :vsim => '',
+
+  # Cadence NC-Sim
+  :ncsim => '',
+
 }
 
 # This task is invoked _before_ the simulator runs.

data/samp/pipelined_alu/Hw5UnitModel.rb

@@ -1,22 +1,6 @@
-=begin
-  Copyright 2006 Suraj N. Kurapati
-
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-=end
+#--
+# Copyright 2006 Suraj N. Kurapati
+# See the file named LICENSE for details.
 
 # Behavioral model of the hw5_unit Verilog module.
 class Hw5UnitModel

data/samp/pipelined_alu/README

@@ -1,6 +1,9 @@
 PIPELINED ALU
 
-  This example is my solution to a homework assignment for an Advanced Logic Design class I had taken during the Winter of 2006 at University of California, Santa Cruz. Relevant portions of the problem have been revised and reproduced here with permission from the instructor: professor Jose Renau.
+  This example is my solution to a homework assignment for an Advanced Logic
+  Design class I had taken during the Winter of 2006 at University of
+  California, Santa Cruz. Relevant portions of the problem have been revised and
+  reproduced here with permission from the instructor: professor Jose Renau.
 
 
 
@@ -44,13 +47,20 @@ PROBLEM
 
   5. OP_MULT must have 3 cycles latency.
 
-  6. There is only one result (res). Since three operations can finish every cycle, you need to buffer the other two. Note that since at most one operation starts per cycle, a 3-entry buffer should be enough.
+  6. There is only one result (res). Since three operations can finish every
+  cycle, you need to buffer the other two. Note that since at most one operation
+  starts per cycle, a 3-entry buffer should be enough.
 
-  7. Each operation has an associated tag (in_databits) which you must pass back with the result (out_databits). For example, if a OP_MULT operation is started with parameters a=2, b=4, in_databits=3; then after the multiplication finishes three cycles later, the outputs should be res=8, out_databits=3, out_op=OP_MULT.
+  7. Each operation has an associated tag (in_databits) which you must pass back
+  with the result (out_databits). For example, if a OP_MULT operation is started
+  with parameters a=2, b=4, in_databits=3; then after the multiplication
+  finishes three cycles later, the outputs should be res=8, out_databits=3,
+  out_op=OP_MULT.
 
   8. The testbench used to verify this module must:
 
-    a. Test random combinations of positive, zero, one, prime numbers, power-of-two values from powers 1 to 32, and random numbers.
+    a. Test random combinations of positive, zero, one, prime numbers,
+    power-of-two values from powers 1 to 32, and random numbers.
 
     b. Execute random combinations of add, subtract, and multiply operations.
 
@@ -60,7 +70,10 @@ PROBLEM
 
 DESIGN
 
-  From the start, my approach was to use a single queue to solve the resource conflict (only one ALU can give an output per cycle). After drawing some sketches and understanding the problem, I wrote the following algorithm to solve the resource conflict:
+  From the start, my approach was to use a single queue to solve the resource
+  conflict (only one ALU can give an output per cycle). After drawing some
+  sketches and understanding the problem, I wrote the following algorithm to
+  solve the resource conflict:
 
     def queue_results(a, b, c)
       output a
@@ -68,7 +81,10 @@ DESIGN
     end
 
 
-  We cannot perform all the operations in the queue_results method using only one cycle. However, if the queue_results method is not implemented as shown, then the design will not work---it will be chaotic and produce incoherent results.
+  We cannot perform all the operations in the queue_results method using only
+  one cycle. However, if the queue_results method is not implemented as shown,
+  then the design will not work---it will be chaotic and produce incoherent
+  results.
 
   The trick is to satisfy the post-conditions of the queue_results method (one result is outputted and the other two have been queued) using multiple clock cycles:
 
@@ -88,15 +104,23 @@ DESIGN
     2. enqueue c; output a
     (nothing to remember)
 
-  Note that we cannot output the 'a' result during the first cycle because that would violate the post-conditions.
+  Note that we cannot output the 'a' result during the first cycle because that
+  would violate the post-conditions.
 
 
-  After gaining this understanding, I realized that a separate queue was wholly unnecessary. Instead, I could simply use pipeline registers to remember values until they were needed (i.e. the 'a' result is output only in the last cycle).
+  After gaining this understanding, I realized that a separate queue was wholly
+  unnecessary. Instead, I could simply use pipeline registers to remember values
+  until they were needed (i.e. the 'a' result is output only in the last cycle).
 
-  This approach uses exactly the same number of pipeline registers (three in this case) as the size of the queue suggested by the Professor. Also, this approach uses less storage than the three-queues (one for each ALU output; therefore 9 registers) approach suggested by the Professor.
+  This approach uses exactly the same number of pipeline registers (three in
+  this case) as the size of the queue suggested by the Professor. Also, this
+  approach uses less storage than the three-queues (one for each ALU output;
+  therefore 9 registers) approach suggested by the Professor.
 
 
-  Finally, I wrote a behavioral model (see MODEL section) of the RTL using Ruby and verified both my initial approach (magical single-cycle queueing of multiple items) and its later improvement (the pipeline-register approach).
+  Finally, I wrote a behavioral model (see MODEL section) of the RTL using Ruby
+  and verified both my initial approach (magical single-cycle queueing of
+  multiple items) and its later improvement (the pipeline-register approach).
 
 
 
@@ -106,7 +130,8 @@ MODEL
   $ ruby -w TestHw5UnitModel.rb		# use the "-d" option for details
 
 
-  The model is written in Ruby and comes with a unit test which is similar to the Ruby-VPI test bench I wrote for the RTL implementation.
+  The model is written in Ruby and comes with a unit test which is similar to
+  the Ruby-VPI test bench I wrote for the RTL implementation.
 
 
 
@@ -123,5 +148,5 @@ TEST BENCH
 
 
 
-  The test bench structure was ported from my unit test for the behavioral model of hw5_unit.
-
+  The test bench structure was ported from my unit test for the behavioral model
+  of hw5_unit.

data/samp/pipelined_alu/TestHw5UnitModel.rb

@@ -1,22 +1,6 @@
-=begin
-  Copyright 2006 Suraj N. Kurapati
-
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-=end
+#--
+# Copyright 2006 Suraj N. Kurapati
+# See the file named LICENSE for details.
 
 require 'InputGenerator'
 require 'Hw5UnitModel'
@@ -41,7 +25,12 @@ class TestHw5UnitModel < Test::Unit::TestCase
     inputQueue = []
 
     NUM_VECTORS.times do |i|
-      inputQueue << Hw5UnitModel::Operation.new(Hw5UnitModel::OPERATIONS[rand(Hw5UnitModel::OPERATIONS.size)], i, @ingen.gen.abs, @ingen.gen.abs)
+      inputQueue << Hw5UnitModel::Operation.new(
+        Hw5UnitModel::OPERATIONS[rand(Hw5UnitModel::OPERATIONS.size)],
+        i,
+        @ingen.gen.abs,
+        @ingen.gen.abs
+      )
     end
 
 

data/samp/pipelined_alu/hw5_unit.v

@@ -1,21 +1,6 @@
 /*
   Copyright 2006 Suraj N. Kurapati
-
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+  See the file named LICENSE for details.
 */
 
 `define WIDTH 32

data/samp/pipelined_alu/hw5_unit_test_runner.rake

@@ -33,6 +33,10 @@ SIMULATOR_ARGUMENTS = {
 
   # Mentor Modelsim
   :vsim => '',
+
+  # Cadence NC-Sim
+  :ncsim => '',
+
 }
 
 # This task is invoked _before_ the simulator runs.

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -1,24 +1,7 @@
-=begin
-  Copyright 2006 Suraj N. Kurapati
-
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-=end
-
 # This file is a behavioral specification for the design under test.
+#--
+# Copyright 2006 Suraj N. Kurapati
+# See the file named LICENSE for details.
 
 require 'int_gen'
 

data/samp/pipelined_alu/int_gen.rb

@@ -1,22 +1,7 @@
-=begin
-  Copyright 2006 Suraj N. Kurapati
-
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-=end
+# Library for generating integers.
+#--
+# Copyright 2006 Suraj N. Kurapati
+# See the file named LICENSE for details.
 
 # Generates random integers of configurable length.
 class IntegerGenerator
@@ -27,7 +12,8 @@ class IntegerGenerator
 
   attr_reader :bits
 
-  # Generates random integers that are representable by the given number of bits.
+  # Generates random integers that are representable by the given number of
+  # bits.
   def initialize aBits
     @bits = aBits
     @limit = 2 ** @bits

metadata

@@ -1,17 +1,17 @@
 --- !ruby/object:Gem::Specification 
-rubygems_version: 0.9.0
+rubygems_version: 0.9.2
 specification_version: 1
 name: ruby-vpi
 version: !ruby/object:Gem::Version 
-  version: 15.0.2
-date: 2007-01-22 00:00:00 -08:00
+  version: 16.0.0
+date: 2007-05-02 00:00:00 -07:00
 summary: Ruby interface to IEEE 1364-2005 Verilog VPI
 require_paths: 
 - lib
 email: 
 homepage: http://ruby-vpi.rubyforge.org
 rubyforge_project: ruby-vpi
-description: Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI. It lets you create complex Verilog test benches easily and wholly in Ruby.
+description: Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby.
 autorequire: ruby-vpi
 default_executable: 
 bindir: bin
@@ -76,53 +76,57 @@ files:
 - lib/ruby-vpi/float.rb
 - lib/ruby-vpi/vpi.rb
 - lib/ruby-vpi/verilog_parser.rb
-- doc/history.yml
+- doc/history.rb
 - doc/Rakefile
 - doc/figures
 - doc/images
 - doc/rss.erb
-- doc/LICENSE
+- doc/rss.xml
 - doc/memo.doc
 - doc/manual.doc
 - doc/history.doc
 - doc/common.css
 - doc/readme.doc
 - doc/common.tpl
-- doc/history.rb
+- doc/memo.html
 - doc/intro.inc
 - doc/lib
-- doc/memo.html
 - doc/manual.html
 - doc/history.html
 - doc/readme.html
-- doc/rss.xml
+- doc/history.yaml
+- doc/README
 - doc/print.css
 - doc/figures/figures.dia
 - doc/figures/ruby_relay.png
 - doc/figures/organization.png
 - doc/figures/organization_detailed.png
-- doc/images/LICENSE
-- doc/images/feed-icon.LICENSE
-- doc/images/feed-icon.png
-- doc/images/caution.png
-- doc/images/caution.svg
-- doc/images/feed-icon.svg
-- doc/images/home.png
-- doc/images/home.svg
-- doc/images/important.png
-- doc/images/important.svg
-- doc/images/next.png
-- doc/images/next.svg
-- doc/images/note.png
-- doc/images/note.svg
-- doc/images/prev.png
-- doc/images/prev.svg
-- doc/images/tip.png
-- doc/images/tip.svg
-- doc/images/up.png
-- doc/images/up.svg
-- doc/images/warning.png
-- doc/images/warning.svg
+- doc/images/feed-icon-28x28.png
+- doc/images/ruby
+- doc/images/tango
+- doc/images/ruby/logo.png
+- doc/images/ruby/LICENSE
+- doc/images/ruby/logo-reflection.png
+- doc/images/ruby/logo-reflection.xcf
+- doc/images/tango/caution.png
+- doc/images/tango/home.png
+- doc/images/tango/important.png
+- doc/images/tango/next.png
+- doc/images/tango/note.png
+- doc/images/tango/prev.png
+- doc/images/tango/tip.png
+- doc/images/tango/up.png
+- doc/images/tango/warning.png
+- doc/images/tango/caution.svg
+- doc/images/tango/home.svg
+- doc/images/tango/important.svg
+- doc/images/tango/next.svg
+- doc/images/tango/note.svg
+- doc/images/tango/prev.svg
+- doc/images/tango/tip.svg
+- doc/images/tango/up.svg
+- doc/images/tango/warning.svg
+- doc/images/tango/LICENSE
 - doc/lib/doc_format.rb
 - doc/lib/doc_proxy.rb
 - doc/lib/erb_content.rb
@@ -276,29 +280,29 @@ files:
 - ref/ruby/classes/Integer.src/M000017.html
 - ref/ruby/classes/Integer.src/M000018.html
 - ref/ruby/classes/Integer.src/M000019.html
-- ref/ruby/classes/Integer.src/M000020.html
-- ref/ruby/classes/Integer.src/M000021.html
-- ref/ruby/classes/Float.src/M000022.html
+- ref/ruby/classes/Float.src/M000020.html
+- ref/ruby/classes/String.src/M000021.html
+- ref/ruby/classes/String.src/M000022.html
 - ref/ruby/classes/String.src/M000023.html
-- ref/ruby/classes/String.src/M000024.html
-- ref/ruby/classes/String.src/M000025.html
-- ref/ruby/classes/ERB.src/M000026.html
-- ref/ruby/classes/FileUtils.src/M000027.html
-- ref/ruby/classes/FileUtils.src/M000028.html
-- ref/ruby/classes/RubyVpi.src/M000029.html
+- ref/ruby/classes/ERB.src/M000024.html
+- ref/ruby/classes/FileUtils.src/M000025.html
+- ref/ruby/classes/FileUtils.src/M000026.html
+- ref/ruby/classes/RubyVpi.src/M000027.html
+- ref/ruby/classes/Vpi.src/M000028.html
+- ref/ruby/classes/Vpi.src/M000029.html
 - ref/ruby/classes/Vpi.src/M000030.html
 - ref/ruby/classes/Vpi.src/M000031.html
 - ref/ruby/classes/Vpi.src/M000032.html
-- ref/ruby/classes/Vpi.src/M000033.html
 - ref/ruby/classes/Vpi/S_vpi_value.src
 - ref/ruby/classes/Vpi/Handle.src
 - ref/ruby/classes/Vpi/S_vpi_time.src
 - ref/ruby/classes/Vpi/S_vpi_value.html
 - ref/ruby/classes/Vpi/Handle.html
 - ref/ruby/classes/Vpi/S_vpi_time.html
+- ref/ruby/classes/Vpi/S_vpi_value.src/M000033.html
 - ref/ruby/classes/Vpi/S_vpi_value.src/M000034.html
 - ref/ruby/classes/Vpi/S_vpi_value.src/M000035.html
-- ref/ruby/classes/Vpi/S_vpi_value.src/M000036.html
+- ref/ruby/classes/Vpi/Handle.src/M000036.html
 - ref/ruby/classes/Vpi/Handle.src/M000037.html
 - ref/ruby/classes/Vpi/Handle.src/M000038.html
 - ref/ruby/classes/Vpi/Handle.src/M000039.html
@@ -309,7 +313,7 @@ files:
 - ref/ruby/classes/Vpi/Handle.src/M000044.html
 - ref/ruby/classes/Vpi/Handle.src/M000045.html
 - ref/ruby/classes/Vpi/Handle.src/M000046.html
-- ref/ruby/classes/Vpi/Handle.src/M000047.html
+- ref/ruby/classes/Vpi/Handle.src/M000048.html
 - ref/ruby/classes/Vpi/Handle.src/M000049.html
 - ref/ruby/classes/Vpi/S_vpi_time.src/M000050.html
 - ref/ruby/classes/Vpi/S_vpi_time.src/M000051.html