rggen 0.10.0 → 0.11.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -7,15 +7,15 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.
 
 RgGen has following features:
 
-* Generate source files related to CSR from register map documents
+* Generate source files related to CSR from register map specifications
     * Source files listed below will be generated:
         * SystemVerilog RTL
         * UVM RAL model
-* Register map documents can be written in human readable format
+* Register map specifications can be written in human readable format
     * Supported formats are listed below:
         * Ruby with APIs to describe register map information
         * YAML

data/lib/rggen/built_in.rb

@@ -1,5 +1,6 @@
 # frozen_string_literal: true
 
+require 'rggen/systemverilog'
 require_relative 'built_in/version'
 
 module RgGen
@@ -36,8 +37,8 @@ module RgGen
       'built_in/bit_field/type/rof',
       'built_in/bit_field/type/rs_w0s_w1s',
       'built_in/bit_field/type/rw_wo',
-      'built_in/bit_field/type/rwe_rwl',
-      'built_in/bit_field/type/rwe_rwl'
+      'built_in/bit_field/type/rwc_rwe_rwl',
+      'built_in/bit_field/type/w0trg_w1trg'
     ].freeze
 
     def self.load_built_in

data/lib/rggen/built_in/bit_field/initial_value.rb

@@ -14,6 +14,11 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
         end
     end
 
+    verify(:component) do
+      error_condition { option[:require] && !initial_value? }
+      message { 'no initial value is given' }
+    end
+
     verify(:component) do
       error_condition { initial_value? && initial_value < min_initial_value }
       message do
@@ -32,8 +37,20 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
       end
     end
 
+    verify(:component) do
+      error_condition { initial_value? && !match_valid_condition? }
+      message do
+        "does not match the valid initial value condition: #{initial_value}"
+      end
+    end
+
     private
 
+    def option
+      @option ||=
+        (bit_field.options && bit_field.options[:initial_value]) || {}
+    end
+
     def min_initial_value
       bit_field.width == 1 ? 0 : -(2**(bit_field.width - 1))
     end
@@ -41,5 +58,10 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
     def max_initial_value
       2**bit_field.width - 1
     end
+
+    def match_valid_condition?
+      !option.key?(:valid_condition) ||
+        instance_exec(@initial_value, &option[:valid_condition])
+    end
   end
 end

data/lib/rggen/built_in/bit_field/reference.rb

@@ -3,7 +3,8 @@
 RgGen.define_simple_feature(:bit_field, :reference) do
   register_map do
     property :reference, forward_to: :reference_bit_field, verify: :all
-    property :reference?, body: -> { !@input_reference.nil? }
+    property :reference?, body: -> { use_reference? && !no_reference? }
+    property :reference_width, forward_to: :required_width
     property :find_reference, forward_to: :find_reference_bit_field
 
     input_pattern /(#{variable_name})\.(#{variable_name})/
@@ -17,6 +18,11 @@ RgGen.define_simple_feature(:bit_field, :reference) do
         end
     end
 
+    verify(:component) do
+      error_condition { require_reference? && no_reference? }
+      message { 'no reference bit field is given' }
+    end
+
     verify(:component) do
       error_condition { reference? && @input_reference == bit_field.full_name }
       message { "self reference: #{@input_reference}" }
@@ -70,8 +76,33 @@ RgGen.define_simple_feature(:bit_field, :reference) do
       message { "refer to reserved bit field: #{@input_reference}" }
     end
 
+    verify(:all) do
+      error_condition { reference? && !match_width? }
+      message do
+        "#{required_width} bits reference bit field is required: " \
+        "#{reference_bit_field.width} bit(s) width"
+      end
+    end
+
     private
 
+    def option
+      @option ||=
+        (bit_field.options && bit_field.options[:reference]) || {}
+    end
+
+    def use_reference?
+      option.fetch(:use, false)
+    end
+
+    def require_reference?
+      use_reference? && option[:require]
+    end
+
+    def no_reference?
+      @input_reference.nil?
+    end
+
     def reference_bit_field
       (reference? || nil) &&
         (@reference_bit_field ||= lookup_reference)
@@ -96,5 +127,13 @@ RgGen.define_simple_feature(:bit_field, :reference) do
       !(bit_field.sequential? && reference_bit_field.sequential?) ||
         bit_field.sequence_size == reference_bit_field.sequence_size
     end
+
+    def required_width
+      option[:width] || bit_field.width
+    end
+
+    def match_width?
+      reference_bit_field.width >= required_width
+    end
   end
 end

data/lib/rggen/built_in/bit_field/sv_rtl_top.rb

@@ -47,10 +47,12 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         [*register.array_size, bit_field.sequence_size].compact
     end
 
-    def value(register_offset = nil, bit_field_offset = nil)
+    def value(register_offset = nil, bit_field_offset = nil, width = nil)
+      bit_field_offset ||= local_index
+      width ||= bit_field.width
       register_block
         .register_if[register.index(register_offset)]
-        .value[bit_field.lsb(bit_field_offset || local_index), bit_field.width]
+        .value[bit_field.lsb(bit_field_offset), width]
     end
 
     private

data/lib/rggen/built_in/bit_field/type.rb

@@ -33,28 +33,30 @@ RgGen.define_list_feature(:bit_field, :type) do
         end
 
         def volatile
-          @volatile = true
+          @volatility = -> { true }
         end
 
         def non_volatile
-          @volatile = false
+          @volatility = -> { false }
         end
 
-        def volatile?
-          @volatile.nil? || @volatile
+        def volatile?(&block)
+          @volatility = block
         end
 
-        def need_initial_value(**options)
-          @initial_value_options = options.merge(needed: true)
-        end
+        attr_reader :volatility
 
-        attr_reader :initial_value_options
+        def options
+          @options ||= {}
+        end
 
-        def use_reference(**options)
-          @reference_options = options.merge(usable: true)
+        def initial_value(**option)
+          options[:initial_value] = option
         end
 
-        attr_reader :reference_options
+        def reference(**option)
+          options[:reference] = option
+        end
       end
 
       property :type
@@ -63,78 +65,19 @@ RgGen.define_list_feature(:bit_field, :type) do
       property :read_only?, body: -> { readable? && !writable? }
       property :write_only?, body: -> { writable? && !readable? }
       property :reserved?, body: -> { !(readable? || writable?) }
-      property :volatile?, forward_to_helper: true
+      property :volatile?, forward_to: :volatility
+      property :options, forward_to_helper: true
 
       build { |value| @type = value }
 
-      verify(:component) do
-        error_condition { no_initial_value_given? }
-        message { 'no initial value is given' }
-      end
-
-      verify(:component) do
-        error_condition do
-          bit_field.initial_value? && not_match_initial_value?
-        end
-        message do
-          "value 0x#{required_initial_value.to_s(16)} is only allowed for " \
-          "initial value: 0x#{bit_field.initial_value.to_s(16)}"
-        end
-      end
-
-      verify(:component) do
-        error_condition { no_reference_bit_field_given? }
-        message { 'no reference bit field is given' }
-      end
-
-      verify(:all) do
-        error_condition { invalid_reference_width? }
-        message do
-          "#{reference_width} bit(s) reference bit field is required: " \
-          "#{bit_field.reference.full_name} " \
-          "#{bit_field.reference.width} bit(s)"
-        end
-      end
-
       private
 
-      def no_initial_value_given?
-        helper.initial_value_options&.key?(:needed) &&
-          !bit_field.initial_value?
-      end
-
-      def not_match_initial_value?
-        helper.initial_value_options&.key?(:value) &&
-          bit_field.initial_value != required_initial_value
-      end
-
-      def required_initial_value
-        value = helper.initial_value_options[:value]
-        if value.is_a?(Proc)
-          instance_exec(&value)
-        else
-          value
+      def volatility
+        if @volatility.nil?
+          @volatility =
+            helper.volatility.nil? || instance_exec(&helper.volatility)
         end
-      end
-
-      def no_reference_bit_field_given?
-        use_reference? &&
-          helper.reference_options[:required] &&
-          !bit_field.reference?
-      end
-
-      def invalid_reference_width?
-        use_reference? &&
-          bit_field.reference? &&
-          bit_field.reference.width != reference_width
-      end
-
-      def use_reference?
-        helper.reference_options&.key?(:usable)
-      end
-
-      def reference_width
-        helper.reference_options[:width] || bit_field.width
+        @volatility
       end
     end
 
@@ -174,6 +117,14 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.full_name('_')
       end
 
+      def width
+        bit_field.width
+      end
+
+      def array_size
+        bit_field.array_size
+      end
+
       def initial_value
         hex(bit_field.initial_value, bit_field.width)
       end
@@ -184,9 +135,22 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def reference_bit_field
-        bit_field
-          .find_reference(register_block.bit_fields)
-          &.value(register.local_index, bit_field.local_index)
+        bit_field.reference? &&
+          bit_field
+            .find_reference(register_block.bit_fields)
+            .value(
+              register.local_index,
+              bit_field.local_index,
+              bit_field.reference_width
+            )
+      end
+
+      def bit_field_if
+        bit_field.bit_field_sub_if
+      end
+
+      def loop_variables
+        bit_field.loop_variables
       end
     end
 

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb

@@ -2,14 +2,14 @@
 <% if [:w0c, :w1c].include?(bit_field.type) %>
   .CLEAR_VALUE    (<%= clear_value %>),
 <% end %>
-  .WIDTH          (<%= bit_field.width %>),
+  .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
   .i_clk            (<%= register_block.clock %>),
   .i_rst_n          (<%= register_block.reset%>),
-  .bit_field_if     (<%= bit_field.bit_field_sub_if %>),
-  .i_set            (<%= set[bit_field.loop_variables] %>),
+  .bit_field_if     (<%= bit_field_if %>),
+  .i_set            (<%= set[loop_variables] %>),
   .i_mask           (<%= mask %>),
-  .o_value          (<%= value_out[bit_field.loop_variables] %>),
+  .o_value          (<%= value_out[loop_variables] %>),
   .o_value_unmasked (<%= value_out_unmasked %>)
 );

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb

@@ -3,16 +3,16 @@
 RgGen.define_list_item_feature(:bit_field, :type, :rc) do
   register_map do
     read_only
-    use_reference
-    need_initial_value
+    reference use: true
+    initial_value require: true
   end
 end
 
 RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
   register_map do
     read_write
-    use_reference
-    need_initial_value
+    reference use: true
+    initial_value require: true
   end
 end
 
@@ -20,26 +20,17 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
   sv_rtl do
     build do
       input :register_block, :set, {
-        name: "i_#{full_name}_set",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
+        name: "i_#{full_name}_set", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
       }
       output :register_block, :value_out, {
-        name: "o_#{full_name}",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
         output :register_block, :value_unmasked, {
-          name: "o_#{full_name}_unmasked",
-          data_type: :logic,
-          width: bit_field.width,
-          array_size: bit_field.array_size,
-          array_format: array_port_format
+          name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
+          array_size: array_size, array_format: array_port_format
         }
       end
     end
@@ -62,7 +53,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
 
     def value_out_unmasked
       (bit_field.reference? || nil) &&
-        value_unmasked[bit_field.loop_variables]
+        value_unmasked[loop_variables]
     end
   end
 end

data/lib/rggen/built_in/bit_field/type/reserved.erb

@@ -1,3 +1,3 @@
 rggen_bit_field_reserved u_bit_field (
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>)
+  .bit_field_if (<%= bit_field_if %>)
 );

data/lib/rggen/built_in/bit_field/type/ro.erb

@@ -1,6 +1,6 @@
 rggen_bit_field_ro #(
-  .WIDTH  (<%= bit_field.width %>)
+  .WIDTH  (<%= width %>)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .bit_field_if (<%= bit_field_if %>),
   .i_value      (<%= reference_or_value_in %>)
 );

data/lib/rggen/built_in/bit_field/type/ro.rb

@@ -3,18 +3,15 @@
 RgGen.define_list_item_feature(:bit_field, :type, :ro) do
   register_map do
     read_only
-    use_reference
+    reference use: true
   end
 
   sv_rtl do
     build do
       unless bit_field.reference?
         input :register_block, :value_in, {
-          name: "i_#{full_name}",
-          data_type: :logic,
-          width: bit_field.width,
-          array_size: bit_field.array_size,
-          array_format: array_port_format
+          name: "i_#{full_name}", data_type: :logic, width: width,
+          array_size: array_size, array_format: array_port_format
         }
       end
     end
@@ -27,7 +24,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
       if bit_field.reference?
         reference_bit_field
       else
-        value_in[bit_field.loop_variables]
+        value_in[loop_variables]
       end
     end
   end