rggen 0.10.0 → 0.11.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (44) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +3 -3
  3. data/lib/rggen/built_in.rb +3 -2
  4. data/lib/rggen/built_in/bit_field/initial_value.rb +22 -0
  5. data/lib/rggen/built_in/bit_field/reference.rb +40 -1
  6. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +4 -2
  7. data/lib/rggen/built_in/bit_field/type.rb +44 -80
  8. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +4 -4
  9. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +11 -20
  10. data/lib/rggen/built_in/bit_field/type/reserved.erb +1 -1
  11. data/lib/rggen/built_in/bit_field/type/ro.erb +2 -2
  12. data/lib/rggen/built_in/bit_field/type/ro.rb +4 -7
  13. data/lib/rggen/built_in/bit_field/type/rof.erb +2 -2
  14. data/lib/rggen/built_in/bit_field/type/rof.rb +1 -1
  15. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +4 -4
  16. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +6 -12
  17. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +3 -3
  18. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +4 -7
  19. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +16 -0
  20. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +92 -0
  21. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +9 -0
  22. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +29 -0
  23. data/lib/rggen/built_in/register/type.rb +12 -0
  24. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +3 -3
  25. data/lib/rggen/built_in/register/type/external.rb +9 -22
  26. data/lib/rggen/built_in/register/type/indirect.rb +1 -3
  27. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +3 -3
  28. data/lib/rggen/built_in/register_block/protocol.rb +28 -0
  29. data/lib/rggen/built_in/register_block/protocol/apb.erb +4 -4
  30. data/lib/rggen/built_in/register_block/protocol/apb.rb +14 -38
  31. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +4 -4
  32. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +22 -64
  33. data/lib/rggen/built_in/register_block/sv_ral_package.rb +13 -6
  34. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +8 -9
  35. data/lib/rggen/built_in/version.rb +1 -1
  36. data/lib/rggen/setup/default.rb +3 -2
  37. data/sample/block_0.rb +9 -4
  38. data/sample/block_0.sv +97 -20
  39. data/sample/block_0.xlsx +0 -0
  40. data/sample/block_0.yml +9 -4
  41. data/sample/block_0_ral_pkg.sv +16 -6
  42. metadata +11 -9
  43. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +0 -14
  44. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +0 -39
@@ -1,6 +1,6 @@
1
1
  rggen_bit_field_ro #(
2
- .WIDTH (<%= bit_field.width %>)
2
+ .WIDTH (<%= width %>)
3
3
  ) u_bit_field (
4
- .bit_field_if (<%= bit_field.bit_field_sub_if %>),
4
+ .bit_field_if (<%= bit_field_if %>),
5
5
  .i_value (<%= initial_value %>)
6
6
  );
@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :rof) do
4
4
  register_map do
5
5
  read_only
6
6
  non_volatile
7
- need_initial_value
7
+ initial_value require: true
8
8
  end
9
9
 
10
10
  sv_rtl do
@@ -2,12 +2,12 @@
2
2
  <% if [:w0s, :w1s].include?(bit_field.type) %>
3
3
  .SET_VALUE (<%= set_value %>),
4
4
  <% end %>
5
- .WIDTH (<%= bit_field.width %>),
5
+ .WIDTH (<%= width %>),
6
6
  .INITIAL_VALUE (<%= initial_value %>)
7
7
  ) u_bit_field (
8
8
  .i_clk (<%= register_block.clock %>),
9
9
  .i_rst_n (<%= register_block.reset %>),
10
- .bit_field_if (<%= bit_field.bit_field_sub_if %>),
11
- .i_clear (<%= clear[bit_field.loop_variables] %>),
12
- .o_value (<%= value_out[bit_field.loop_variables] %>)
10
+ .bit_field_if (<%= bit_field_if %>),
11
+ .i_clear (<%= clear[loop_variables] %>),
12
+ .o_value (<%= value_out[loop_variables] %>)
13
13
  );
@@ -3,14 +3,14 @@
3
3
  RgGen.define_list_item_feature(:bit_field, :type, :rs) do
4
4
  register_map do
5
5
  read_only
6
- need_initial_value
6
+ initial_value require: true
7
7
  end
8
8
  end
9
9
 
10
10
  RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
11
11
  register_map do
12
12
  read_write
13
- need_initial_value
13
+ initial_value require: true
14
14
  end
15
15
  end
16
16
 
@@ -18,18 +18,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
18
18
  sv_rtl do
19
19
  build do
20
20
  input :register_block, :clear, {
21
- name: "i_#{full_name}_clear",
22
- data_type: :logic,
23
- width: bit_field.width,
24
- array_size: bit_field.array_size,
25
- array_format: array_port_format
21
+ name: "i_#{full_name}_clear", data_type: :logic, width: width,
22
+ array_size: array_size, array_format: array_port_format
26
23
  }
27
24
  output :register_block, :value_out, {
28
- name: "o_#{full_name}",
29
- data_type: :logic,
30
- width: bit_field.width,
31
- array_size: bit_field.array_size,
32
- array_format: array_port_format
25
+ name: "o_#{full_name}", data_type: :logic, width: width,
26
+ array_size: array_size, array_format: array_port_format
33
27
  }
34
28
  end
35
29
 
@@ -1,9 +1,9 @@
1
1
  rggen_bit_field_<%= bit_field.type %> #(
2
- .WIDTH (<%= bit_field.width %>),
2
+ .WIDTH (<%= width %>),
3
3
  .INITIAL_VALUE (<%= initial_value %>)
4
4
  ) u_bit_field (
5
5
  .i_clk (<%= register_block.clock %>),
6
6
  .i_rst_n (<%= register_block.reset %>),
7
- .bit_field_if (<%= bit_field.bit_field_sub_if %>),
8
- .o_value (<%= value_out[bit_field.loop_variables] %>)
7
+ .bit_field_if (<%= bit_field_if %>),
8
+ .o_value (<%= value_out[loop_variables] %>)
9
9
  );
@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :rw) do
4
4
  register_map do
5
5
  read_write
6
6
  non_volatile
7
- need_initial_value
7
+ initial_value require: true
8
8
  end
9
9
  end
10
10
 
@@ -12,7 +12,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :wo) do
12
12
  register_map do
13
13
  write_only
14
14
  non_volatile
15
- need_initial_value
15
+ initial_value require: true
16
16
  end
17
17
  end
18
18
 
@@ -20,11 +20,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
20
20
  sv_rtl do
21
21
  build do
22
22
  output :register_block, :value_out, {
23
- name: "o_#{full_name}",
24
- data_type: :logic,
25
- width: bit_field.width,
26
- array_size: bit_field.array_size,
27
- array_format: array_port_format
23
+ name: "o_#{full_name}", data_type: :logic, width: width,
24
+ array_size: array_size, array_format: array_port_format
28
25
  }
29
26
  end
30
27
 
@@ -0,0 +1,16 @@
1
+ rggen_bit_field_<%= bit_field.type %> #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>)
4
+ ) u_bit_field (
5
+ .i_clk (<%= register_block.clock %>),
6
+ .i_rst_n (<%= register_block.reset %>),
7
+ .bit_field_if (<%= bit_field_if %>),
8
+ <% if bit_field.type == :rwc %>
9
+ .i_clear (<%= control_signal %>),
10
+ <% elsif bit_field.type == :rwe %>
11
+ .i_enable (<%= control_signal %>),
12
+ <% else %>
13
+ .i_lock (<%= control_signal %>),
14
+ <% end %>
15
+ .o_value (<%= value_out[loop_variables] %>)
16
+ );
@@ -0,0 +1,92 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwe, :rwl]) do
4
+ register_map do
5
+ read_write
6
+ volatile? { bit_field.type == :rwc || !bit_field.reference? }
7
+ initial_value require: true
8
+ reference use: true, width: 1
9
+ end
10
+
11
+ sv_rtl do
12
+ build do
13
+ if clear_port?
14
+ input :register_block, :clear, {
15
+ name: "i_#{full_name}_clear", data_type: :logic, width: 1,
16
+ array_size: array_size, array_format: array_port_format
17
+ }
18
+ end
19
+ if enable_port?
20
+ input :register_block, :enable, {
21
+ name: "i_#{full_name}_enable", data_type: :logic, width: 1,
22
+ array_size: array_size, array_format: array_port_format
23
+ }
24
+ end
25
+ if lock_port?
26
+ input :register_block, :lock, {
27
+ name: "i_#{full_name}_lock", data_type: :logic, width: 1,
28
+ array_size: array_size, array_format: array_port_format
29
+ }
30
+ end
31
+ output :register_block, :value_out, {
32
+ name: "o_#{full_name}", data_type: :logic, width: width,
33
+ array_size: array_size, array_format: array_port_format
34
+ }
35
+ end
36
+
37
+ main_code :bit_field, from_template: true
38
+
39
+ private
40
+
41
+ def clear_port?
42
+ bit_field.type == :rwc && !bit_field.reference?
43
+ end
44
+
45
+ def enable_port?
46
+ bit_field.type == :rwe && !bit_field.reference?
47
+ end
48
+
49
+ def lock_port?
50
+ bit_field.type == :rwl && !bit_field.reference?
51
+ end
52
+
53
+ def control_signal
54
+ reference_bit_field || control_port[loop_variables]
55
+ end
56
+
57
+ def control_port
58
+ case bit_field.type
59
+ when :rwc
60
+ clear
61
+ when :rwe
62
+ enable
63
+ when :rwl
64
+ lock
65
+ end
66
+ end
67
+ end
68
+ end
69
+
70
+ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
71
+ sv_ral do
72
+ access 'RW'
73
+ end
74
+ end
75
+
76
+ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
77
+ sv_ral do
78
+ model_name do
79
+ "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
80
+ end
81
+
82
+ private
83
+
84
+ def reference_names
85
+ reference = bit_field.reference
86
+ register = reference&.register
87
+ [register&.name, reference&.name]
88
+ .map { |name| string(name) }
89
+ .join(', ')
90
+ end
91
+ end
92
+ end
@@ -0,0 +1,9 @@
1
+ rggen_bit_field_w01trg #(
2
+ .TRIGGER_VALUE (<%= trigger_value %>),
3
+ .WIDTH (<%= width %>)
4
+ ) u_bit_field (
5
+ .i_clk (<%= register_block.clock %>),
6
+ .i_rst_n (<%= register_block.reset %>),
7
+ .bit_field_if (<%= bit_field_if %>),
8
+ .o_trigger (<%= trigger[loop_variables] %>)
9
+ );
@@ -0,0 +1,29 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
4
+ register_map do
5
+ write_only
6
+ non_volatile
7
+ end
8
+
9
+ sv_rtl do
10
+ build do
11
+ output :register_block, :trigger, {
12
+ name: "o_#{full_name}_trigger", data_type: :logic, width: width,
13
+ array_size: array_size, array_format: array_port_format
14
+ }
15
+ end
16
+
17
+ main_code :bit_field, from_template: true
18
+
19
+ private
20
+
21
+ def trigger_value
22
+ bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
23
+ end
24
+ end
25
+
26
+ sv_ral do
27
+ model_name { "rggen_ral_#{bit_field.type}_field" }
28
+ end
29
+ end
@@ -195,6 +195,10 @@ RgGen.define_list_feature(:register, :type) do
195
195
  register.writable? && 1 || 0
196
196
  end
197
197
 
198
+ def bus_width
199
+ configuration.bus_width
200
+ end
201
+
198
202
  def address_width
199
203
  register_block.local_address_width
200
204
  end
@@ -203,6 +207,10 @@ RgGen.define_list_feature(:register, :type) do
203
207
  hex(register.offset_address, address_width)
204
208
  end
205
209
 
210
+ def width
211
+ register.width
212
+ end
213
+
206
214
  def valid_bits
207
215
  bits = register.bit_fields.map(&:bit_map).inject(:|)
208
216
  hex(bits, register.width)
@@ -215,6 +223,10 @@ RgGen.define_list_feature(:register, :type) do
215
223
  def register_if
216
224
  register_block.register_if[register.index]
217
225
  end
226
+
227
+ def bit_field_if
228
+ register.bit_field_if
229
+ end
218
230
  end
219
231
 
220
232
  default_feature do
@@ -3,13 +3,13 @@ rggen_default_register #(
3
3
  .WRITABLE (<%= writable %>),
4
4
  .ADDRESS_WIDTH (<%= address_width %>),
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
- .BUS_WIDTH (<%= configuration.bus_width %>),
7
- .DATA_WIDTH (<%= register.width %>),
6
+ .BUS_WIDTH (<%= bus_width %>),
7
+ .DATA_WIDTH (<%= width %>),
8
8
  .VALID_BITS (<%= valid_bits %>),
9
9
  .REGISTER_INDEX (<%= register_index %>)
10
10
  ) u_register (
11
11
  .i_clk (<%= register_block.clock %>),
12
12
  .i_rst_n (<%= register_block.reset %>),
13
13
  .register_if (<%= register_if %>),
14
- .bit_field_if (<%= register.bit_field_if %>)
14
+ .bit_field_if (<%= bit_field_if %>)
15
15
  );
@@ -25,47 +25,38 @@ RgGen.define_list_item_feature(:register, :type, :external) do
25
25
  else
26
26
  output :register_block, :valid, {
27
27
  name: "o_#{register.name}_valid",
28
- data_type: :logic,
29
- width: 1
28
+ data_type: :logic, width: 1
30
29
  }
31
30
  output :register_block, :address, {
32
31
  name: "o_#{register.name}_address",
33
- data_type: :logic,
34
- width: address_width
32
+ data_type: :logic, width: address_width
35
33
  }
36
34
  output :register_block, :write, {
37
35
  name: "o_#{register.name}_write",
38
- data_type: :logic,
39
- width: 1
36
+ data_type: :logic, width: 1
40
37
  }
41
38
  output :register_block, :write_data, {
42
39
  name: "o_#{register.name}_data",
43
- data_type: :logic,
44
- width: bus_width
40
+ data_type: :logic, width: bus_width
45
41
  }
46
42
  output :register_block, :strobe, {
47
43
  name: "o_#{register.name}_strobe",
48
- data_type: :logic,
49
- width: byte_width
44
+ data_type: :logic, width: byte_width
50
45
  }
51
46
  input :register_block, :ready, {
52
47
  name: "i_#{register.name}_ready",
53
- data_type: :logic,
54
- width: 1
48
+ data_type: :logic, width: 1
55
49
  }
56
50
  input :register_block, :status, {
57
51
  name: "i_#{register.name}_status",
58
- data_type: :logic,
59
- width: 2
52
+ data_type: :logic, width: 2
60
53
  }
61
54
  input :register_block, :read_data, {
62
55
  name: "i_#{register.name}_data",
63
- data_type: :logic,
64
- width: bus_width
56
+ data_type: :logic, width: bus_width
65
57
  }
66
58
  interface :register, :bus_if, {
67
- name: 'bus_if',
68
- interface_type: 'rggen_bus_if',
59
+ name: 'bus_if', interface_type: 'rggen_bus_if',
69
60
  parameter_values: [address_width, bus_width],
70
61
  variables: [
71
62
  'valid', 'address', 'write', 'write_data', 'strobe',
@@ -97,10 +88,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
97
88
  register_block.local_address_width
98
89
  end
99
90
 
100
- def bus_width
101
- configuration.bus_width
102
- end
103
-
104
91
  def byte_width
105
92
  configuration.byte_width
106
93
  end
@@ -254,9 +254,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
254
254
 
255
255
  sv_rtl do
256
256
  build do
257
- logic :register, :indirect_index, {
258
- width: index_width
259
- }
257
+ logic :register, :indirect_index, { width: index_width }
260
258
  end
261
259
 
262
260
  main_code :register do |code|
@@ -3,8 +3,8 @@ rggen_indirect_register #(
3
3
  .WRITABLE (<%= writable %>),
4
4
  .ADDRESS_WIDTH (<%= address_width %>),
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
- .BUS_WIDTH (<%= configuration.bus_width %>),
7
- .DATA_WIDTH (<%= register.width %>),
6
+ .BUS_WIDTH (<%= bus_width %>),
7
+ .DATA_WIDTH (<%= width %>),
8
8
  .VALID_BITS (<%= valid_bits %>),
9
9
  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
10
10
  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
@@ -13,5 +13,5 @@ rggen_indirect_register #(
13
13
  .i_rst_n (<%= register_block.reset %>),
14
14
  .register_if (<%= register_if %>),
15
15
  .i_indirect_index (<%= indirect_index %>),
16
- .bit_field_if (<%= register.bit_field_if %>)
16
+ .bit_field_if (<%= bit_field_if %>)
17
17
  );
@@ -62,6 +62,34 @@ RgGen.define_list_feature(:register_block, :protocol) do
62
62
  sv_rtl do
63
63
  shared_context.feature_registry(registry)
64
64
 
65
+ base_feature do
66
+ private
67
+
68
+ def address_width
69
+ configuration.address_width
70
+ end
71
+
72
+ def bus_width
73
+ configuration.bus_width
74
+ end
75
+
76
+ def byte_width
77
+ configuration.byte_width
78
+ end
79
+
80
+ def local_address_width
81
+ register_block.local_address_width
82
+ end
83
+
84
+ def total_registers
85
+ register_block.total_registers
86
+ end
87
+
88
+ def register_if
89
+ register_block.register_if
90
+ end
91
+ end
92
+
65
93
  factory do
66
94
  def select_feature(configuration, _register_block)
67
95
  target_features[configuration.protocol]