rggen 0.10.0 → 0.11.0

data/lib/rggen/built_in/bit_field/type/rof.erb

@@ -1,6 +1,6 @@
 rggen_bit_field_ro #(
-  .WIDTH  (<%= bit_field.width %>)
+  .WIDTH  (<%= width %>)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .bit_field_if (<%= bit_field_if %>),
   .i_value      (<%= initial_value %>)
 );

data/lib/rggen/built_in/bit_field/type/rof.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :rof) do
   register_map do
     read_only
     non_volatile
-    need_initial_value
+    initial_value require: true
   end
 
   sv_rtl do

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb

@@ -2,12 +2,12 @@
 <% if [:w0s, :w1s].include?(bit_field.type) %>
   .SET_VALUE      (<%= set_value %>),
 <% end %>
-  .WIDTH          (<%= bit_field.width %>),
+  .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
-  .i_clear      (<%= clear[bit_field.loop_variables] %>),
-  .o_value      (<%= value_out[bit_field.loop_variables] %>)
+  .bit_field_if (<%= bit_field_if %>),
+  .i_clear      (<%= clear[loop_variables] %>),
+  .o_value      (<%= value_out[loop_variables] %>)
 );

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb

@@ -3,14 +3,14 @@
 RgGen.define_list_item_feature(:bit_field, :type, :rs) do
   register_map do
     read_only
-    need_initial_value
+    initial_value require: true
   end
 end
 
 RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
   register_map do
     read_write
-    need_initial_value
+    initial_value require: true
   end
 end
 
@@ -18,18 +18,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
   sv_rtl do
     build do
       input :register_block, :clear, {
-        name: "i_#{full_name}_clear",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
+        name: "i_#{full_name}_clear", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
       }
       output :register_block, :value_out, {
-        name: "o_#{full_name}",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
       }
     end
 

data/lib/rggen/built_in/bit_field/type/rw_wo.erb

@@ -1,9 +1,9 @@
 rggen_bit_field_<%= bit_field.type %> #(
-  .WIDTH          (<%= bit_field.width %>),
+  .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
-  .o_value      (<%= value_out[bit_field.loop_variables] %>)
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
 );

data/lib/rggen/built_in/bit_field/type/rw_wo.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :rw) do
   register_map do
     read_write
     non_volatile
-    need_initial_value
+    initial_value require: true
   end
 end
 
@@ -12,7 +12,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :wo) do
   register_map do
     write_only
     non_volatile
-    need_initial_value
+    initial_value require: true
   end
 end
 
@@ -20,11 +20,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
   sv_rtl do
     build do
       output :register_block, :value_out, {
-        name: "o_#{full_name}",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
       }
     end
 

data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+<% if bit_field.type == :rwc %>
+  .i_clear      (<%= control_signal %>),
+<% elsif bit_field.type == :rwe %>
+  .i_enable     (<%= control_signal %>),
+<% else %>
+  .i_lock       (<%= control_signal %>),
+<% end %>
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb

@@ -0,0 +1,92 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwe, :rwl]) do
+  register_map do
+    read_write
+    volatile? { bit_field.type == :rwc || !bit_field.reference? }
+    initial_value require: true
+    reference use: true, width: 1
+  end
+
+  sv_rtl do
+    build do
+      if clear_port?
+        input :register_block, :clear, {
+          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if enable_port?
+        input :register_block, :enable, {
+          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if lock_port?
+        input :register_block, :lock, {
+          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_port?
+      bit_field.type == :rwc && !bit_field.reference?
+    end
+
+    def enable_port?
+      bit_field.type == :rwe && !bit_field.reference?
+    end
+
+    def lock_port?
+      bit_field.type == :rwl && !bit_field.reference?
+    end
+
+    def control_signal
+      reference_bit_field || control_port[loop_variables]
+    end
+
+    def control_port
+      case bit_field.type
+      when :rwc
+        clear
+      when :rwe
+        enable
+      when :rwl
+        lock
+      end
+    end
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  sv_ral do
+    access 'RW'
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  sv_ral do
+    model_name do
+      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
+    end
+
+    private
+
+    def reference_names
+      reference = bit_field.reference
+      register = reference&.register
+      [register&.name, reference&.name]
+        .map { |name| string(name) }
+        .join(', ')
+    end
+  end
+end

data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_trigger    (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  register_map do
+    write_only
+    non_volatile
+  end
+
+  sv_rtl do
+    build do
+      output :register_block, :trigger, {
+        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
+    end
+  end
+
+  sv_ral do
+    model_name { "rggen_ral_#{bit_field.type}_field" }
+  end
+end

data/lib/rggen/built_in/register/type.rb

@@ -195,6 +195,10 @@ RgGen.define_list_feature(:register, :type) do
         register.writable? && 1 || 0
       end
 
+      def bus_width
+        configuration.bus_width
+      end
+
       def address_width
         register_block.local_address_width
       end
@@ -203,6 +207,10 @@ RgGen.define_list_feature(:register, :type) do
         hex(register.offset_address, address_width)
       end
 
+      def width
+        register.width
+      end
+
       def valid_bits
         bits = register.bit_fields.map(&:bit_map).inject(:|)
         hex(bits, register.width)
@@ -215,6 +223,10 @@ RgGen.define_list_feature(:register, :type) do
       def register_if
         register_block.register_if[register.index]
       end
+
+      def bit_field_if
+        register.bit_field_if
+      end
     end
 
     default_feature do

data/lib/rggen/built_in/register/type/default_sv_rtl.erb

@@ -3,13 +3,13 @@ rggen_default_register #(
   .WRITABLE       (<%= writable %>),
   .ADDRESS_WIDTH  (<%= address_width %>),
   .OFFSET_ADDRESS (<%= offset_address %>),
-  .BUS_WIDTH      (<%= configuration.bus_width %>),
-  .DATA_WIDTH     (<%= register.width %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>),
   .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),
   .register_if  (<%= register_if %>),
-  .bit_field_if (<%= register.bit_field_if %>)
+  .bit_field_if (<%= bit_field_if %>)
 );

data/lib/rggen/built_in/register/type/external.rb

@@ -25,47 +25,38 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       else
         output :register_block, :valid, {
           name: "o_#{register.name}_valid",
-          data_type: :logic,
-          width: 1
+          data_type: :logic, width: 1
         }
         output :register_block, :address, {
           name: "o_#{register.name}_address",
-          data_type: :logic,
-          width: address_width
+          data_type: :logic, width: address_width
         }
         output :register_block, :write, {
           name: "o_#{register.name}_write",
-          data_type: :logic,
-          width: 1
+          data_type: :logic, width: 1
         }
         output :register_block, :write_data, {
           name: "o_#{register.name}_data",
-          data_type: :logic,
-          width: bus_width
+          data_type: :logic, width: bus_width
         }
         output :register_block, :strobe, {
           name: "o_#{register.name}_strobe",
-          data_type: :logic,
-          width: byte_width
+          data_type: :logic, width: byte_width
         }
         input :register_block, :ready, {
           name: "i_#{register.name}_ready",
-          data_type: :logic,
-          width: 1
+          data_type: :logic, width: 1
         }
         input :register_block, :status, {
           name: "i_#{register.name}_status",
-          data_type: :logic,
-          width: 2
+          data_type: :logic, width: 2
         }
         input :register_block, :read_data, {
           name: "i_#{register.name}_data",
-          data_type: :logic,
-          width: bus_width
+          data_type: :logic, width: bus_width
         }
         interface :register, :bus_if, {
-          name: 'bus_if',
-          interface_type: 'rggen_bus_if',
+          name: 'bus_if', interface_type: 'rggen_bus_if',
           parameter_values: [address_width, bus_width],
           variables: [
             'valid', 'address', 'write', 'write_data', 'strobe',
@@ -97,10 +88,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       register_block.local_address_width
     end
 
-    def bus_width
-      configuration.bus_width
-    end
-
     def byte_width
       configuration.byte_width
     end

data/lib/rggen/built_in/register/type/indirect.rb

@@ -254,9 +254,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
 
   sv_rtl do
     build do
-      logic :register, :indirect_index, {
-        width: index_width
-      }
+      logic :register, :indirect_index, { width: index_width }
     end
 
     main_code :register do |code|

data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb

@@ -3,8 +3,8 @@ rggen_indirect_register #(
   .WRITABLE             (<%= writable %>),
   .ADDRESS_WIDTH        (<%= address_width %>),
   .OFFSET_ADDRESS       (<%= offset_address %>),
-  .BUS_WIDTH            (<%= configuration.bus_width %>),
-  .DATA_WIDTH           (<%= register.width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .DATA_WIDTH           (<%= width %>),
   .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
@@ -13,5 +13,5 @@ rggen_indirect_register #(
   .i_rst_n          (<%= register_block.reset %>),
   .register_if      (<%= register_if %>),
   .i_indirect_index (<%= indirect_index %>),
-  .bit_field_if     (<%= register.bit_field_if %>)
+  .bit_field_if     (<%= bit_field_if %>)
 );

data/lib/rggen/built_in/register_block/protocol.rb

@@ -62,6 +62,34 @@ RgGen.define_list_feature(:register_block, :protocol) do
   sv_rtl do
     shared_context.feature_registry(registry)
 
+    base_feature do
+      private
+
+      def address_width
+        configuration.address_width
+      end
+
+      def bus_width
+        configuration.bus_width
+      end
+
+      def byte_width
+        configuration.byte_width
+      end
+
+      def local_address_width
+        register_block.local_address_width
+      end
+
+      def total_registers
+        register_block.total_registers
+      end
+
+      def register_if
+        register_block.register_if
+      end
+    end
+
     factory do
       def select_feature(configuration, _register_block)
         target_features[configuration.protocol]