rggen 0.10.0 → 0.11.0

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Files changed (44) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +3 -3
  3. data/lib/rggen/built_in.rb +3 -2
  4. data/lib/rggen/built_in/bit_field/initial_value.rb +22 -0
  5. data/lib/rggen/built_in/bit_field/reference.rb +40 -1
  6. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +4 -2
  7. data/lib/rggen/built_in/bit_field/type.rb +44 -80
  8. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +4 -4
  9. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +11 -20
  10. data/lib/rggen/built_in/bit_field/type/reserved.erb +1 -1
  11. data/lib/rggen/built_in/bit_field/type/ro.erb +2 -2
  12. data/lib/rggen/built_in/bit_field/type/ro.rb +4 -7
  13. data/lib/rggen/built_in/bit_field/type/rof.erb +2 -2
  14. data/lib/rggen/built_in/bit_field/type/rof.rb +1 -1
  15. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +4 -4
  16. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +6 -12
  17. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +3 -3
  18. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +4 -7
  19. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +16 -0
  20. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +92 -0
  21. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +9 -0
  22. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +29 -0
  23. data/lib/rggen/built_in/register/type.rb +12 -0
  24. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +3 -3
  25. data/lib/rggen/built_in/register/type/external.rb +9 -22
  26. data/lib/rggen/built_in/register/type/indirect.rb +1 -3
  27. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +3 -3
  28. data/lib/rggen/built_in/register_block/protocol.rb +28 -0
  29. data/lib/rggen/built_in/register_block/protocol/apb.erb +4 -4
  30. data/lib/rggen/built_in/register_block/protocol/apb.rb +14 -38
  31. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +4 -4
  32. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +22 -64
  33. data/lib/rggen/built_in/register_block/sv_ral_package.rb +13 -6
  34. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +8 -9
  35. data/lib/rggen/built_in/version.rb +1 -1
  36. data/lib/rggen/setup/default.rb +3 -2
  37. data/sample/block_0.rb +9 -4
  38. data/sample/block_0.sv +97 -20
  39. data/sample/block_0.xlsx +0 -0
  40. data/sample/block_0.yml +9 -4
  41. data/sample/block_0_ral_pkg.sv +16 -6
  42. metadata +11 -9
  43. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +0 -14
  44. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +0 -39
Binary file
@@ -26,8 +26,9 @@ register_blocks: [
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  name: register_2,
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  offset_address: 0x04,
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  bit_fields: [
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- { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wo, initial_value: 0 },
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- { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: wo, initial_value: 0 }
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+ { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: wo, initial_value: 0 },
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+ { name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: w0trg },
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+ { name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: w1trg }
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  ]
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  },
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  {
@@ -44,8 +45,12 @@ register_blocks: [
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  name: register_4,
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  offset_address: 0x0C,
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  bit_fields: [
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- { name: bit_field_0, bit_assignment: { lsb: 0 , width: 8 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
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- { name: bit_field_1, bit_assignment: { lsb: 16, width: 8 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
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+ { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rwc, initial_value: 0 },
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+ { name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rwc, initial_value: 0, reference: register_2.bit_field_1 },
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+ { name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: rwe, initial_value: 0 },
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+ { name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
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+ { name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: rwl, initial_value: 0 },
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+ { name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
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  ]
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  },
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  {
@@ -33,13 +33,15 @@ package block_0_ral_pkg;
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  endclass
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  class register_2_reg_model extends rggen_ral_reg;
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  rand rggen_ral_field bit_field_0;
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- rand rggen_ral_field bit_field_1;
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+ rand rggen_ral_w0trg_field bit_field_1;
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+ rand rggen_ral_w1trg_field bit_field_2;
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  function new(string name);
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  super.new(name, 32, 0);
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  endfunction
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  function void build();
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  `rggen_ral_create_field_model(bit_field_0, 0, 4, WO, 0, 4'h0, 1)
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- `rggen_ral_create_field_model(bit_field_1, 8, 4, WO, 0, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_1, 8, 4, W0TRG, 0, 4'h0, 0)
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+ `rggen_ral_create_field_model(bit_field_2, 16, 4, W1TRG, 0, 4'h0, 0)
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  endfunction
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  endclass
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  class register_3_reg_model extends rggen_ral_reg;
@@ -58,14 +60,22 @@ package block_0_ral_pkg;
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  endfunction
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  endclass
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  class register_4_reg_model extends rggen_ral_reg;
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- rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_0;
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- rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_1;
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+ rand rggen_ral_field bit_field_0;
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+ rand rggen_ral_field bit_field_1;
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+ rand rggen_ral_rwe_field #("", "") bit_field_2;
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+ rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_3;
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+ rand rggen_ral_rwl_field #("", "") bit_field_4;
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+ rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_5;
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  function new(string name);
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  super.new(name, 32, 0);
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  endfunction
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  function void build();
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- `rggen_ral_create_field_model(bit_field_0, 0, 8, RWE, 0, 8'h00, 1)
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- `rggen_ral_create_field_model(bit_field_1, 16, 8, RWL, 0, 8'h00, 1)
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+ `rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 1, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 1, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_2, 8, 4, RWE, 1, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_3, 12, 4, RWE, 0, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_4, 16, 4, RWL, 1, 4'h0, 1)
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+ `rggen_ral_create_field_model(bit_field_5, 20, 4, RWL, 0, 4'h0, 1)
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  endfunction
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  endclass
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  class register_5_reg_model extends rggen_ral_reg;
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.10.0
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+ version: 0.11.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2019-07-31 00:00:00.000000000 Z
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+ date: 2019-08-11 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-core
@@ -16,14 +16,14 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.10'
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+ version: '0.11'
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.10'
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+ version: '0.11'
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  - !ruby/object:Gem::Dependency
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  name: rggen-spreadsheet-loader
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  requirement: !ruby/object:Gem::Requirement
@@ -44,14 +44,14 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.10'
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+ version: '0.11'
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.10'
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+ version: '0.11'
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
@@ -69,7 +69,7 @@ dependencies:
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  description: |
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  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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  It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
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- from human readable register map documents.
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+ from human readable register map specifications.
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  email:
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  - rggen@googlegroups.com
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  executables: []
@@ -100,8 +100,10 @@ files:
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  - lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb
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  - lib/rggen/built_in/bit_field/type/rw_wo.erb
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  - lib/rggen/built_in/bit_field/type/rw_wo.rb
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- - lib/rggen/built_in/bit_field/type/rwe_rwl.erb
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- - lib/rggen/built_in/bit_field/type/rwe_rwl.rb
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+ - lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb
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+ - lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb
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+ - lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb
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+ - lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb
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  - lib/rggen/built_in/global/address_width.rb
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  - lib/rggen/built_in/global/array_port_format.rb
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  - lib/rggen/built_in/global/bus_width.rb
@@ -1,14 +0,0 @@
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- rggen_bit_field_<%= bit_field.type %> #(
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- .WIDTH (<%= bit_field.width %>),
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- .INITIAL_VALUE (<%= initial_value %>)
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- ) u_bit_field (
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- .i_clk (<%= register_block.clock %>),
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- .i_rst_n (<%= register_block.reset %>),
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- .bit_field_if (<%= bit_field.bit_field_sub_if %>),
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- <% if bit_field.type == :rwe %>
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- .i_enable (<%= reference_bit_field %>),
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- <% else %>
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- .i_lock (<%= reference_bit_field %>),
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- <% end %>
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- .o_value (<%= value_out[bit_field.loop_variables] %>)
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- );
@@ -1,39 +0,0 @@
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- # frozen_string_literal: true
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-
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- RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
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- register_map do
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- read_write
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- non_volatile
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- need_initial_value
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- use_reference required: true, width: 1
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- end
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-
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- sv_rtl do
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- build do
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- output :register_block, :value_out, {
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- name: "o_#{full_name}",
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- data_type: :logic,
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- width: bit_field.width,
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- array_size: bit_field.array_size,
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- array_format: array_port_format
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- }
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- end
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-
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- main_code :bit_field, from_template: true
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- end
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-
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- sv_ral do
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- model_name do
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- "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
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- end
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-
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- private
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-
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- def reference_names
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- reference = bit_field.find_reference(register_block.bit_fields)
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- [reference.register.name, reference.name]
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- .map { |name| string(name) }
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- .join(', ')
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- end
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- end
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- end