rggen 0.10.0 → 0.11.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +3 -3
- data/lib/rggen/built_in.rb +3 -2
- data/lib/rggen/built_in/bit_field/initial_value.rb +22 -0
- data/lib/rggen/built_in/bit_field/reference.rb +40 -1
- data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +4 -2
- data/lib/rggen/built_in/bit_field/type.rb +44 -80
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +4 -4
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +11 -20
- data/lib/rggen/built_in/bit_field/type/reserved.erb +1 -1
- data/lib/rggen/built_in/bit_field/type/ro.erb +2 -2
- data/lib/rggen/built_in/bit_field/type/ro.rb +4 -7
- data/lib/rggen/built_in/bit_field/type/rof.erb +2 -2
- data/lib/rggen/built_in/bit_field/type/rof.rb +1 -1
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +4 -4
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +6 -12
- data/lib/rggen/built_in/bit_field/type/rw_wo.erb +3 -3
- data/lib/rggen/built_in/bit_field/type/rw_wo.rb +4 -7
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +16 -0
- data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +92 -0
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +9 -0
- data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +29 -0
- data/lib/rggen/built_in/register/type.rb +12 -0
- data/lib/rggen/built_in/register/type/default_sv_rtl.erb +3 -3
- data/lib/rggen/built_in/register/type/external.rb +9 -22
- data/lib/rggen/built_in/register/type/indirect.rb +1 -3
- data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +3 -3
- data/lib/rggen/built_in/register_block/protocol.rb +28 -0
- data/lib/rggen/built_in/register_block/protocol/apb.erb +4 -4
- data/lib/rggen/built_in/register_block/protocol/apb.rb +14 -38
- data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +4 -4
- data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +22 -64
- data/lib/rggen/built_in/register_block/sv_ral_package.rb +13 -6
- data/lib/rggen/built_in/register_block/sv_rtl_top.rb +8 -9
- data/lib/rggen/built_in/version.rb +1 -1
- data/lib/rggen/setup/default.rb +3 -2
- data/sample/block_0.rb +9 -4
- data/sample/block_0.sv +97 -20
- data/sample/block_0.xlsx +0 -0
- data/sample/block_0.yml +9 -4
- data/sample/block_0_ral_pkg.sv +16 -6
- metadata +11 -9
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +0 -14
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +0 -39
data/sample/block_0.xlsx
CHANGED
Binary file
|
data/sample/block_0.yml
CHANGED
@@ -26,8 +26,9 @@ register_blocks: [
|
|
26
26
|
name: register_2,
|
27
27
|
offset_address: 0x04,
|
28
28
|
bit_fields: [
|
29
|
-
{ name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wo, initial_value: 0 },
|
30
|
-
{ name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type:
|
29
|
+
{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: wo, initial_value: 0 },
|
30
|
+
{ name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: w0trg },
|
31
|
+
{ name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: w1trg }
|
31
32
|
]
|
32
33
|
},
|
33
34
|
{
|
@@ -44,8 +45,12 @@ register_blocks: [
|
|
44
45
|
name: register_4,
|
45
46
|
offset_address: 0x0C,
|
46
47
|
bit_fields: [
|
47
|
-
{ name: bit_field_0, bit_assignment: { lsb: 0 , width:
|
48
|
-
{ name: bit_field_1, bit_assignment: { lsb:
|
48
|
+
{ name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rwc, initial_value: 0 },
|
49
|
+
{ name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rwc, initial_value: 0, reference: register_2.bit_field_1 },
|
50
|
+
{ name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: rwe, initial_value: 0 },
|
51
|
+
{ name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
|
52
|
+
{ name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: rwl, initial_value: 0 },
|
53
|
+
{ name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
|
49
54
|
]
|
50
55
|
},
|
51
56
|
{
|
data/sample/block_0_ral_pkg.sv
CHANGED
@@ -33,13 +33,15 @@ package block_0_ral_pkg;
|
|
33
33
|
endclass
|
34
34
|
class register_2_reg_model extends rggen_ral_reg;
|
35
35
|
rand rggen_ral_field bit_field_0;
|
36
|
-
rand
|
36
|
+
rand rggen_ral_w0trg_field bit_field_1;
|
37
|
+
rand rggen_ral_w1trg_field bit_field_2;
|
37
38
|
function new(string name);
|
38
39
|
super.new(name, 32, 0);
|
39
40
|
endfunction
|
40
41
|
function void build();
|
41
42
|
`rggen_ral_create_field_model(bit_field_0, 0, 4, WO, 0, 4'h0, 1)
|
42
|
-
`rggen_ral_create_field_model(bit_field_1, 8, 4,
|
43
|
+
`rggen_ral_create_field_model(bit_field_1, 8, 4, W0TRG, 0, 4'h0, 0)
|
44
|
+
`rggen_ral_create_field_model(bit_field_2, 16, 4, W1TRG, 0, 4'h0, 0)
|
43
45
|
endfunction
|
44
46
|
endclass
|
45
47
|
class register_3_reg_model extends rggen_ral_reg;
|
@@ -58,14 +60,22 @@ package block_0_ral_pkg;
|
|
58
60
|
endfunction
|
59
61
|
endclass
|
60
62
|
class register_4_reg_model extends rggen_ral_reg;
|
61
|
-
rand
|
62
|
-
rand
|
63
|
+
rand rggen_ral_field bit_field_0;
|
64
|
+
rand rggen_ral_field bit_field_1;
|
65
|
+
rand rggen_ral_rwe_field #("", "") bit_field_2;
|
66
|
+
rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_3;
|
67
|
+
rand rggen_ral_rwl_field #("", "") bit_field_4;
|
68
|
+
rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_5;
|
63
69
|
function new(string name);
|
64
70
|
super.new(name, 32, 0);
|
65
71
|
endfunction
|
66
72
|
function void build();
|
67
|
-
`rggen_ral_create_field_model(bit_field_0, 0,
|
68
|
-
`rggen_ral_create_field_model(bit_field_1,
|
73
|
+
`rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 1, 4'h0, 1)
|
74
|
+
`rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 1, 4'h0, 1)
|
75
|
+
`rggen_ral_create_field_model(bit_field_2, 8, 4, RWE, 1, 4'h0, 1)
|
76
|
+
`rggen_ral_create_field_model(bit_field_3, 12, 4, RWE, 0, 4'h0, 1)
|
77
|
+
`rggen_ral_create_field_model(bit_field_4, 16, 4, RWL, 1, 4'h0, 1)
|
78
|
+
`rggen_ral_create_field_model(bit_field_5, 20, 4, RWL, 0, 4'h0, 1)
|
69
79
|
endfunction
|
70
80
|
endclass
|
71
81
|
class register_5_reg_model extends rggen_ral_reg;
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.11.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2019-
|
11
|
+
date: 2019-08-11 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: rggen-core
|
@@ -16,14 +16,14 @@ dependencies:
|
|
16
16
|
requirements:
|
17
17
|
- - "~>"
|
18
18
|
- !ruby/object:Gem::Version
|
19
|
-
version: '0.
|
19
|
+
version: '0.11'
|
20
20
|
type: :runtime
|
21
21
|
prerelease: false
|
22
22
|
version_requirements: !ruby/object:Gem::Requirement
|
23
23
|
requirements:
|
24
24
|
- - "~>"
|
25
25
|
- !ruby/object:Gem::Version
|
26
|
-
version: '0.
|
26
|
+
version: '0.11'
|
27
27
|
- !ruby/object:Gem::Dependency
|
28
28
|
name: rggen-spreadsheet-loader
|
29
29
|
requirement: !ruby/object:Gem::Requirement
|
@@ -44,14 +44,14 @@ dependencies:
|
|
44
44
|
requirements:
|
45
45
|
- - "~>"
|
46
46
|
- !ruby/object:Gem::Version
|
47
|
-
version: '0.
|
47
|
+
version: '0.11'
|
48
48
|
type: :runtime
|
49
49
|
prerelease: false
|
50
50
|
version_requirements: !ruby/object:Gem::Requirement
|
51
51
|
requirements:
|
52
52
|
- - "~>"
|
53
53
|
- !ruby/object:Gem::Version
|
54
|
-
version: '0.
|
54
|
+
version: '0.11'
|
55
55
|
- !ruby/object:Gem::Dependency
|
56
56
|
name: bundler
|
57
57
|
requirement: !ruby/object:Gem::Requirement
|
@@ -69,7 +69,7 @@ dependencies:
|
|
69
69
|
description: |
|
70
70
|
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
|
71
71
|
It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
|
72
|
-
from human readable register map
|
72
|
+
from human readable register map specifications.
|
73
73
|
email:
|
74
74
|
- rggen@googlegroups.com
|
75
75
|
executables: []
|
@@ -100,8 +100,10 @@ files:
|
|
100
100
|
- lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb
|
101
101
|
- lib/rggen/built_in/bit_field/type/rw_wo.erb
|
102
102
|
- lib/rggen/built_in/bit_field/type/rw_wo.rb
|
103
|
-
- lib/rggen/built_in/bit_field/type/
|
104
|
-
- lib/rggen/built_in/bit_field/type/
|
103
|
+
- lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb
|
104
|
+
- lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb
|
105
|
+
- lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb
|
106
|
+
- lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb
|
105
107
|
- lib/rggen/built_in/global/address_width.rb
|
106
108
|
- lib/rggen/built_in/global/array_port_format.rb
|
107
109
|
- lib/rggen/built_in/global/bus_width.rb
|
@@ -1,14 +0,0 @@
|
|
1
|
-
rggen_bit_field_<%= bit_field.type %> #(
|
2
|
-
.WIDTH (<%= bit_field.width %>),
|
3
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
4
|
-
) u_bit_field (
|
5
|
-
.i_clk (<%= register_block.clock %>),
|
6
|
-
.i_rst_n (<%= register_block.reset %>),
|
7
|
-
.bit_field_if (<%= bit_field.bit_field_sub_if %>),
|
8
|
-
<% if bit_field.type == :rwe %>
|
9
|
-
.i_enable (<%= reference_bit_field %>),
|
10
|
-
<% else %>
|
11
|
-
.i_lock (<%= reference_bit_field %>),
|
12
|
-
<% end %>
|
13
|
-
.o_value (<%= value_out[bit_field.loop_variables] %>)
|
14
|
-
);
|
@@ -1,39 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
|
4
|
-
register_map do
|
5
|
-
read_write
|
6
|
-
non_volatile
|
7
|
-
need_initial_value
|
8
|
-
use_reference required: true, width: 1
|
9
|
-
end
|
10
|
-
|
11
|
-
sv_rtl do
|
12
|
-
build do
|
13
|
-
output :register_block, :value_out, {
|
14
|
-
name: "o_#{full_name}",
|
15
|
-
data_type: :logic,
|
16
|
-
width: bit_field.width,
|
17
|
-
array_size: bit_field.array_size,
|
18
|
-
array_format: array_port_format
|
19
|
-
}
|
20
|
-
end
|
21
|
-
|
22
|
-
main_code :bit_field, from_template: true
|
23
|
-
end
|
24
|
-
|
25
|
-
sv_ral do
|
26
|
-
model_name do
|
27
|
-
"rggen_ral_#{bit_field.type}_field #(#{reference_names})"
|
28
|
-
end
|
29
|
-
|
30
|
-
private
|
31
|
-
|
32
|
-
def reference_names
|
33
|
-
reference = bit_field.find_reference(register_block.bit_fields)
|
34
|
-
[reference.register.name, reference.name]
|
35
|
-
.map { |name| string(name) }
|
36
|
-
.join(', ')
|
37
|
-
end
|
38
|
-
end
|
39
|
-
end
|