rggen 0.10.0 → 0.11.0

data/sample/block_0.yml

@@ -26,8 +26,9 @@ register_blocks: [
         name: register_2,
         offset_address: 0x04,
         bit_fields: [
-          { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wo, initial_value: 0 },
-          { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: wo, initial_value: 0 }
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: wo, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: w0trg },
+          { name: bit_field_2, bit_assignment: { lsb: 16, width: 4 }, type: w1trg }
         ]
       },
       {
@@ -44,8 +45,12 @@ register_blocks: [
         name: register_4,
         offset_address: 0x0C,
         bit_fields: [
-          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 8 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
-          { name: bit_field_1, bit_assignment: { lsb: 16, width: 8 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rwc, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rwc, initial_value: 0, reference: register_2.bit_field_1 },
+          { name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: rwe, initial_value: 0 },
+          { name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
+          { name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: rwl, initial_value: 0 },
+          { name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
         ]
       },
       {

data/sample/block_0_ral_pkg.sv

@@ -33,13 +33,15 @@ package block_0_ral_pkg;
   endclass
   class register_2_reg_model extends rggen_ral_reg;
     rand rggen_ral_field bit_field_0;
-    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_w0trg_field bit_field_1;
+    rand rggen_ral_w1trg_field bit_field_2;
     function new(string name);
       super.new(name, 32, 0);
     endfunction
     function void build();
       `rggen_ral_create_field_model(bit_field_0, 0, 4, WO, 0, 4'h0, 1)
-      `rggen_ral_create_field_model(bit_field_1, 8, 4, WO, 0, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 8, 4, W0TRG, 0, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_2, 16, 4, W1TRG, 0, 4'h0, 0)
     endfunction
   endclass
   class register_3_reg_model extends rggen_ral_reg;
@@ -58,14 +60,22 @@ package block_0_ral_pkg;
     endfunction
   endclass
   class register_4_reg_model extends rggen_ral_reg;
-    rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_0;
-    rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_1;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_rwe_field #("", "") bit_field_2;
+    rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_3;
+    rand rggen_ral_rwl_field #("", "") bit_field_4;
+    rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_5;
     function new(string name);
       super.new(name, 32, 0);
     endfunction
     function void build();
-      `rggen_ral_create_field_model(bit_field_0, 0, 8, RWE, 0, 8'h00, 1)
-      `rggen_ral_create_field_model(bit_field_1, 16, 8, RWL, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2, 8, 4, RWE, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_3, 12, 4, RWE, 0, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_4, 16, 4, RWL, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_5, 20, 4, RWL, 0, 4'h0, 1)
     endfunction
   endclass
   class register_5_reg_model extends rggen_ral_reg;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.10.0
+  version: 0.11.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-07-31 00:00:00.000000000 Z
+date: 2019-08-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-core
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.10'
+        version: '0.11'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.10'
+        version: '0.11'
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.10'
+        version: '0.11'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.10'
+        version: '0.11'
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -69,7 +69,7 @@ dependencies:
 description: |
   RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
   It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
-  from human readable register map documents.
+  from human readable register map specifications.
 email:
 - rggen@googlegroups.com
 executables: []
@@ -100,8 +100,10 @@ files:
 - lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb
 - lib/rggen/built_in/bit_field/type/rw_wo.erb
 - lib/rggen/built_in/bit_field/type/rw_wo.rb
-- lib/rggen/built_in/bit_field/type/rwe_rwl.erb
-- lib/rggen/built_in/bit_field/type/rwe_rwl.rb
+- lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb
+- lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb
+- lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb
+- lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/built_in/global/address_width.rb
 - lib/rggen/built_in/global/array_port_format.rb
 - lib/rggen/built_in/global/bus_width.rb

data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb

@@ -1,14 +0,0 @@
-rggen_bit_field_<%= bit_field.type %> #(
-  .WIDTH          (<%= bit_field.width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
-<% if bit_field.type == :rwe %>
-  .i_enable     (<%= reference_bit_field %>),
-<% else %>
-  .i_lock       (<%= reference_bit_field %>),
-<% end %>
-  .o_value      (<%= value_out[bit_field.loop_variables] %>)
-);

data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb

@@ -1,39 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
-  register_map do
-    read_write
-    non_volatile
-    need_initial_value
-    use_reference required: true, width: 1
-  end
-
-  sv_rtl do
-    build do
-      output :register_block, :value_out, {
-        name: "o_#{full_name}",
-        data_type: :logic,
-        width: bit_field.width,
-        array_size: bit_field.array_size,
-        array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-  end
-
-  sv_ral do
-    model_name do
-      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
-    end
-
-    private
-
-    def reference_names
-      reference = bit_field.find_reference(register_block.bit_fields)
-      [reference.register.name, reference.name]
-        .map { |name| string(name) }
-        .join(', ')
-    end
-  end
-end