rggen 0.10.0 → 0.11.0

data/lib/rggen/built_in/register_block/protocol/apb.erb

@@ -1,10 +1,10 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH  (<%= register_block.local_address_width %>),
-  .BUS_WIDTH      (<%= configuration.bus_width %>),
-  .REGISTERS      (<%= register_block.total_registers %>)
+  .ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .REGISTERS      (<%= total_registers %>)
 ) u_adapter (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),
   .apb_if       (<%= apb_if %>),
-  .register_if  (<%= register_block.register_if %>)
+  .register_if  (<%= register_if %>)
 );

data/lib/rggen/built_in/register_block/protocol/apb.rb

@@ -23,67 +23,43 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
     build do
       if configuration.fold_sv_interface_port?
         interface_port :register_block, :apb_if, {
-          name: 'apb_if',
-          interface_type: 'rggen_apb_if',
-          modport: 'slave'
+          name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
         }
       else
         input :register_block, :psel, {
-          name: 'i_psel',
-          data_type: :logic,
-          width: 1
+          name: 'i_psel', data_type: :logic, width: 1
         }
         input :register_block, :penable, {
-          name: 'i_penable',
-          data_type: :logic,
-          width: 1
+          name: 'i_penable', data_type: :logic, width: 1
         }
         input :register_block, :paddr, {
-          name: 'i_paddr',
-          data_type: :logic,
-          width: configuration.address_width
+          name: 'i_paddr', data_type: :logic, width: address_width
         }
         input :register_block, :pprot, {
-          name: 'i_pprot',
-          data_type: :logic,
-          width: 3
+          name: 'i_pprot', data_type: :logic, width: 3
         }
         input :register_block, :pwrite, {
-          name: 'i_pwrite',
-          data_type: :logic,
-          width: 1
+          name: 'i_pwrite', data_type: :logic, width: 1
         }
         input :register_block, :pstrb, {
-          name: 'i_pstrb',
-          data_type: :logic,
-          width: configuration.byte_width
+          name: 'i_pstrb', data_type: :logic,
+          width: byte_width
         }
         input :register_block, :pwdata, {
-          name: 'i_pwdata',
-          data_type: :logic,
-          width: configuration.bus_width
+          name: 'i_pwdata', data_type: :logic, width: bus_width
         }
         output :register_block, :pready, {
-          name: 'o_pready',
-          data_type: :logic,
-          width: 1
+          name: 'o_pready', data_type: :logic, width: 1
         }
         output :register_block, :prdata, {
-          name: 'o_prdata',
-          data_type: :logic,
-          width: configuration.bus_width
+          name: 'o_prdata', data_type: :logic, width: bus_width
         }
         output :register_block, :pslverr, {
-          name: 'o_pslverr',
-          data_type: :logic,
-          width: 1
+          name: 'o_pslverr', data_type: :logic, width: 1
         }
         interface :register_block, :apb_if, {
-          name: 'apb_if',
-          interface_type: 'rggen_apb_if',
-          parameter_values: [
-            configuration.address_width, configuration.bus_width
-          ],
+          name: 'apb_if', interface_type: 'rggen_apb_if',
+          parameter_values: [address_width, bus_width],
           variables: [
             'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
             'pready', 'prdata', 'pslverr'

data/lib/rggen/built_in/register_block/protocol/axi4lite.erb

@@ -1,11 +1,11 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH  (<%= register_block.local_address_width %>),
-  .BUS_WIDTH      (<%= configuration.bus_width %>),
-  .REGISTERS      (<%= register_block.total_registers %>),
+  .ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .REGISTERS      (<%= total_registers %>),
   .WRITE_FIRST    (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),
   .axi4lite_if  (<%= axi4lite_if %>),
-  .register_if  (<%= register_block.register_if %>)
+  .register_if  (<%= register_if %>)
 );

data/lib/rggen/built_in/register_block/protocol/axi4lite.rb

@@ -21,111 +21,69 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
       if configuration.fold_sv_interface_port?
         interface_port :register_block, :axi4lite_if, {
           name: 'axi4lite_if',
-          interface_type: 'rggen_axi4lite_if',
-          modport: 'slave'
+          interface_type: 'rggen_axi4lite_if', modport: 'slave'
         }
       else
         input :register_block, :awvalid, {
-          name: 'i_awvalid',
-          data_type: :logic,
-          width: 1
+          name: 'i_awvalid', data_type: :logic, width: 1
         }
         output :register_block, :awready, {
-          name: 'o_awready',
-          data_type: :logic,
-          width: 1
+          name: 'o_awready', data_type: :logic, width: 1
         }
         input :register_block, :awaddr, {
-          name: 'i_awaddr',
-          data_type: :logic,
-          width: configuration.address_width
+          name: 'i_awaddr', data_type: :logic, width: address_width
         }
         input :register_block, :awprot, {
-          name: 'i_awprot',
-          data_type: :logic,
-          width: 3
+          name: 'i_awprot', data_type: :logic, width: 3
         }
         input :register_block, :wvalid, {
-          name: 'i_wvalid',
-          data_type: :logic,
-          width: 1
+          name: 'i_wvalid', data_type: :logic, width: 1
         }
         output :register_block, :wready, {
-          name: 'o_wready',
-          data_type: :logic,
-          width: 1
+          name: 'o_wready', data_type: :logic, width: 1
         }
         input :register_block, :wdata, {
-          name: 'i_wdata',
-          data_type: :logic,
-          width: configuration.bus_width
+          name: 'i_wdata', data_type: :logic, width: bus_width
         }
         input :register_block, :wstrb, {
-          name: 'i_wstrb',
-          data_type: :logic,
-          width: configuration.byte_width
+          name: 'i_wstrb', data_type: :logic, width: byte_width
         }
         output :register_block, :bvalid, {
-          name: 'o_bvalid',
-          data_type: :logic,
-          width: 1
+          name: 'o_bvalid', data_type: :logic, width: 1
         }
         input :register_block, :bready, {
-          name: 'i_bready',
-          data_type: :logic,
-          width: 1
+          name: 'i_bready', data_type: :logic, width: 1
         }
         output :register_block, :bresp, {
-          name: 'o_bresp',
-          data_type: :logic,
-          width: 2
+          name: 'o_bresp', data_type: :logic, width: 2
         }
         input :register_block, :arvalid, {
-          name: 'i_arvalid',
-          data_type: :logic,
-          width: 1
+          name: 'i_arvalid', data_type: :logic, width: 1
         }
         output :register_block, :arready, {
-          name: 'o_arready',
-          data_type: :logic,
-          width: 1
+          name: 'o_arready', data_type: :logic, width: 1
         }
         input :register_block, :araddr, {
-          name: 'i_araddr',
-          data_type: :logic,
-          width: configuration.address_width
+          name: 'i_araddr', data_type: :logic, width: address_width
         }
         input :register_block, :arprot, {
-          name: 'i_arprot',
-          data_type: :logic,
-          width: 3
+          name: 'i_arprot', data_type: :logic, width: 3
         }
         output :register_block, :rvalid, {
-          name: 'o_rvalid',
-          data_type: :logic,
-          width: 1
+          name: 'o_rvalid', data_type: :logic, width: 1
         }
         input :register_block, :rready, {
-          name: 'i_rready',
-          data_type: :logic,
-          width: 1
+          name: 'i_rready', data_type: :logic, width: 1
         }
         output :register_block, :rdata, {
-          name: 'o_rdata',
-          data_type: :logic,
-          width: configuration.bus_width
+          name: 'o_rdata', data_type: :logic, width: bus_width
         }
         output :register_block, :rresp, {
-          name: 'o_rresp',
-          data_type: :logic,
-          width: 2
+          name: 'o_rresp', data_type: :logic, width: 2
         }
         interface :register_block, :axi4lite_if, {
-          name: 'axi4lite_if',
-          interface_type: 'rggen_axi4lite_if',
-          parameter_values: [
-            configuration.address_width, configuration.bus_width
-          ],
+          name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
+          parameter_values: [address_width, bus_width],
           variables: [
             'awvalid', 'awready', 'awaddr', 'awprot',
             'wvalid', 'wready', 'wdata', 'wstrb',

data/lib/rggen/built_in/register_block/sv_ral_package.rb

@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
     write_file '<%= package_name %>.sv' do |file|
       file.body do
         package_definition(package_name) do |package|
-          package.package_imports [
-            'uvm_pkg', 'rggen_ral_pkg'
-          ]
-          package.include_files [
-            'uvm_macros.svh', 'rggen_ral_macros.svh'
-          ]
+          package.package_imports packages
+          package.include_files include_files
           package.body do |code|
             register_block.generate_code(:ral_package, :bottom_up, code)
           end
@@ -35,6 +31,17 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
       "#{register_block.name}_ral_pkg"
     end
 
+    def packages
+      [
+        'uvm_pkg', 'rggen_ral_pkg',
+        *register_block.package_imports(:ral_package)
+      ]
+    end
+
+    def include_files
+      ['uvm_macros.svh', 'rggen_ral_macros.svh']
+    end
+
     def model_name
       "#{register_block.name}_block_model"
     end

data/lib/rggen/built_in/register_block/sv_rtl_top.rb

@@ -6,18 +6,13 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
 
     build do
       input :register_block, :clock, {
-        name: 'i_clk',
-        data_type: :logic,
-        width: 1
+        name: 'i_clk', data_type: :logic, width: 1
       }
       input :register_block, :reset, {
-        name: 'i_rst_n',
-        data_type: :logic,
-        width: 1
+        name: 'i_rst_n', data_type: :logic, width: 1
       }
       interface :register_block, :register_if, {
-        name: 'register_if',
-        interface_type: 'rggen_register_if',
+        name: 'register_if', interface_type: 'rggen_register_if',
         parameter_values: [address_width, bus_width, value_width],
         array_size: [total_registers],
         variables: ['value']
@@ -60,7 +55,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
 
     def sv_module_definition(code)
       code << module_definition(register_block.name) do |sv_module|
-        sv_module.package_imports [:rggen_rtl_pkg]
+        sv_module.package_imports packages
         sv_module.parameters parameters
         sv_module.ports ports
         sv_module.variables variables
@@ -68,6 +63,10 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
       end
     end
 
+    def packages
+      ['rggen_rtl_pkg', *register_block.package_imports(:register_block)]
+    end
+
     def parameters
       register_block.declarations(:register_block, :parameter)
     end

data/lib/rggen/built_in/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module BuiltIn
-    VERSION = '0.10.0'
+    VERSION = '0.11.0'
   end
 end

data/lib/rggen/setup/default.rb

@@ -1,6 +1,5 @@
 # frozen_string_literal: true
 
-require 'rggen/systemverilog'
 require 'rggen/built_in'
 require 'rggen/spreadsheet_loader'
 
@@ -15,7 +14,9 @@ RgGen.enable :bit_field, [
   :name, :bit_assignment, :type, :initial_value, :reference, :comment
 ]
 RgGen.enable :bit_field, :type, [
-  :rc, :reserved, :ro, :rof, :rs, :rw, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s, :wo
+  :rc, :reserved, :ro, :rof, :rs,
+  :rw, :rwc, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s,
+  :w0trg, :w1trg, :wo
 ]
 
 RgGen.enable :register_block, [:sv_rtl_top, :protocol]

data/sample/block_0.rb

@@ -24,8 +24,9 @@ register_block {
   register {
     name 'register_2'
     offset_address 0x04
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :wo; initial_value 0 }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :wo; initial_value 0 }
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :wo; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :w0trg }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :w1trg }
   }
 
   register {
@@ -40,8 +41,12 @@ register_block {
   register {
     name 'register_4'
     offset_address 0x0C
-    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 8; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
-    bit_field { name 'bit_field_1'; bit_assignment lsb: 16, width: 8; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rwc; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :rwc; initial_value 0; reference 'register_2.bit_field_1' }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 4; type :rwe; initial_value 0 }
+    bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
+    bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :rwl; initial_value 0 }
+    bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
   }
 
   register {

data/sample/block_0.sv

@@ -19,7 +19,8 @@ module block_0
   input logic [3:0] i_register_1_bit_field_0,
   input logic [3:0] i_register_1_bit_field_1,
   output logic [3:0] o_register_2_bit_field_0,
-  output logic [3:0] o_register_2_bit_field_1,
+  output logic [3:0] o_register_2_bit_field_1_trigger,
+  output logic [3:0] o_register_2_bit_field_2_trigger,
   input logic [3:0] i_register_3_bit_field_0_set,
   output logic [3:0] o_register_3_bit_field_0,
   input logic [3:0] i_register_3_bit_field_1_set,
@@ -27,8 +28,15 @@ module block_0
   output logic [3:0] o_register_3_bit_field_1_unmasked,
   input logic [3:0] i_register_3_bit_field_3_clear,
   output logic [3:0] o_register_3_bit_field_3,
-  output logic [7:0] o_register_4_bit_field_0,
-  output logic [7:0] o_register_4_bit_field_1,
+  input logic i_register_4_bit_field_0_clear,
+  output logic [3:0] o_register_4_bit_field_0,
+  output logic [3:0] o_register_4_bit_field_1,
+  input logic i_register_4_bit_field_2_enable,
+  output logic [3:0] o_register_4_bit_field_2,
+  output logic [3:0] o_register_4_bit_field_3,
+  input logic i_register_4_bit_field_4_lock,
+  output logic [3:0] o_register_4_bit_field_4,
+  output logic [3:0] o_register_4_bit_field_5,
   input logic [3:0] i_register_5_bit_field_0_set,
   output logic [3:0] o_register_5_bit_field_0,
   input logic [3:0] i_register_5_bit_field_1_set,
@@ -181,7 +189,7 @@ module block_0
       .OFFSET_ADDRESS (8'h04),
       .BUS_WIDTH      (32),
       .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00000f0f),
+      .VALID_BITS     (32'h000f0f0f),
       .REGISTER_INDEX (0)
     ) u_register (
       .i_clk        (i_clk),
@@ -205,14 +213,27 @@ module block_0
     if (1) begin : g_bit_field_1
       rggen_bit_field_if #(4) bit_field_sub_if();
       `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
-      rggen_bit_field_wo #(
-        .WIDTH          (4),
-        .INITIAL_VALUE  (4'h0)
+      rggen_bit_field_w01trg #(
+        .TRIGGER_VALUE  (1'b0),
+        .WIDTH          (4)
       ) u_bit_field (
         .i_clk        (i_clk),
         .i_rst_n      (i_rst_n),
         .bit_field_if (bit_field_sub_if),
-        .o_value      (o_register_2_bit_field_1)
+        .o_trigger    (o_register_2_bit_field_1_trigger)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
+      rggen_bit_field_w01trg #(
+        .TRIGGER_VALUE  (1'b1),
+        .WIDTH          (4)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_trigger    (o_register_2_bit_field_2_trigger)
       );
     end
   end endgenerate
@@ -299,7 +320,7 @@ module block_0
       .OFFSET_ADDRESS (8'h0c),
       .BUS_WIDTH      (32),
       .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00ff00ff),
+      .VALID_BITS     (32'h00ffffff),
       .REGISTER_INDEX (0)
     ) u_register (
       .i_clk        (i_clk),
@@ -308,31 +329,87 @@ module block_0
       .bit_field_if (bit_field_if)
     );
     if (1) begin : g_bit_field_0
-      rggen_bit_field_if #(8) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8)
-      rggen_bit_field_rwe #(
-        .WIDTH          (8),
-        .INITIAL_VALUE  (8'h00)
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_rwc #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
       ) u_bit_field (
         .i_clk        (i_clk),
         .i_rst_n      (i_rst_n),
         .bit_field_if (bit_field_sub_if),
-        .i_enable     (register_if[0].value[8+:1]),
+        .i_clear      (i_register_4_bit_field_0_clear),
         .o_value      (o_register_4_bit_field_0)
       );
     end
     if (1) begin : g_bit_field_1
-      rggen_bit_field_if #(8) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 8)
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
+      rggen_bit_field_rwc #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_clear      (register_if[2].value[8+:1]),
+        .o_value      (o_register_4_bit_field_1)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
+      rggen_bit_field_rwe #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_enable     (i_register_4_bit_field_2_enable),
+        .o_value      (o_register_4_bit_field_2)
+      );
+    end
+    if (1) begin : g_bit_field_3
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
+      rggen_bit_field_rwe #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_enable     (register_if[0].value[8+:1]),
+        .o_value      (o_register_4_bit_field_3)
+      );
+    end
+    if (1) begin : g_bit_field_4
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
+      rggen_bit_field_rwl #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_lock       (i_register_4_bit_field_4_lock),
+        .o_value      (o_register_4_bit_field_4)
+      );
+    end
+    if (1) begin : g_bit_field_5
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4)
       rggen_bit_field_rwl #(
-        .WIDTH          (8),
-        .INITIAL_VALUE  (8'h00)
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
       ) u_bit_field (
         .i_clk        (i_clk),
         .i_rst_n      (i_rst_n),
         .bit_field_if (bit_field_sub_if),
         .i_lock       (register_if[0].value[8+:1]),
-        .o_value      (o_register_4_bit_field_1)
+        .o_value      (o_register_4_bit_field_5)
       );
     end
   end endgenerate