rggen 0.10.0 → 0.11.0

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Files changed (44) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +3 -3
  3. data/lib/rggen/built_in.rb +3 -2
  4. data/lib/rggen/built_in/bit_field/initial_value.rb +22 -0
  5. data/lib/rggen/built_in/bit_field/reference.rb +40 -1
  6. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +4 -2
  7. data/lib/rggen/built_in/bit_field/type.rb +44 -80
  8. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +4 -4
  9. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +11 -20
  10. data/lib/rggen/built_in/bit_field/type/reserved.erb +1 -1
  11. data/lib/rggen/built_in/bit_field/type/ro.erb +2 -2
  12. data/lib/rggen/built_in/bit_field/type/ro.rb +4 -7
  13. data/lib/rggen/built_in/bit_field/type/rof.erb +2 -2
  14. data/lib/rggen/built_in/bit_field/type/rof.rb +1 -1
  15. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +4 -4
  16. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +6 -12
  17. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +3 -3
  18. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +4 -7
  19. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.erb +16 -0
  20. data/lib/rggen/built_in/bit_field/type/rwc_rwe_rwl.rb +92 -0
  21. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.erb +9 -0
  22. data/lib/rggen/built_in/bit_field/type/w0trg_w1trg.rb +29 -0
  23. data/lib/rggen/built_in/register/type.rb +12 -0
  24. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +3 -3
  25. data/lib/rggen/built_in/register/type/external.rb +9 -22
  26. data/lib/rggen/built_in/register/type/indirect.rb +1 -3
  27. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +3 -3
  28. data/lib/rggen/built_in/register_block/protocol.rb +28 -0
  29. data/lib/rggen/built_in/register_block/protocol/apb.erb +4 -4
  30. data/lib/rggen/built_in/register_block/protocol/apb.rb +14 -38
  31. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +4 -4
  32. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +22 -64
  33. data/lib/rggen/built_in/register_block/sv_ral_package.rb +13 -6
  34. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +8 -9
  35. data/lib/rggen/built_in/version.rb +1 -1
  36. data/lib/rggen/setup/default.rb +3 -2
  37. data/sample/block_0.rb +9 -4
  38. data/sample/block_0.sv +97 -20
  39. data/sample/block_0.xlsx +0 -0
  40. data/sample/block_0.yml +9 -4
  41. data/sample/block_0_ral_pkg.sv +16 -6
  42. metadata +11 -9
  43. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +0 -14
  44. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +0 -39
@@ -1,10 +1,10 @@
1
1
  rggen_apb_adapter #(
2
- .ADDRESS_WIDTH (<%= register_block.local_address_width %>),
3
- .BUS_WIDTH (<%= configuration.bus_width %>),
4
- .REGISTERS (<%= register_block.total_registers %>)
2
+ .ADDRESS_WIDTH (<%= local_address_width %>),
3
+ .BUS_WIDTH (<%= bus_width %>),
4
+ .REGISTERS (<%= total_registers %>)
5
5
  ) u_adapter (
6
6
  .i_clk (<%= register_block.clock %>),
7
7
  .i_rst_n (<%= register_block.reset %>),
8
8
  .apb_if (<%= apb_if %>),
9
- .register_if (<%= register_block.register_if %>)
9
+ .register_if (<%= register_if %>)
10
10
  );
@@ -23,67 +23,43 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
23
23
  build do
24
24
  if configuration.fold_sv_interface_port?
25
25
  interface_port :register_block, :apb_if, {
26
- name: 'apb_if',
27
- interface_type: 'rggen_apb_if',
28
- modport: 'slave'
26
+ name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
29
27
  }
30
28
  else
31
29
  input :register_block, :psel, {
32
- name: 'i_psel',
33
- data_type: :logic,
34
- width: 1
30
+ name: 'i_psel', data_type: :logic, width: 1
35
31
  }
36
32
  input :register_block, :penable, {
37
- name: 'i_penable',
38
- data_type: :logic,
39
- width: 1
33
+ name: 'i_penable', data_type: :logic, width: 1
40
34
  }
41
35
  input :register_block, :paddr, {
42
- name: 'i_paddr',
43
- data_type: :logic,
44
- width: configuration.address_width
36
+ name: 'i_paddr', data_type: :logic, width: address_width
45
37
  }
46
38
  input :register_block, :pprot, {
47
- name: 'i_pprot',
48
- data_type: :logic,
49
- width: 3
39
+ name: 'i_pprot', data_type: :logic, width: 3
50
40
  }
51
41
  input :register_block, :pwrite, {
52
- name: 'i_pwrite',
53
- data_type: :logic,
54
- width: 1
42
+ name: 'i_pwrite', data_type: :logic, width: 1
55
43
  }
56
44
  input :register_block, :pstrb, {
57
- name: 'i_pstrb',
58
- data_type: :logic,
59
- width: configuration.byte_width
45
+ name: 'i_pstrb', data_type: :logic,
46
+ width: byte_width
60
47
  }
61
48
  input :register_block, :pwdata, {
62
- name: 'i_pwdata',
63
- data_type: :logic,
64
- width: configuration.bus_width
49
+ name: 'i_pwdata', data_type: :logic, width: bus_width
65
50
  }
66
51
  output :register_block, :pready, {
67
- name: 'o_pready',
68
- data_type: :logic,
69
- width: 1
52
+ name: 'o_pready', data_type: :logic, width: 1
70
53
  }
71
54
  output :register_block, :prdata, {
72
- name: 'o_prdata',
73
- data_type: :logic,
74
- width: configuration.bus_width
55
+ name: 'o_prdata', data_type: :logic, width: bus_width
75
56
  }
76
57
  output :register_block, :pslverr, {
77
- name: 'o_pslverr',
78
- data_type: :logic,
79
- width: 1
58
+ name: 'o_pslverr', data_type: :logic, width: 1
80
59
  }
81
60
  interface :register_block, :apb_if, {
82
- name: 'apb_if',
83
- interface_type: 'rggen_apb_if',
84
- parameter_values: [
85
- configuration.address_width, configuration.bus_width
86
- ],
61
+ name: 'apb_if', interface_type: 'rggen_apb_if',
62
+ parameter_values: [address_width, bus_width],
87
63
  variables: [
88
64
  'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
89
65
  'pready', 'prdata', 'pslverr'
@@ -1,11 +1,11 @@
1
1
  rggen_axi4lite_adapter #(
2
- .ADDRESS_WIDTH (<%= register_block.local_address_width %>),
3
- .BUS_WIDTH (<%= configuration.bus_width %>),
4
- .REGISTERS (<%= register_block.total_registers %>),
2
+ .ADDRESS_WIDTH (<%= local_address_width %>),
3
+ .BUS_WIDTH (<%= bus_width %>),
4
+ .REGISTERS (<%= total_registers %>),
5
5
  .WRITE_FIRST (<%= write_first %>)
6
6
  ) u_adapter (
7
7
  .i_clk (<%= register_block.clock %>),
8
8
  .i_rst_n (<%= register_block.reset %>),
9
9
  .axi4lite_if (<%= axi4lite_if %>),
10
- .register_if (<%= register_block.register_if %>)
10
+ .register_if (<%= register_if %>)
11
11
  );
@@ -21,111 +21,69 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
21
21
  if configuration.fold_sv_interface_port?
22
22
  interface_port :register_block, :axi4lite_if, {
23
23
  name: 'axi4lite_if',
24
- interface_type: 'rggen_axi4lite_if',
25
- modport: 'slave'
24
+ interface_type: 'rggen_axi4lite_if', modport: 'slave'
26
25
  }
27
26
  else
28
27
  input :register_block, :awvalid, {
29
- name: 'i_awvalid',
30
- data_type: :logic,
31
- width: 1
28
+ name: 'i_awvalid', data_type: :logic, width: 1
32
29
  }
33
30
  output :register_block, :awready, {
34
- name: 'o_awready',
35
- data_type: :logic,
36
- width: 1
31
+ name: 'o_awready', data_type: :logic, width: 1
37
32
  }
38
33
  input :register_block, :awaddr, {
39
- name: 'i_awaddr',
40
- data_type: :logic,
41
- width: configuration.address_width
34
+ name: 'i_awaddr', data_type: :logic, width: address_width
42
35
  }
43
36
  input :register_block, :awprot, {
44
- name: 'i_awprot',
45
- data_type: :logic,
46
- width: 3
37
+ name: 'i_awprot', data_type: :logic, width: 3
47
38
  }
48
39
  input :register_block, :wvalid, {
49
- name: 'i_wvalid',
50
- data_type: :logic,
51
- width: 1
40
+ name: 'i_wvalid', data_type: :logic, width: 1
52
41
  }
53
42
  output :register_block, :wready, {
54
- name: 'o_wready',
55
- data_type: :logic,
56
- width: 1
43
+ name: 'o_wready', data_type: :logic, width: 1
57
44
  }
58
45
  input :register_block, :wdata, {
59
- name: 'i_wdata',
60
- data_type: :logic,
61
- width: configuration.bus_width
46
+ name: 'i_wdata', data_type: :logic, width: bus_width
62
47
  }
63
48
  input :register_block, :wstrb, {
64
- name: 'i_wstrb',
65
- data_type: :logic,
66
- width: configuration.byte_width
49
+ name: 'i_wstrb', data_type: :logic, width: byte_width
67
50
  }
68
51
  output :register_block, :bvalid, {
69
- name: 'o_bvalid',
70
- data_type: :logic,
71
- width: 1
52
+ name: 'o_bvalid', data_type: :logic, width: 1
72
53
  }
73
54
  input :register_block, :bready, {
74
- name: 'i_bready',
75
- data_type: :logic,
76
- width: 1
55
+ name: 'i_bready', data_type: :logic, width: 1
77
56
  }
78
57
  output :register_block, :bresp, {
79
- name: 'o_bresp',
80
- data_type: :logic,
81
- width: 2
58
+ name: 'o_bresp', data_type: :logic, width: 2
82
59
  }
83
60
  input :register_block, :arvalid, {
84
- name: 'i_arvalid',
85
- data_type: :logic,
86
- width: 1
61
+ name: 'i_arvalid', data_type: :logic, width: 1
87
62
  }
88
63
  output :register_block, :arready, {
89
- name: 'o_arready',
90
- data_type: :logic,
91
- width: 1
64
+ name: 'o_arready', data_type: :logic, width: 1
92
65
  }
93
66
  input :register_block, :araddr, {
94
- name: 'i_araddr',
95
- data_type: :logic,
96
- width: configuration.address_width
67
+ name: 'i_araddr', data_type: :logic, width: address_width
97
68
  }
98
69
  input :register_block, :arprot, {
99
- name: 'i_arprot',
100
- data_type: :logic,
101
- width: 3
70
+ name: 'i_arprot', data_type: :logic, width: 3
102
71
  }
103
72
  output :register_block, :rvalid, {
104
- name: 'o_rvalid',
105
- data_type: :logic,
106
- width: 1
73
+ name: 'o_rvalid', data_type: :logic, width: 1
107
74
  }
108
75
  input :register_block, :rready, {
109
- name: 'i_rready',
110
- data_type: :logic,
111
- width: 1
76
+ name: 'i_rready', data_type: :logic, width: 1
112
77
  }
113
78
  output :register_block, :rdata, {
114
- name: 'o_rdata',
115
- data_type: :logic,
116
- width: configuration.bus_width
79
+ name: 'o_rdata', data_type: :logic, width: bus_width
117
80
  }
118
81
  output :register_block, :rresp, {
119
- name: 'o_rresp',
120
- data_type: :logic,
121
- width: 2
82
+ name: 'o_rresp', data_type: :logic, width: 2
122
83
  }
123
84
  interface :register_block, :axi4lite_if, {
124
- name: 'axi4lite_if',
125
- interface_type: 'rggen_axi4lite_if',
126
- parameter_values: [
127
- configuration.address_width, configuration.bus_width
128
- ],
85
+ name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
86
+ parameter_values: [address_width, bus_width],
129
87
  variables: [
130
88
  'awvalid', 'awready', 'awaddr', 'awprot',
131
89
  'wvalid', 'wready', 'wdata', 'wstrb',
@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
5
5
  write_file '<%= package_name %>.sv' do |file|
6
6
  file.body do
7
7
  package_definition(package_name) do |package|
8
- package.package_imports [
9
- 'uvm_pkg', 'rggen_ral_pkg'
10
- ]
11
- package.include_files [
12
- 'uvm_macros.svh', 'rggen_ral_macros.svh'
13
- ]
8
+ package.package_imports packages
9
+ package.include_files include_files
14
10
  package.body do |code|
15
11
  register_block.generate_code(:ral_package, :bottom_up, code)
16
12
  end
@@ -35,6 +31,17 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
35
31
  "#{register_block.name}_ral_pkg"
36
32
  end
37
33
 
34
+ def packages
35
+ [
36
+ 'uvm_pkg', 'rggen_ral_pkg',
37
+ *register_block.package_imports(:ral_package)
38
+ ]
39
+ end
40
+
41
+ def include_files
42
+ ['uvm_macros.svh', 'rggen_ral_macros.svh']
43
+ end
44
+
38
45
  def model_name
39
46
  "#{register_block.name}_block_model"
40
47
  end
@@ -6,18 +6,13 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
6
6
 
7
7
  build do
8
8
  input :register_block, :clock, {
9
- name: 'i_clk',
10
- data_type: :logic,
11
- width: 1
9
+ name: 'i_clk', data_type: :logic, width: 1
12
10
  }
13
11
  input :register_block, :reset, {
14
- name: 'i_rst_n',
15
- data_type: :logic,
16
- width: 1
12
+ name: 'i_rst_n', data_type: :logic, width: 1
17
13
  }
18
14
  interface :register_block, :register_if, {
19
- name: 'register_if',
20
- interface_type: 'rggen_register_if',
15
+ name: 'register_if', interface_type: 'rggen_register_if',
21
16
  parameter_values: [address_width, bus_width, value_width],
22
17
  array_size: [total_registers],
23
18
  variables: ['value']
@@ -60,7 +55,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
60
55
 
61
56
  def sv_module_definition(code)
62
57
  code << module_definition(register_block.name) do |sv_module|
63
- sv_module.package_imports [:rggen_rtl_pkg]
58
+ sv_module.package_imports packages
64
59
  sv_module.parameters parameters
65
60
  sv_module.ports ports
66
61
  sv_module.variables variables
@@ -68,6 +63,10 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
68
63
  end
69
64
  end
70
65
 
66
+ def packages
67
+ ['rggen_rtl_pkg', *register_block.package_imports(:register_block)]
68
+ end
69
+
71
70
  def parameters
72
71
  register_block.declarations(:register_block, :parameter)
73
72
  end
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module BuiltIn
5
- VERSION = '0.10.0'
5
+ VERSION = '0.11.0'
6
6
  end
7
7
  end
@@ -1,6 +1,5 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- require 'rggen/systemverilog'
4
3
  require 'rggen/built_in'
5
4
  require 'rggen/spreadsheet_loader'
6
5
 
@@ -15,7 +14,9 @@ RgGen.enable :bit_field, [
15
14
  :name, :bit_assignment, :type, :initial_value, :reference, :comment
16
15
  ]
17
16
  RgGen.enable :bit_field, :type, [
18
- :rc, :reserved, :ro, :rof, :rs, :rw, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s, :wo
17
+ :rc, :reserved, :ro, :rof, :rs,
18
+ :rw, :rwc, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s,
19
+ :w0trg, :w1trg, :wo
19
20
  ]
20
21
 
21
22
  RgGen.enable :register_block, [:sv_rtl_top, :protocol]
@@ -24,8 +24,9 @@ register_block {
24
24
  register {
25
25
  name 'register_2'
26
26
  offset_address 0x04
27
- bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :wo; initial_value 0 }
28
- bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :wo; initial_value 0 }
27
+ bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :wo; initial_value 0 }
28
+ bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :w0trg }
29
+ bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 4; type :w1trg }
29
30
  }
30
31
 
31
32
  register {
@@ -40,8 +41,12 @@ register_block {
40
41
  register {
41
42
  name 'register_4'
42
43
  offset_address 0x0C
43
- bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 8; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
44
- bit_field { name 'bit_field_1'; bit_assignment lsb: 16, width: 8; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
44
+ bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rwc; initial_value 0 }
45
+ bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :rwc; initial_value 0; reference 'register_2.bit_field_1' }
46
+ bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 4; type :rwe; initial_value 0 }
47
+ bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
48
+ bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :rwl; initial_value 0 }
49
+ bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
45
50
  }
46
51
 
47
52
  register {
@@ -19,7 +19,8 @@ module block_0
19
19
  input logic [3:0] i_register_1_bit_field_0,
20
20
  input logic [3:0] i_register_1_bit_field_1,
21
21
  output logic [3:0] o_register_2_bit_field_0,
22
- output logic [3:0] o_register_2_bit_field_1,
22
+ output logic [3:0] o_register_2_bit_field_1_trigger,
23
+ output logic [3:0] o_register_2_bit_field_2_trigger,
23
24
  input logic [3:0] i_register_3_bit_field_0_set,
24
25
  output logic [3:0] o_register_3_bit_field_0,
25
26
  input logic [3:0] i_register_3_bit_field_1_set,
@@ -27,8 +28,15 @@ module block_0
27
28
  output logic [3:0] o_register_3_bit_field_1_unmasked,
28
29
  input logic [3:0] i_register_3_bit_field_3_clear,
29
30
  output logic [3:0] o_register_3_bit_field_3,
30
- output logic [7:0] o_register_4_bit_field_0,
31
- output logic [7:0] o_register_4_bit_field_1,
31
+ input logic i_register_4_bit_field_0_clear,
32
+ output logic [3:0] o_register_4_bit_field_0,
33
+ output logic [3:0] o_register_4_bit_field_1,
34
+ input logic i_register_4_bit_field_2_enable,
35
+ output logic [3:0] o_register_4_bit_field_2,
36
+ output logic [3:0] o_register_4_bit_field_3,
37
+ input logic i_register_4_bit_field_4_lock,
38
+ output logic [3:0] o_register_4_bit_field_4,
39
+ output logic [3:0] o_register_4_bit_field_5,
32
40
  input logic [3:0] i_register_5_bit_field_0_set,
33
41
  output logic [3:0] o_register_5_bit_field_0,
34
42
  input logic [3:0] i_register_5_bit_field_1_set,
@@ -181,7 +189,7 @@ module block_0
181
189
  .OFFSET_ADDRESS (8'h04),
182
190
  .BUS_WIDTH (32),
183
191
  .DATA_WIDTH (32),
184
- .VALID_BITS (32'h00000f0f),
192
+ .VALID_BITS (32'h000f0f0f),
185
193
  .REGISTER_INDEX (0)
186
194
  ) u_register (
187
195
  .i_clk (i_clk),
@@ -205,14 +213,27 @@ module block_0
205
213
  if (1) begin : g_bit_field_1
206
214
  rggen_bit_field_if #(4) bit_field_sub_if();
207
215
  `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
208
- rggen_bit_field_wo #(
209
- .WIDTH (4),
210
- .INITIAL_VALUE (4'h0)
216
+ rggen_bit_field_w01trg #(
217
+ .TRIGGER_VALUE (1'b0),
218
+ .WIDTH (4)
211
219
  ) u_bit_field (
212
220
  .i_clk (i_clk),
213
221
  .i_rst_n (i_rst_n),
214
222
  .bit_field_if (bit_field_sub_if),
215
- .o_value (o_register_2_bit_field_1)
223
+ .o_trigger (o_register_2_bit_field_1_trigger)
224
+ );
225
+ end
226
+ if (1) begin : g_bit_field_2
227
+ rggen_bit_field_if #(4) bit_field_sub_if();
228
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
229
+ rggen_bit_field_w01trg #(
230
+ .TRIGGER_VALUE (1'b1),
231
+ .WIDTH (4)
232
+ ) u_bit_field (
233
+ .i_clk (i_clk),
234
+ .i_rst_n (i_rst_n),
235
+ .bit_field_if (bit_field_sub_if),
236
+ .o_trigger (o_register_2_bit_field_2_trigger)
216
237
  );
217
238
  end
218
239
  end endgenerate
@@ -299,7 +320,7 @@ module block_0
299
320
  .OFFSET_ADDRESS (8'h0c),
300
321
  .BUS_WIDTH (32),
301
322
  .DATA_WIDTH (32),
302
- .VALID_BITS (32'h00ff00ff),
323
+ .VALID_BITS (32'h00ffffff),
303
324
  .REGISTER_INDEX (0)
304
325
  ) u_register (
305
326
  .i_clk (i_clk),
@@ -308,31 +329,87 @@ module block_0
308
329
  .bit_field_if (bit_field_if)
309
330
  );
310
331
  if (1) begin : g_bit_field_0
311
- rggen_bit_field_if #(8) bit_field_sub_if();
312
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8)
313
- rggen_bit_field_rwe #(
314
- .WIDTH (8),
315
- .INITIAL_VALUE (8'h00)
332
+ rggen_bit_field_if #(4) bit_field_sub_if();
333
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
334
+ rggen_bit_field_rwc #(
335
+ .WIDTH (4),
336
+ .INITIAL_VALUE (4'h0)
316
337
  ) u_bit_field (
317
338
  .i_clk (i_clk),
318
339
  .i_rst_n (i_rst_n),
319
340
  .bit_field_if (bit_field_sub_if),
320
- .i_enable (register_if[0].value[8+:1]),
341
+ .i_clear (i_register_4_bit_field_0_clear),
321
342
  .o_value (o_register_4_bit_field_0)
322
343
  );
323
344
  end
324
345
  if (1) begin : g_bit_field_1
325
- rggen_bit_field_if #(8) bit_field_sub_if();
326
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 8)
346
+ rggen_bit_field_if #(4) bit_field_sub_if();
347
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
348
+ rggen_bit_field_rwc #(
349
+ .WIDTH (4),
350
+ .INITIAL_VALUE (4'h0)
351
+ ) u_bit_field (
352
+ .i_clk (i_clk),
353
+ .i_rst_n (i_rst_n),
354
+ .bit_field_if (bit_field_sub_if),
355
+ .i_clear (register_if[2].value[8+:1]),
356
+ .o_value (o_register_4_bit_field_1)
357
+ );
358
+ end
359
+ if (1) begin : g_bit_field_2
360
+ rggen_bit_field_if #(4) bit_field_sub_if();
361
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
362
+ rggen_bit_field_rwe #(
363
+ .WIDTH (4),
364
+ .INITIAL_VALUE (4'h0)
365
+ ) u_bit_field (
366
+ .i_clk (i_clk),
367
+ .i_rst_n (i_rst_n),
368
+ .bit_field_if (bit_field_sub_if),
369
+ .i_enable (i_register_4_bit_field_2_enable),
370
+ .o_value (o_register_4_bit_field_2)
371
+ );
372
+ end
373
+ if (1) begin : g_bit_field_3
374
+ rggen_bit_field_if #(4) bit_field_sub_if();
375
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
376
+ rggen_bit_field_rwe #(
377
+ .WIDTH (4),
378
+ .INITIAL_VALUE (4'h0)
379
+ ) u_bit_field (
380
+ .i_clk (i_clk),
381
+ .i_rst_n (i_rst_n),
382
+ .bit_field_if (bit_field_sub_if),
383
+ .i_enable (register_if[0].value[8+:1]),
384
+ .o_value (o_register_4_bit_field_3)
385
+ );
386
+ end
387
+ if (1) begin : g_bit_field_4
388
+ rggen_bit_field_if #(4) bit_field_sub_if();
389
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
390
+ rggen_bit_field_rwl #(
391
+ .WIDTH (4),
392
+ .INITIAL_VALUE (4'h0)
393
+ ) u_bit_field (
394
+ .i_clk (i_clk),
395
+ .i_rst_n (i_rst_n),
396
+ .bit_field_if (bit_field_sub_if),
397
+ .i_lock (i_register_4_bit_field_4_lock),
398
+ .o_value (o_register_4_bit_field_4)
399
+ );
400
+ end
401
+ if (1) begin : g_bit_field_5
402
+ rggen_bit_field_if #(4) bit_field_sub_if();
403
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4)
327
404
  rggen_bit_field_rwl #(
328
- .WIDTH (8),
329
- .INITIAL_VALUE (8'h00)
405
+ .WIDTH (4),
406
+ .INITIAL_VALUE (4'h0)
330
407
  ) u_bit_field (
331
408
  .i_clk (i_clk),
332
409
  .i_rst_n (i_rst_n),
333
410
  .bit_field_if (bit_field_sub_if),
334
411
  .i_lock (register_if[0].value[8+:1]),
335
- .o_value (o_register_4_bit_field_1)
412
+ .o_value (o_register_4_bit_field_5)
336
413
  );
337
414
  end
338
415
  end endgenerate