rggen 0.3.3 → 0.4.0

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
-  MINOR   = 3
-  TEENY   = 3
+  MINOR   = 4
+  TEENY   = 0
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/rggen_ral_block.svh

@@ -18,8 +18,7 @@ class rggen_ral_block extends uvm_reg_block;
 
   extern protected virtual function void set_cfg(uvm_object cfg);
   extern protected virtual function uvm_reg_map create_default_map();
-  extern protected virtual function void create_blocks();
-  extern protected virtual function void create_registers();
+  extern protected virtual function void create_sub_models();
 endclass
 
 function rggen_ral_block::new(string name, int has_coverage);
@@ -32,8 +31,7 @@ function void rggen_ral_block::configure(uvm_object cfg, uvm_reg_block parent, s
   if (default_map == null) begin
     default_map = create_default_map();
   end
-  create_blocks();
-  create_registers();
+  create_sub_models();
 endfunction
 
 function uvm_reg_map rggen_ral_block::create_map(
@@ -76,9 +74,6 @@ endfunction
 function uvm_reg_map rggen_ral_block::create_default_map();
 endfunction
 
-function void rggen_ral_block::create_blocks();
-endfunction
-
-function void rggen_ral_block::create_registers();
+function void rggen_ral_block::create_sub_models();
 endfunction
 `endif

data/ral/rggen_ral_macros.svh

@@ -7,9 +7,9 @@ begin \
   handle.configure(this.cfg, this, width, lsb, access, volatile, reset, has_reset, 1, 1); \
 end
 
-`define rggen_ral_create_reg_model(handle, base_naem, array_index, offset_address, rights, unmapped) \
+`define rggen_ral_create_reg_model(handle, base_name, array_index, offset_address, rights, unmapped) \
 begin \
-  string  __instance_name   = base_naem; \
+  string  __instance_name   = base_name; \
   int     __array_index[$]  = array_index; \
   foreach (__array_index[__i]) begin \
     $sformat(__instance_name, "%s[%0d]", __instance_name, __array_index[__i]); \
@@ -19,4 +19,11 @@ begin \
   default_map.add_reg(handle, offset_address, rights, unmapped); \
 end
 
+`define rggen_ral_create_block_model(handle, name, offset_address) \
+begin \
+  handle  = new(name); \
+  handle.configure(this.cfg, this, ""); \
+  default_map.add_submap(handle.default_map, offset_address); \
+end
+
 `endif

data/rtl/register/rggen_bus_exporter.sv

@@ -0,0 +1,96 @@
+module rggen_bus_exporter #(
+  parameter DATA_WIDTH              = 32,
+  parameter LOCAL_ADDRESS_WIDTH     = 16,
+  parameter EXTERNAL_ADDRESS_WIDTH  = 8,
+  parameter START_ADDRESS           = 16'h0000
+)(
+  input                                 clk,
+  input                                 rst_n,
+  input                                 i_valid,
+  input                                 i_select,
+  input                                 i_write,
+  input                                 i_read,
+  input   [LOCAL_ADDRESS_WIDTH-1:0]     i_address,
+  input   [DATA_WIDTH/8-1:0]            i_strobe,
+  input   [DATA_WIDTH-1:0]              i_write_data,
+  output                                o_ready,
+  output  [DATA_WIDTH-1:0]              o_read_data,
+  output  [1:0]                         o_status,
+  output                                o_valid,
+  output                                o_write,
+  output                                o_read,
+  output  [EXTERNAL_ADDRESS_WIDTH-1:0]  o_address,
+  output  [DATA_WIDTH/8-1:0]            o_strobe,
+  output  [DATA_WIDTH-1:0]              o_write_data,
+  input                                 i_ready,
+  input   [DATA_WIDTH-1:0]              i_read_data,
+  input   [1:0]                         i_status
+);
+  logic                               access_done;
+  logic                               valid;
+  logic                               write;
+  logic                               read;
+  logic [EXTERNAL_ADDRESS_WIDTH-1:0]  address;
+  logic [DATA_WIDTH/8-1:0]            strobe;
+  logic [DATA_WIDTH-1:0]              write_data;
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      access_done <= 1'b0;
+    end
+    else if (valid && i_ready) begin
+      access_done <= 1'b1;
+    end
+    else begin
+      access_done <= 1'b0;
+    end
+  end
+
+  //  Internal -> External
+  assign  o_valid       = valid;
+  assign  o_write       = write;
+  assign  o_read        = read;
+  assign  o_address     = address;
+  assign  o_strobe      = strobe;
+  assign  o_write_data  = write_data;
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      valid       <= 1'b0;
+      write       <= 1'b0;
+      read        <= 1'b0;
+      address     <= '0;
+      strobe      <= '0;
+      write_data  <= '0;
+    end
+    else if (valid && i_ready) begin
+      valid       <= 1'b0;
+      write       <= 1'b0;
+      read        <= 1'b0;
+      address     <= '0;
+      strobe      <= '0;
+      write_data  <= '0;
+    end
+    else if (i_valid && i_select && (!valid) && (!access_done)) begin
+      valid       <= 1'b1;
+      write       <= i_write;
+      read        <= i_read;
+      address     <= calc_address(i_address);
+      strobe      <= i_strobe;
+      write_data  <= i_write_data;
+    end
+  end
+
+  function automatic logic [EXTERNAL_ADDRESS_WIDTH-1:0] calc_address(
+    input [LOCAL_ADDRESS_WIDTH-1:0] address
+  );
+    logic [LOCAL_ADDRESS_WIDTH-1:0] external_address;
+    external_address  = address - START_ADDRESS;
+    return external_address[EXTERNAL_ADDRESS_WIDTH-1:0];
+  endfunction
+
+  //  External -> Internal
+  assign  o_ready     = i_ready;
+  assign  o_read_data = i_read_data;
+  assign  o_status    = i_status;
+endmodule

data/rtl/register_block/rggen_host_if_apb.sv

@@ -19,6 +19,7 @@ module rggen_host_if_apb #(
   output                            o_write,
   output                            o_read,
   output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
+  output  [DATA_WIDTH/8-1:0]        o_strobe,
   output  [DATA_WIDTH-1:0]          o_write_data,
   output  [DATA_WIDTH-1:0]          o_write_mask,
   input                             i_response_ready,
@@ -35,6 +36,7 @@ module rggen_host_if_apb #(
   assign  o_write         = i_pwrite;
   assign  o_read          = ~i_pwrite;
   assign  o_address       = i_paddr[LOCAL_ADDRESS_WIDTH-1:0];
+  assign  o_strobe        = i_pstrb;
   assign  o_write_data    = i_pwdata;
   assign  o_write_mask    = get_write_mask(i_pstrb);
 endmodule

data/rtl/register_block/rggen_host_if_axi4lite.sv

@@ -29,6 +29,7 @@ module rggen_host_if_axi4lite #(
   output                            o_write,
   output                            o_read,
   output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
+  output  [DATA_WIDTH/8-1:0]        o_strobe,
   output  [DATA_WIDTH-1:0]          o_write_data,
   output  [DATA_WIDTH-1:0]          o_write_mask,
   input                             i_response_ready,
@@ -78,6 +79,7 @@ module rggen_host_if_axi4lite #(
   logic                           command_valid;
   logic                           local_done;
   logic [LOCAL_ADDRESS_WIDTH-1:0] address;
+  logic [DATA_WIDTH/8-1:0]        strobe;
   logic [DATA_WIDTH-1:0]          write_data;
   logic [DATA_WIDTH-1:0]          write_mask;
 
@@ -199,9 +201,10 @@ module rggen_host_if_axi4lite #(
 // Local bus
 //--------------------------------------------------------------
   assign  o_command_valid = command_valid;
-  assign  o_address       = address;
   assign  o_write         = state[2];
   assign  o_read          = state[4];
+  assign  o_address       = address;
+  assign  o_strobe        = strobe;
   assign  o_write_data    = write_data;
   assign  o_write_mask    = write_mask;
 
@@ -236,14 +239,17 @@ module rggen_host_if_axi4lite #(
 
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
+      strobe      <= '0;
       write_data  <= '0;
       write_mask  <= '0;
     end
     else if (wack) begin
+      strobe      <= i_wstrb;
       write_data  <= i_wdata;
       write_mask  <= get_write_mask(i_wstrb);
     end
     else if (local_done) begin
+      strobe      <= '0;
       write_data  <= '0;
       write_mask  <= '0;
     end

data/rtl/register_block/rggen_response_mux.sv

@@ -1,23 +1,34 @@
 module rggen_response_mux #(
-  parameter DATA_WIDTH      = 32,
-  parameter TOTAL_REGISTERS = 1
+  parameter DATA_WIDTH                = 32,
+  parameter TOTAL_REGISTERS           = 1,
+  parameter TOTAL_EXTERNAL_REGISTERS  = 0,
+  parameter EXTERNAL_REGISTERS        = TOTAL_EXTERNAL_REGISTERS
+                                      + ((TOTAL_EXTERNAL_REGISTERS == 0) ? 1 : 0)
 )(
-  input                         clk,
-  input                         rst_n,
-  input                         i_command_valid,
-  input                         i_read,
-  output                        o_response_ready,
-  output  [DATA_WIDTH-1:0]      o_read_data,
-  output  [1:0]                 o_status,
-  input   [TOTAL_REGISTERS-1:0] i_register_select,
-  input   [DATA_WIDTH-1:0]      i_register_read_data[TOTAL_REGISTERS]
+  input                             clk,
+  input                             rst_n,
+  input                             i_command_valid,
+  input                             i_read,
+  output                            o_response_ready,
+  output  [DATA_WIDTH-1:0]          o_read_data,
+  output  [1:0]                     o_status,
+  input   [TOTAL_REGISTERS-1:0]     i_register_select,
+  input   [DATA_WIDTH-1:0]          i_register_read_data[TOTAL_REGISTERS],
+  input   [EXTERNAL_REGISTERS-1:0]  i_external_register_select,
+  input   [EXTERNAL_REGISTERS-1:0]  i_external_register_ready,
+  input   [1:0]                     i_external_register_status[EXTERNAL_REGISTERS]
 );
   //  Response ready
+  logic internal_ready;
+  logic external_ready;
   logic response_valid;
   logic response_ready;
 
+  assign  internal_ready  = (TOTAL_EXTERNAL_REGISTERS > 0) ? ~|i_external_register_select : 1'b1;
+  assign  external_ready  = (TOTAL_EXTERNAL_REGISTERS > 0) ?  |i_external_register_ready  : 1'b0;
+  assign  response_valid  = i_command_valid & (internal_ready | external_ready) & (~response_ready);
+
   assign  o_response_ready  = response_ready;
-  assign  response_valid    = (i_command_valid && (!response_ready)) ? 1'b1 : 1'b0;
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       response_ready  <= 1'b0;
@@ -31,28 +42,50 @@ module rggen_response_mux #(
   end
 
   //  Status
-  logic       slave_error;
-  logic       exokay;
   logic [1:0] status;
 
   assign  o_status      = status;
-  assign  slave_error   = (TOTAL_REGISTERS == 1) ? ~i_register_select[0] : ~|i_register_select;
-  assign  exokay        = 1'b0;
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       status  <= 2'b00;
     end
     else if (response_valid) begin
-      status  <= {exokay, slave_error};
+      status  <= get_internal_response(i_register_select)
+               | get_external_response(i_external_register_select, i_external_register_status);
     end
     else begin
       status  <= 2'b00;
     end
   end
 
+  function automatic logic [1:0] get_internal_response(
+    input [TOTAL_REGISTERS-1:0] register_select
+  );
+    logic slave_error;
+    logic exokay;
+    slave_error = ~|register_select;
+    exokay      = 1'b0;
+    return {exokay, slave_error};
+  endfunction
+
+  function automatic logic [1:0] get_external_response(
+    input [EXTERNAL_REGISTERS-1:0]  external_register_select,
+    input [1:0]                     external_register_status[EXTERNAL_REGISTERS]
+  );
+    if (TOTAL_EXTERNAL_REGISTERS > 0) begin
+      logic [1:0] masked_status[TOTAL_EXTERNAL_REGISTERS];
+      for (int i = 0;i < TOTAL_EXTERNAL_REGISTERS;i++) begin
+        masked_status[i]  = {2{external_register_select[i]}} & external_register_status[i];
+      end
+      return masked_status.or();
+    end
+    else begin
+      return 2'b00;
+    end
+  endfunction
+
   //  Read data
   logic [DATA_WIDTH-1:0]  read_data;
-  logic [DATA_WIDTH-1:0]  selected_data;
 
   assign  o_read_data = read_data;
   always_ff @(posedge clk or negedge rst_n) begin
@@ -60,17 +93,14 @@ module rggen_response_mux #(
       read_data <= '0;
     end
     else if (response_valid && i_read) begin
-      read_data <= select_read_data(
-        .select     (i_register_select    ),
-        .read_data  (i_register_read_data )
-      );
+      read_data <= get_read_data(i_register_select, i_register_read_data);
     end
     else begin
       read_data <= '0;
     end
   end
 
-  function automatic logic [DATA_WIDTH-1:0] select_read_data(
+  function automatic logic [DATA_WIDTH-1:0] get_read_data(
     input logic [TOTAL_REGISTERS-1:0] select,
     input logic [DATA_WIDTH-1:0]      read_data[TOTAL_REGISTERS]
   );

data/sample/sample.csv

@@ -1,14 +1,15 @@
-,block name,block_0,,,,,,,
-,byte size,256,,,,,,,
-,,,,,,,,,
-,offset address,registe name,array dimension,shadow index,assignment,field name,type,initial value,reference
-,0x00,register_0,,,[31:16],bit_field_0_0,rw,0,
-,,,,,[15:0],bit_field_0_1,rw,0,
-,0x04,register_1,,,[31:0],bit_field_1_0,rw,0,
-,0x08,register_2,,,[16],bit_field_2_0,ro,,
-,,,,,[0],bit_field_2_1,rw,0,
-,0x0C,register_3,,,[31:0],bit_field_3_0,ro,,
-,0x10 - 0x1F,register_4,[4],,[31:16],bit_field_4_0,ro,,
-,,,,,[15:0],bit_field_4_1,rw,0,
-,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",[31:16],bit_field_5_0,ro,,
-,,,,,[15:0],bit_field_5_1,rw,0,
+,block name,block_0,,,,,,,,
+,byte size,256,,,,,,,,
+,,,,,,,,,,
+,offset address,registe name,array dimension,shadow index,external,assignment,field name,type,initial value,reference
+,0x00,register_0,,,,[31:16],bit_field_0_0,rw,0,
+,,,,,,[15:0],bit_field_0_1,rw,0,
+,0x04,register_1,,,,[31:0],bit_field_1_0,rw,0,
+,0x08,register_2,,,,[16],bit_field_2_0,ro,,
+,,,,,,[0],bit_field_2_1,rw,0,
+,0x0C,register_3,,,,[31:0],bit_field_3_0,ro,,
+,0x10 - 0x1F,register_4,[4],,,[31:16],bit_field_4_0,ro,,
+,,,,,,[15:0],bit_field_4_1,rw,0,
+,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",,[31:16],bit_field_5_0,ro,,
+,,,,,,[15:0],bit_field_5_1,rw,0,
+,0x80-0xFF,register_6,,,true,,,,,

data/sample/sample_0.sv

@@ -20,19 +20,32 @@ module sample_0 (
   input [15:0] i_bit_field_4_0[4],
   output [15:0] o_bit_field_4_1[4],
   input [15:0] i_bit_field_5_0[2][4],
-  output [15:0] o_bit_field_5_1[2][4]
+  output [15:0] o_bit_field_5_1[2][4],
+  output o_register_6_valid,
+  output o_register_6_write,
+  output o_register_6_read,
+  output [6:0] o_register_6_address,
+  output [3:0] o_register_6_strobe,
+  output [31:0] o_register_6_write_data,
+  input i_register_6_ready,
+  input [1:0] i_register_6_status,
+  input [31:0] i_register_6_read_data
 );
   logic command_valid;
   logic write;
   logic read;
   logic [7:0] address;
+  logic [3:0] strobe;
   logic [31:0] write_data;
   logic [31:0] write_mask;
   logic response_ready;
   logic [31:0] read_data;
   logic [1:0] status;
-  logic [15:0] register_select;
-  logic [31:0] register_read_data[16];
+  logic [16:0] register_select;
+  logic [31:0] register_read_data[17];
+  logic [0:0] external_register_select;
+  logic [0:0] external_register_ready;
+  logic [1:0] external_register_status[1];
   logic [15:0] bit_field_0_0_value;
   logic [15:0] bit_field_0_1_value;
   logic [31:0] bit_field_1_0_value;
@@ -65,6 +78,7 @@ module sample_0 (
     .o_write          (write),
     .o_read           (read),
     .o_address        (address),
+    .o_strobe         (strobe),
     .o_write_data     (write_data),
     .o_write_mask     (write_mask),
     .i_response_ready (response_ready),
@@ -72,18 +86,22 @@ module sample_0 (
     .i_status         (status)
   );
   rggen_response_mux #(
-    .DATA_WIDTH       (32),
-    .TOTAL_REGISTERS  (16)
+    .DATA_WIDTH               (32),
+    .TOTAL_REGISTERS          (17),
+    .TOTAL_EXTERNAL_REGISTERS (1)
   ) u_response_mux (
-    .clk                  (clk),
-    .rst_n                (rst_n),
-    .i_command_valid      (command_valid),
-    .i_read               (read),
-    .o_response_ready     (response_ready),
-    .o_read_data          (read_data),
-    .o_status             (status),
-    .i_register_select    (register_select),
-    .i_register_read_data (register_read_data)
+    .clk                        (clk),
+    .rst_n                      (rst_n),
+    .i_command_valid            (command_valid),
+    .i_read                     (read),
+    .o_response_ready           (response_ready),
+    .o_read_data                (read_data),
+    .o_status                   (status),
+    .i_register_select          (register_select),
+    .i_register_read_data       (register_read_data),
+    .i_external_register_select (external_register_select),
+    .i_external_register_ready  (external_register_ready),
+    .i_external_register_status (external_register_status)
   );
   rggen_address_decoder #(
     .READABLE           (1),
@@ -288,4 +306,49 @@ module sample_0 (
       end
     end
   end endgenerate
+  rggen_address_decoder #(
+    .READABLE           (1),
+    .WRITABLE           (1),
+    .ADDRESS_WIDTH      (6),
+    .START_ADDRESS      (6'h20),
+    .END_ADDRESS        (6'h3f),
+    .USE_SHADOW_INDEX   (0),
+    .SHADOW_INDEX_WIDTH (1),
+    .SHADOW_INDEX_VALUE (1'h0)
+  ) u_register_6_address_decoder (
+    .i_read         (read),
+    .i_write        (write),
+    .i_address      (address[7:2]),
+    .i_shadow_index (1'h0),
+    .o_select       (register_select[16])
+  );
+  assign external_register_select[0] = register_select[16];
+  rggen_bus_exporter #(
+    .DATA_WIDTH             (32),
+    .LOCAL_ADDRESS_WIDTH    (8),
+    .EXTERNAL_ADDRESS_WIDTH (7),
+    .START_ADDRESS          (8'h80)
+  ) u_register_6_bus_exporter (
+    .clk          (clk),
+    .rst_n        (rst_n),
+    .i_valid      (command_valid),
+    .i_select     (register_select[16]),
+    .i_write      (write),
+    .i_read       (read),
+    .i_address    (address),
+    .i_strobe     (strobe),
+    .i_write_data (write_data),
+    .o_ready      (external_register_ready[0]),
+    .o_read_data  (register_read_data[16]),
+    .o_status     (external_register_status[0]),
+    .o_valid      (o_register_6_valid),
+    .o_write      (o_register_6_write),
+    .o_read       (o_register_6_read),
+    .o_address    (o_register_6_address),
+    .o_strobe     (o_register_6_strobe),
+    .o_write_data (o_register_6_write_data),
+    .i_ready      (i_register_6_ready),
+    .i_read_data  (i_register_6_read_data),
+    .i_status     (i_register_6_status)
+  );
 endmodule