rggen 0.3.3 → 0.4.0

data/lib/rggen/core_components.rb

@@ -9,6 +9,7 @@ require_relative 'core_components/register_map/loader'
 require_relative 'core_components/register_map/raise_error'
 require_relative 'core_components/register_map/component'
 require_relative 'core_components/register_map/item'
+require_relative 'core_components/register_map/component_factory'
 require_relative 'core_components/register_map/register_map_factory'
 require_relative 'core_components/register_map/register_block_factory'
 require_relative 'core_components/register_map/register_factory'
@@ -20,5 +21,6 @@ require_relative 'core_components/rtl/component'
 require_relative 'core_components/rtl/item'
 require_relative 'core_components/rtl/setup'
 
+require_relative 'core_components/ral/component'
 require_relative 'core_components/ral/item'
 require_relative 'core_components/ral/setup'

data/lib/rggen/core_components/configuration/item_factory.rb

@@ -5,7 +5,7 @@ module RgGen
 
       def create(configuration, data = nil)
         data  &&= convert(data)
-        create_item(configuration, data).tap do |item|
+        create_item(configuration, data) do |item|
           item.build(data) unless data.nil?
         end
       end

data/lib/rggen/core_components/ral/component.rb

@@ -0,0 +1,24 @@
+module RgGen
+  module RAL
+    class Component < OutputBase::Component
+      def build
+        super
+        @items.each do |item|
+          def_object_delegators(item, *item.identifiers)
+        end
+      end
+
+      def variable_declarations(domain)
+        [*@items, *@children].flat_map do |item_or_child|
+          item_or_child.variable_declarations(domain)
+        end
+      end
+
+      def parameter_declarations(domain)
+        [*@items, *@children].flat_map do |item_or_child|
+          item_or_child.parameter_declarations(domain)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/core_components/ral/item.rb

@@ -3,13 +3,58 @@ module RgGen
     class Item < OutputBase::Item
       use_verilog_utility
 
+      def initialize(owner)
+        super(owner)
+        @identifiers            = []
+        @variable_declarations  = Hash.new { |h, d| h[d]  = [] }
+        @parameter_declarations = Hash.new { |h, d| h[d]  = [] }
+      end
+
+      attr_reader :identifiers
+
+      class << self
+        private
+
+        def define_declaration_method(method_name)
+          define_method(method_name) do |domain, handle_name, attributes = {}|
+            attributes[:name] ||= handle_name
+            add_identifier(handle_name, attributes[:name])
+            add_declaration(method_name, domain, attributes)
+          end
+        end
+      end
+
+      define_declaration_method :variable
+      define_declaration_method :parameter
+
+      def variable_declarations(domain = nil)
+        return @variable_declarations if domain.nil?
+        @variable_declarations[domain]
+      end
+
+      def parameter_declarations(domain = nil)
+        return @parameter_declarations if domain.nil?
+        @parameter_declarations[domain]
+      end
+
       private
 
-      def model_declaration(model_class, name, attributes = {})
-        create_declaration(
-          :variable,
-          attributes.merge(data_type: model_class, name: name, random: true)
-        )
+      def add_identifier(handle_name, name)
+        create_identifier(name).tap do |i|
+          instance_variable_set(handle_name.variablize, i)
+          attr_singleton_reader(handle_name)
+          identifiers << handle_name
+        end
+      end
+
+      def add_declaration(type, domain, attributes)
+        create_declaration(type, attributes).tap do |d|
+          declarations  = {
+            variable: @variable_declarations,
+            parameter: @parameter_declarations
+          }.fetch(type)
+          declarations[domain] << d
+        end
       end
     end
   end

data/lib/rggen/core_components/ral/setup.rb

@@ -7,7 +7,7 @@ module RgGen
       end
 
       entry [:register_block, :register, :bit_field] do
-        component_class   OutputBase::Component
+        component_class   Component
         component_factory OutputBase::ComponentFactory
         item_base         Item
         item_factory      OutputBase::ItemFactory

data/lib/rggen/core_components/register_map/bit_field_factory.rb

@@ -1,6 +1,6 @@
 module RgGen
   module RegisterMap
-    class BitFieldFactory < InputBase::ComponentFactory
+    class BitFieldFactory < ComponentFactory
       def create_active_items(bit_field, configuration, cells)
         active_item_factories.each_value.with_index do |factory, index|
           create_item(factory, bit_field, configuration, cells[index])

data/lib/rggen/core_components/register_map/component.rb

@@ -3,10 +3,13 @@ module RgGen
     class Component < InputBase::Component
       include Base::HierarchicalAccessors
 
-      def initialize(parent)
+      def initialize(parent, configuration)
         super(parent)
+        @configuration  = configuration
         define_hierarchical_accessors
       end
+
+      attr_reader :configuration
     end
   end
 end

data/lib/rggen/core_components/register_map/component_factory.rb

@@ -0,0 +1,9 @@
+module RgGen
+  module RegisterMap
+    class ComponentFactory < InputBase::ComponentFactory
+      def create_component(parent, configuration, _)
+        @target_component.new(parent, configuration)
+      end
+    end
+  end
+end

data/lib/rggen/core_components/register_map/item.rb

@@ -4,7 +4,6 @@ module RgGen
       include Base::HierarchicalItemAccessors
       include RaiseError
 
-      attr_reader :configuration
       attr_reader :position
 
       def initialize(owner)
@@ -12,12 +11,15 @@ module RgGen
         define_hierarchical_item_accessors
       end
 
-      def build(configuration, cell)
-        @configuration  = configuration
-        unless cell.nil?
-          @position = cell.position
-          super(cell.value)
-        end
+      def build(cell)
+        @position = cell.position
+        super(cell.value)
+      end
+
+      private
+
+      def configuration
+        @owner.configuration
       end
     end
   end

data/lib/rggen/core_components/register_map/item_factory.rb

@@ -5,8 +5,8 @@ module RgGen
 
       def create(component, configuration, cell = nil)
         convert_cell_value(cell)
-        create_item(component, cell).tap do |item|
-          item.build(configuration, cell)
+        create_item(component, cell) do |item|
+          item.build(cell) unless cell.nil?
         end
       end
 

data/lib/rggen/core_components/register_map/register_block_factory.rb

@@ -1,6 +1,6 @@
 module RgGen
   module RegisterMap
-    class RegisterBlockFactory < InputBase::ComponentFactory
+    class RegisterBlockFactory < ComponentFactory
       def create_active_items(register_block, configuration, sheet)
         active_item_factories.each_value.with_index do |factory, index|
           cell  = sheet[index, 2]

data/lib/rggen/core_components/register_map/register_factory.rb

@@ -1,6 +1,6 @@
 module RgGen
   module RegisterMap
-    class RegisterFactory < InputBase::ComponentFactory
+    class RegisterFactory < ComponentFactory
       def create_active_items(register, configuration, rows)
         active_item_factories.each_value.with_index do |factory, index|
           create_item(factory, register, configuration, rows.first[index])

data/lib/rggen/core_components/register_map/register_map_factory.rb

@@ -1,6 +1,6 @@
 module RgGen
   module RegisterMap
-    class RegisterMapFactory < InputBase::ComponentFactory
+    class RegisterMapFactory < ComponentFactory
       def create_children(register_map, configuration, map)
         map.sheets.each do |sheet|
           create_child(register_map, configuration, sheet)

data/lib/rggen/core_components/rtl/item.rb

@@ -25,7 +25,7 @@ module RgGen
 
         def define_declaration_method(method_name)
           define_method(method_name) do |handle_name, attributes = {}|
-            attributes[:name] ||= handle_name.to_s
+            attributes[:name] ||= handle_name
             add_identifier(handle_name, attributes[:name])
             add_declaration(method_name, attributes)
           end

data/lib/rggen/input_base/component.rb

@@ -1,6 +1,15 @@
 module RgGen
   module InputBase
     class Component < Base::Component
+      def initialize(parent)
+        super(parent)
+        @need_children  = true
+      end
+
+      def need_no_children
+        @need_children  = false
+      end
+
       def add_item(item)
         super(item)
         def_object_delegators(@items.last, *item.fields)

data/lib/rggen/output_base/code_utility.rb

@@ -36,6 +36,12 @@ module RgGen
         code_block.indent -= indent_size
       end
 
+      def wrap(code_block, head, tail, &block)
+        code_block << head
+        block.call if block_given?
+        code_block << tail
+      end
+
       def loop_index(level)
         level.times.with_object('i') { |_, index| index.next! }
       end

data/lib/rggen/output_base/component.rb

@@ -8,6 +8,7 @@ module RgGen
         define_hierarchical_accessors
         @configuration  = configuration
         @register_map   = register_map
+        @need_children  = register_map.need_children?
         def_delegators(:@register_map, *@register_map.fields)
       end
 

data/lib/rggen/output_base/item_factory.rb

@@ -1,6 +1,9 @@
 module RgGen
   module OutputBase
     class ItemFactory < Base::ItemFactory
+      def create(owner, *args)
+        create_item(owner, *args)
+      end
     end
   end
 end

data/lib/rggen/output_base/verilog_utility/class_definition.rb

@@ -3,12 +3,20 @@ module RgGen
     module VerilogUtility
       class ClassDefinition < StructureDefinition
         attr_setter :base
+        attr_setter :parameters
+        attr_setter :variables
+
+        def to_code
+          bodies.unshift(variables_declarations) if variables?
+          super
+        end
 
         private
 
         def header_code
           code_block do |code|
             code << :class << space   << @name
+            paraemter_declarations(code) if parameters?
             code << space  <<:extends << space << @base unless @base.nil?
             code << semicolon
           end
@@ -17,6 +25,33 @@ module RgGen
         def footer_code
           :endclass
         end
+
+        def parameters?
+          !(@parameters.nil? || @parameters.empty?)
+        end
+
+        def variables?
+          !(@variables.nil? || @variables.empty?)
+        end
+
+        def paraemter_declarations(code)
+          wrap(code, '#(', ')') do
+            indent(code, 2) do
+              @parameters.each_with_index do |d, i|
+                code << comma << nl if i > 0
+                code << d
+              end
+            end
+          end
+        end
+
+        def variables_declarations
+          lambda do |code|
+            variables.each do |variable|
+              code << variable << semicolon << nl
+            end
+          end
+        end
       end
     end
   end

data/lib/rggen/output_base/verilog_utility/declaration.rb

@@ -30,7 +30,7 @@ module RgGen
           when :port
             @attributes[:direction] || ''
           when :parameter
-            @attributes[:parameter_type]
+            @attributes[:parameter_type] || ''
           end
         end
 
@@ -39,9 +39,7 @@ module RgGen
         end
 
         def width
-          return '' if @attributes[:width].nil?
-          return '' if (variable? || port?) && @attributes[:width] == 1
-          "[#{@attributes[:width] - 1}:0]"
+          (vector? && "[#{(@attributes[:width] || 1) - 1}:0]") || ''
         end
 
         def identifier
@@ -64,6 +62,15 @@ module RgGen
         def port?
           @declation_type == :port
         end
+
+        def parameter?
+          @declation_type == :parameter
+        end
+
+        def vector?
+          return true if @attributes[:vector]
+          @attributes[:width] && (parameter? || (@attributes[:width] > 1))
+        end
       end
     end
   end

data/lib/rggen/output_base/verilog_utility/identifier.rb

@@ -7,7 +7,7 @@ module RgGen
         end
 
         def to_s
-          @name
+          @name.to_s
         end
 
         def [](indexes_or_msb, lsb = indexes_or_msb)

data/lib/rggen/output_base/verilog_utility/module_definition.rb

@@ -4,6 +4,12 @@ module RgGen
       class ModuleDefinition < StructureDefinition
         attr_setter :parameters
         attr_setter :ports
+        attr_setter :signals
+
+        def to_code
+          bodies.unshift(signal_declarations) if signals?
+          super
+        end
 
         private
 
@@ -20,17 +26,37 @@ module RgGen
           :endmodule
         end
 
+        def parameters?
+          !(@parameters.nil? || @parameters.empty?)
+        end
+
+        def ports?
+          !(@ports.nil? || @ports.empty?)
+        end
+
+        def signals?
+          !(@signals.nil? || @signals.empty?)
+        end
+
         def parameter_declarations(code)
-          return if @parameters.nil? || @parameters.empty?
-          code << '#('
-          declarations(@parameters, code)
-          code << ')'
+          return unless parameters?
+          wrap(code, '#(', ')') do
+            declarations(@parameters, code)
+          end
         end
 
         def port_declarations(code)
-          code << '('
-          declarations(@ports, code) if @ports && @ports.size > 0
-          code << ')'
+          wrap(code, '(', ')') do
+            declarations(@ports, code) if ports?
+          end
+        end
+
+        def signal_declarations
+          lambda do |code|
+            signals.each do |signal|
+              code << signal << semicolon << nl
+            end
+          end
         end
 
         def declarations(list, code)