rggen-veryl 0.1.0

data/lib/rggen/veryl/utility/data_object.rb

@@ -0,0 +1,79 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      class DataObject
+        include Core::Utility::AttributeSetter
+
+        def initialize(object_type, default_attributes = {})
+          @object_type = object_type
+          apply_attributes(**default_attributes)
+          block_given? && yield(self)
+        end
+
+        define_attribute :name
+        define_attribute :direction
+        define_attribute :type, :logic
+        define_attribute :width
+        define_attribute :array_size
+        define_attribute :default
+
+        def declaration
+          declaration_snippets
+            .reject { _1.nil? || _1.empty? }
+            .join(' ')
+        end
+
+        def identifier
+          SystemVerilog::Common::Utility::Identifier.new(name) do |id|
+            id.__width__(width)
+            id.__array_size__(array_size)
+          end
+        end
+
+        private
+
+        def declaration_snippets
+          [
+            declaration_header,
+            "#{name}:",
+            direction_keyword,
+            type_declaration,
+            default_value
+          ]
+        end
+
+        def declaration_header
+          @object_type if @object_type in :var | :param | :const
+        end
+
+        def direction_keyword
+          @direction if @object_type == :port
+        end
+
+        def type_declaration
+          if emit_width? || array_size
+            "#{type}<#{array_dimensions.join(', ')}>"
+          else
+            type
+          end
+        end
+
+        def emit_width?
+          width && (!width.is_a?(Integer) || width >= 2)
+        end
+
+        def array_dimensions
+          dimensions = Array(array_size)
+          dimensions << width if emit_width?
+          dimensions
+        end
+
+        def default_value
+          "= #{default}" if @object_type in :param | :const
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/utility/interface_instance.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      class InterfaceInstance < SystemVerilog::Common::Utility::InterfaceInstance
+        define_attribute :param_values
+
+        def instantiation
+          [
+            'inst',
+            "#{name}:",
+            type_notation
+          ].join(' ')
+        end
+
+        alias_method :declaration, :instantiation
+
+        private
+
+        def type_notation
+          [
+            interface_type,
+            array_size_notation,
+            param_assignments
+          ].join
+        end
+
+        def array_size_notation
+          return if (array_size&.size || 0).zero?
+
+          "[#{array_size.join(', ')}]"
+        end
+
+        def param_assignments
+          return if (param_values&.size || 0).zero?
+
+          "#(#{param_values.map { |k, v| "#{k}: #{v}" }.join(', ')})"
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/utility/local_scope.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      class LocalScope < SystemVerilog::Common::Utility::StructureDefinition
+        define_attribute :name
+        define_attribute :consts
+        define_attribute :variables
+        define_attribute :loop_size
+
+        private
+
+        def header_code(code)
+          code << ":#{name} {" << nl
+        end
+
+        def footer_code(code)
+          code << '}'
+        end
+
+        def pre_body_code(code)
+          generate_for_header(code)
+          add_declarations_to_body(code, Array(consts))
+          add_declarations_to_body(code, Array(variables))
+        end
+
+        def generate_for_header(code)
+          loop_size&.each do |genvar, size|
+            code << "for #{genvar} in 0..#{size} :g {" << nl
+            code.indent += 2
+          end
+        end
+
+        def post_body_code(code)
+          generate_for_footer(code)
+        end
+
+        def generate_for_footer(code)
+          loop_size&.each do
+            code.indent -= 2
+            code << '}' << nl
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/utility/modport.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      class Modport < SystemVerilog::Common::Utility::InterfacePort
+        def declaration
+          [
+            "#{name}:",
+            'modport',
+            port_type
+          ].join(' ')
+        end
+
+        private
+
+        def port_type
+          "#{@interface_type}::#{@modport_name}#{array_size_notation}"
+        end
+
+        def array_size_notation
+          return if (@array_size&.size || 0).zero?
+
+          "[#{@array_size.join(', ')}]"
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/utility/module_definition.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      class ModuleDefinition < SystemVerilog::Common::Utility::StructureDefinition
+        define_attribute :name
+        define_attribute :package_imports
+        define_attribute :params
+        define_attribute :ports
+        define_attribute :variables
+
+        private
+
+        def header_code(code)
+          package_import_declaration(code)
+          module_header_begin(code)
+          param_declarations(code)
+          port_declarations(code)
+          module_header_end(code)
+        end
+
+        def package_import_declaration(code)
+          package_imports&.each do |package|
+            code << "import #{package}::*;" << nl
+          end
+        end
+
+        def module_header_begin(code)
+          code << "pub module #{name} "
+        end
+
+        def param_declarations(code)
+          return if (params&.size || 0).zero?
+
+          wrap(code, '#(', ')') do
+            add_declarations_to_header(code, params)
+          end
+        end
+
+        def port_declarations(code)
+          return if (ports&.size || 0).zero?
+
+          wrap(code, '(', ')') do
+            add_declarations_to_header(code, ports)
+          end
+        end
+
+        def module_header_end(code)
+          code << '{' << nl
+        end
+
+        def pre_body_code(code)
+          add_declarations_to_body(code, Array(variables))
+        end
+
+        def footer_code
+          '}'
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/utility.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module Utility
+      private
+
+      def local_scope(name, attributes = {}, &block)
+        LocalScope
+          .new(attributes.merge(name: name), &block)
+          .to_code
+      end
+
+      def module_definition(name, attributes = {}, &block)
+        ModuleDefinition
+          .new(attributes.merge(name: name), &block)
+          .to_code
+      end
+
+      def width_cast(expression, width)
+        "(#{expression} as #{width})"
+      end
+
+      def repeat(count, expression)
+        "{#{expression} repeat #{count}}"
+      end
+
+      def array(expressions)
+        concat(expressions.reverse)
+      end
+
+      def unused
+        '_'
+      end
+    end
+  end
+end

data/lib/rggen/veryl/version.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    VERSION = '0.1.0'
+  end
+end

data/lib/rggen/veryl.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+require_relative 'veryl/version'
+require_relative 'veryl/utility/data_object'
+require_relative 'veryl/utility/modport'
+require_relative 'veryl/utility/interface_instance'
+require_relative 'veryl/utility/local_scope'
+require_relative 'veryl/utility/module_definition'
+require_relative 'veryl/utility'
+require_relative 'veryl/component'
+require_relative 'veryl/feature'
+require_relative 'veryl/factories'
+
+RgGen.setup_plugin :'rggen-veryl' do |plugin|
+  plugin.version RgGen::Veryl::VERSION
+
+  plugin.register_component :veryl do
+    component RgGen::Veryl::Component,
+              RgGen::Veryl::ComponentFactory
+    feature RgGen::Veryl::Feature,
+            RgGen::Veryl::FeatureFactory
+  end
+
+  plugin.files [
+    'veryl/register_block/veryl_top',
+    'veryl/register_block/protocol',
+    'veryl/register_block/protocol/apb',
+    'veryl/register_block/protocol/axi4lite',
+    'veryl/register_block/protocol/wishbone',
+    'veryl/register_file/veryl_top',
+    'veryl/register/veryl_top',
+    'veryl/register/type',
+    'veryl/register/type/external',
+    'veryl/register/type/indirect',
+    'veryl/register/type/rw',
+    'veryl/bit_field/veryl_top',
+    'veryl/bit_field/type',
+    'veryl/bit_field/type/custom',
+    'veryl/bit_field/type/rc_w0c_w1c_wc_woc',
+    'veryl/bit_field/type/ro_rotrg',
+    'veryl/bit_field/type/rof',
+    'veryl/bit_field/type/rohw',
+    'veryl/bit_field/type/row0trg_row1trg',
+    'veryl/bit_field/type/rowo_rowotrg',
+    'veryl/bit_field/type/rs_w0s_w1s_ws_wos',
+    'veryl/bit_field/type/rw_rwtrg_w1',
+    'veryl/bit_field/type/rwc',
+    'veryl/bit_field/type/rwe_rwl',
+    'veryl/bit_field/type/rwhw',
+    'veryl/bit_field/type/rws',
+    'veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'veryl/bit_field/type/w0t_w1t',
+    'veryl/bit_field/type/w0trg_w1trg',
+    'veryl/bit_field/type/wo_wo1_wotrg',
+    'veryl/bit_field/type/wrc_wrs'
+  ]
+end

metadata

@@ -0,0 +1,133 @@
+--- !ruby/object:Gem::Specification
+name: rggen-veryl
+version: !ruby/object:Gem::Version
+  version: 0.1.0
+platform: ruby
+authors:
+- Taichi Ishitani
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2024-11-28 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: rggen-systemverilog
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.33.1
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.33.1
+description: Veryl writer plugin for RgGen
+email:
+- rggen@googlegroups.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- CODE_OF_CONDUCT.md
+- LICENSE
+- README.md
+- lib/rggen/veryl.rb
+- lib/rggen/veryl/bit_field/common.erb
+- lib/rggen/veryl/bit_field/type.rb
+- lib/rggen/veryl/bit_field/type/custom.erb
+- lib/rggen/veryl/bit_field/type/custom.rb
+- lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb
+- lib/rggen/veryl/bit_field/type/ro_rotrg.erb
+- lib/rggen/veryl/bit_field/type/ro_rotrg.rb
+- lib/rggen/veryl/bit_field/type/rof.erb
+- lib/rggen/veryl/bit_field/type/rof.rb
+- lib/rggen/veryl/bit_field/type/rohw.erb
+- lib/rggen/veryl/bit_field/type/rohw.rb
+- lib/rggen/veryl/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/veryl/bit_field/type/row0trg_row1trg.rb
+- lib/rggen/veryl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/veryl/bit_field/type/rowo_rowotrg.rb
+- lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb
+- lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb
+- lib/rggen/veryl/bit_field/type/rwc.erb
+- lib/rggen/veryl/bit_field/type/rwc.rb
+- lib/rggen/veryl/bit_field/type/rwe_rwl.erb
+- lib/rggen/veryl/bit_field/type/rwe_rwl.rb
+- lib/rggen/veryl/bit_field/type/rwhw.erb
+- lib/rggen/veryl/bit_field/type/rwhw.rb
+- lib/rggen/veryl/bit_field/type/rws.erb
+- lib/rggen/veryl/bit_field/type/rws.rb
+- lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+- lib/rggen/veryl/bit_field/type/w0t_w1t.erb
+- lib/rggen/veryl/bit_field/type/w0t_w1t.rb
+- lib/rggen/veryl/bit_field/type/w0trg_w1trg.erb
+- lib/rggen/veryl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb
+- lib/rggen/veryl/bit_field/type/wrc_wrs.erb
+- lib/rggen/veryl/bit_field/type/wrc_wrs.rb
+- lib/rggen/veryl/bit_field/veryl_top.rb
+- lib/rggen/veryl/component.rb
+- lib/rggen/veryl/factories.rb
+- lib/rggen/veryl/feature.rb
+- lib/rggen/veryl/register/type.rb
+- lib/rggen/veryl/register/type/default.erb
+- lib/rggen/veryl/register/type/external.erb
+- lib/rggen/veryl/register/type/external.rb
+- lib/rggen/veryl/register/type/indirect.erb
+- lib/rggen/veryl/register/type/indirect.rb
+- lib/rggen/veryl/register/type/rw.erb
+- lib/rggen/veryl/register/type/rw.rb
+- lib/rggen/veryl/register/veryl_top.rb
+- lib/rggen/veryl/register_block/protocol.rb
+- lib/rggen/veryl/register_block/protocol/apb.erb
+- lib/rggen/veryl/register_block/protocol/apb.rb
+- lib/rggen/veryl/register_block/protocol/axi4lite.erb
+- lib/rggen/veryl/register_block/protocol/axi4lite.rb
+- lib/rggen/veryl/register_block/protocol/wishbone.erb
+- lib/rggen/veryl/register_block/protocol/wishbone.rb
+- lib/rggen/veryl/register_block/veryl_top.rb
+- lib/rggen/veryl/register_file/veryl_top.rb
+- lib/rggen/veryl/utility.rb
+- lib/rggen/veryl/utility/data_object.rb
+- lib/rggen/veryl/utility/interface_instance.rb
+- lib/rggen/veryl/utility/local_scope.rb
+- lib/rggen/veryl/utility/modport.rb
+- lib/rggen/veryl/utility/module_definition.rb
+- lib/rggen/veryl/version.rb
+homepage: https://github.com/rggen/rggen-veryl
+licenses:
+- MIT
+metadata:
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
+  mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
+  source_code_uri: https://github.com/rggen/rggen-vhdl
+  wiki_uri: https://github.com/rggen/rggen/wiki
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: 3.0.0
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.5.16
+signing_key: 
+specification_version: 4
+summary: rggen-veryl-0.1.0
+test_files: []