rggen-veryl 0.1.0

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -0,0 +1,21 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:            <%= width %>,
+  INITIAL_VALUE:    <%= initial_value %>,
+  SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
+  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  <%= sw_write_enable %>,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         <%= clear[loop_variables] %>,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
+  veryl do
+    build do
+      input :clear, {
+        name: "i_#{full_name}_clear",
+        width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        rs: 'READ_SET', wos: 'READ_NONE'
+      }.fetch(bit_field.type, 'READ_DEFAULT')
+    end
+
+    def write_action
+      {
+        rs: 'WRITE_NONE', w0s: 'WRITE_0_SET', w1s: 'WRITE_1_SET'
+      }.fetch(bit_field.type, 'WRITE_SET')
+    end
+
+    def sw_write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.erb

@@ -0,0 +1,21 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>,
+  SW_WRITE_ONCE:  <%= write_once %>,
+  TRIGGER:        <%= trigger %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    <%= write_trigger_signal %>,
+  o_read_trigger:     <%= read_trigger_signal %>,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  veryl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger",
+          width: 1, array_size: array_size
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger",
+          width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def trigger
+      rwtrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || unused
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || unused
+    end
+
+    def write_once
+      bit_field.type == :w1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/rwc.erb

@@ -0,0 +1,20 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>,
+  HW_CLEAR_WIDTH: 1
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         <%= clear_signal %>,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rwc.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  veryl do
+    build do
+      unless bit_field.reference?
+        input :clear, {
+          name: "i_#{full_name}_clear",
+          width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/rwe_rwl.erb

@@ -0,0 +1,20 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:                    <%= width %>,
+  INITIAL_VALUE:            <%= initial_value %>,
+  SW_WRITE_ENABLE_POLARITY: rggen_polarity::<%= polarity %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  <%= control_signal %>,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  veryl do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}",
+          width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: 'enable', rwl: 'lock' }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+
+    def polarity
+      { rwe: 'ACTIVE_HIGH', rwl: 'ACTIVE_LOW' }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/rwhw.erb

@@ -0,0 +1,19 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  <%= valid_signal %>,
+  i_hw_write_data:    <%= value_in[loop_variables] %>,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rwhw.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  veryl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid",
+          width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}",
+        width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/rws.erb

@@ -0,0 +1,20 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>,
+  HW_SET_WIDTH:   1
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           <%= set_signal %>,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/rws.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rws) do
+  veryl do
+    build do
+      unless bit_field.reference?
+        input :set, {
+          name: "i_#{full_name}_set",
+          width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_signal
+      reference_bit_field || set[loop_variables]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -0,0 +1,21 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:            <%= width %>,
+  INITIAL_VALUE:    <%= initial_value %>,
+  SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
+  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(
+  :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
+) do
+  veryl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        w0crs: 'READ_SET', w1crs: 'READ_SET', wcrs: 'READ_SET'
+      }.fetch(bit_field.type, 'READ_CLEAR')
+    end
+
+    def write_action
+      {
+        w0crs: 'WRITE_0_CLEAR',
+        w0src: 'WRITE_0_SET',
+        w1crs: 'WRITE_1_CLEAR',
+        w1src: 'WRITE_1_SET',
+        wcrs: 'WRITE_CLEAR',
+        wsrc: 'WRITE_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,20 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:            <%= width %>,
+  INITIAL_VALUE:    <%= initial_value %>,
+  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  veryl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def write_action
+      {
+        w0t: 'WRITE_0_TOGGLE',
+        w1t: 'WRITE_1_TOGGLE'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/w0trg_w1trg.erb

@@ -0,0 +1,10 @@
+inst u_bit_field: rggen::rggen_bit_field_w01trg #(
+  TRIGGER_VALUE:  <%= trigger_value %>,
+  WIDTH:          <%= width %>
+)(
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  i_value:      '0,
+  o_trigger:    <%= trigger[loop_variables] %>
+);

data/lib/rggen/veryl/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  veryl do
+    build do
+      output :trigger, {
+        name: "o_#{full_name}_trigger",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.erb

@@ -0,0 +1,22 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>,
+  SW_READ_ACTION: rggen_sw_action::READ_NONE,
+  SW_WRITE_ONCE:  <%= write_once %>,
+  TRIGGER:        <%= trigger %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    <%= write_trigger_signal %>,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  veryl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger",
+          width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def trigger
+      wotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || unused
+    end
+
+    def write_once
+      bit_field.type == :wo1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,20 @@
+inst u_bit_field: rggen::rggen_bit_field #(
+  WIDTH:          <%= width %>,
+  INITIAL_VALUE:  <%= initial_value %>,
+  SW_READ_ACTION: rggen_sw_action::<%= read_action %>
+)(
+  i_clk:              <%= clock %>,
+  i_rst:              <%= reset %>,
+  bit_field_if:       <%= bit_field_if %>,
+  o_write_trigger:    _,
+  o_read_trigger:     _,
+  i_sw_write_enable:  '1,
+  i_hw_write_enable:  '0,
+  i_hw_write_data:    '0,
+  i_hw_set:           '0,
+  i_hw_clear:         '0,
+  i_value:            '0,
+  i_mask:             '1,
+  o_value:            <%= value_out[loop_variables] %>,
+  o_value_unmasked:   _
+);

data/lib/rggen/veryl/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  veryl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}",
+        width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      { wrc: 'READ_CLEAR', wrs: 'READ_SET' }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/veryl/bit_field/type.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:bit_field, :type) do
+  veryl do
+    base_feature do
+      pre_code :bit_field, from_template: File.join(__dir__, 'common.erb')
+
+      private
+
+      def full_name
+        bit_field.full_name('_')
+      end
+
+      def width
+        bit_field.width
+      end
+
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
+      def array_size
+        bit_field.array_size
+      end
+
+      def initial_value
+        index =
+          bit_field.initial_value_array? && bit_field.local_index || nil
+        bit_field.initial_value[index]
+      end
+
+      def bit_field_if
+        bit_field.bit_field_sub_if
+      end
+
+      def reference_bit_field
+        return unless bit_field.reference?
+
+        bit_field
+          .find_reference(register_block.bit_fields)
+          .value(bit_field.local_indices, bit_field.reference_width)
+      end
+
+      def mask
+        reference_bit_field || all_bits_1
+      end
+
+      def loop_variables
+        bit_field.loop_variables
+      end
+    end
+
+    factory do
+      def target_feature_key(_configuration, bit_field)
+        return bit_field.type if target_features.key?(bit_field.type)
+
+        error "code generator for #{bit_field.type} " \
+              'bit field type is not implemented'
+      end
+    end
+  end
+end