rggen-veryl 0.1.0

data/lib/rggen/veryl/bit_field/veryl_top.rb

@@ -0,0 +1,102 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :veryl_top) do
+  veryl do
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
+    build do
+      if bit_field.fixed_initial_value?
+        const :initial_value, {
+          name: initial_value_name, type: :bit, width: bit_field.width,
+          array_size: initial_value_size, default: initial_value_rhs
+        }
+      elsif bit_field.initial_value?
+        param :initial_value, {
+          name: initial_value_name, type: :bit, width: bit_field.width,
+          array_size: initial_value_size, default: initial_value_rhs
+        }
+      end
+
+      interface :bit_field_sub_if, {
+        name: 'bit_field_sub_if', interface_type: 'rggen::rggen_bit_field_if',
+        param_values: { WIDTH: bit_field.width },
+        variables: [
+          'valid', 'read_mask', 'write_mask', 'write_data', 'read_data', 'value'
+        ]
+      }
+    end
+
+    main_code :register do
+      local_scope("g_#{bit_field.name}") do |s|
+        s.loop_size loop_size
+        s.consts consts
+        s.variables variables
+        s.body { |c| body_code(c) }
+      end
+    end
+
+    export def value(offsets = nil, width = nil)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
+      value_width = width || bit_field.width
+      register_if(offsets&.[](0..-2)).value[value_lsb, value_width]
+    end
+
+    private
+
+    def initial_value_name
+      if bit_field.fixed_initial_value?
+        'INITIAL_VALUE'
+      else
+        "#{bit_field.full_name('_').upcase}_INITIAL_VALUE"
+      end
+    end
+
+    def initial_value_size
+      return unless bit_field.initial_value_array?
+
+      [bit_field.sequence_size]
+    end
+
+    def initial_value_rhs
+      if !bit_field.initial_value_array?
+        sized_initial_value
+      elsif bit_field.fixed_initial_value?
+        array(sized_initial_values)
+      else
+        repeat(bit_field.sequence_size, sized_initial_value)
+      end
+    end
+
+    def sized_initial_value
+      hex(bit_field.initial_value, bit_field.width)
+    end
+
+    def sized_initial_values
+      bit_field.initial_values.map { |v| hex(v, bit_field.width) }
+    end
+
+    def register_if(offsets)
+      index = register.index(offsets || register.local_indices)
+      register_block.register_if[index]
+    end
+
+    def loop_size
+      loop_variable = local_index
+      return unless loop_variable
+
+      { loop_variable => bit_field.sequence_size }
+    end
+
+    def consts
+      bit_field.declarations[:parameter]
+    end
+
+    def variables
+      bit_field.declarations[:variable]
+    end
+
+    def body_code(code)
+      bit_field.generate_code(code, :bit_field, :top_down)
+    end
+  end
+end

data/lib/rggen/veryl/component.rb

@@ -0,0 +1,8 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    class Component < SystemVerilog::Common::Component
+    end
+  end
+end

data/lib/rggen/veryl/factories.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
+    end
+
+    class FeatureFactory < Core::OutputBase::FeatureFactory
+    end
+  end
+end

data/lib/rggen/veryl/feature.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    class Feature < SystemVerilog::Common::Feature
+      include Utility
+
+      private
+
+      def create_if_instance(_, attributes, &block)
+        InterfaceInstance.new(attributes, &block)
+      end
+
+      def create_port(direction, attributes, &block)
+        attributes =
+          { direction: direction }
+            .merge(attributes)
+        DataObject.new(:port, attributes, &block)
+      end
+
+      def create_modport(_, attributes, &block)
+        Modport.new(attributes, &block)
+      end
+
+      def create_param(_, attributes, &block)
+        DataObject.new(:param, attributes, &block)
+      end
+
+      def create_const(_, attributes, &block)
+        DataObject.new(:const, attributes, &block)
+      end
+
+      def create_var(_, attributes, &block)
+        DataObject.new(:var, attributes, &block)
+      end
+
+      define_entity :input, :create_port, :port, -> { register_block }
+      define_entity :output, :create_port, :port, -> { register_block }
+      define_entity :modport, :create_modport, :port, -> { register_block }
+      define_entity :interface, :create_if_instance, :variable, -> { component }
+      define_entity :param, :create_param, :parameter, -> { register_block }
+      define_entity :const, :create_const, :parameter, -> { component }
+      define_entity :var, :create_var, :variable, -> { component }
+    end
+  end
+end

data/lib/rggen/veryl/register/type/default.erb

@@ -0,0 +1,15 @@
+inst u_register: rggen::rggen_default_register #(
+  READABLE:       <%= readable %>,
+  WRITABLE:       <%= writable %>,
+  ADDRESS_WIDTH:  <%= address_width %>,
+  OFFSET_ADDRESS: <%= offset_address %>,
+  BUS_WIDTH:      <%= bus_width %>,
+  DATA_WIDTH:     <%= width %>,
+  VALUE_WIDTH:    <%= value_width %>,
+  VALID_BITS:     <%= valid_bits %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  register_if:  <%= register_if %>,
+  bit_field_if: <%= bit_field_if %>
+);

data/lib/rggen/veryl/register/type/external.erb

@@ -0,0 +1,13 @@
+inst u_register: rggen::rggen_external_register #(
+  ADDRESS_WIDTH:  <%= address_width %>,
+  BUS_WIDTH:      <%= bus_width %>,
+  VALUE_WIDTH:    <%= value_width %>,
+  STROBE_WIDTH:   <%= strobe_width %>,
+  START_ADDRESS:  <%= start_address %>,
+  BYTE_SIZE:      <%= byte_size %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  register_if:  <%= register_if %>,
+  bus_if:       <%= bus_if %>
+);

data/lib/rggen/veryl/register/type/external.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :external) do
+  veryl do
+    build do
+      param :strobe_width, {
+        name: "#{register.name}_strobe_width".upcase,
+        type: :u32, default: configuration.byte_width
+      }
+      modport :bus_if, {
+        name: "#{register.name}_bus_if",
+        interface_type: 'rggen::rggen_bus_if', modport: 'master'
+      }
+    end
+
+    main_code :register, from_template: true
+
+    private
+
+    def start_address
+      hex(register.address_range.begin, address_width)
+    end
+
+    def byte_size
+      register.total_byte_size
+    end
+  end
+end

data/lib/rggen/veryl/register/type/indirect.erb

@@ -0,0 +1,17 @@
+inst u_register: rggen::rggen_indirect_register #(
+  READABLE:             <%= readable %>,
+  WRITABLE:             <%= writable %>,
+  ADDRESS_WIDTH:        <%= address_width %>,
+  OFFSET_ADDRESS:       <%= offset_address %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  DATA_WIDTH:           <%= width %>,
+  VALUE_WIDTH:          <%= value_width %>,
+  VALID_BITS:           <%= valid_bits %>,
+  INDIRECT_MATCH_WIDTH: <%= index_match_width %>
+)(
+  i_clk:            <%= register_block.clock %>,
+  i_rst:            <%= register_block.reset %>,
+  register_if:      <%= register_if %>,
+  i_indirect_match: <%= indirect_match %>,
+  bit_field_if:     <%= bit_field_if %>
+);

data/lib/rggen/veryl/register/type/indirect.rb

@@ -0,0 +1,22 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :indirect) do
+  veryl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
+    build do
+      var :indirect_match, { width: index_match_width }
+    end
+
+    main_code :register do |code|
+      indirect_index_matches(code)
+      code << process_template
+    end
+
+    private
+
+    def array_index_value(value, width)
+      width_cast(value, width)
+    end
+  end
+end

data/lib/rggen/veryl/register/type/rw.erb

@@ -0,0 +1,15 @@
+inst u_register: rggen::rggen_default_register #(
+  READABLE:       1,
+  WRITABLE:       1,
+  ADDRESS_WIDTH:  <%= address_width %>,
+  OFFSET_ADDRESS: <%= offset_address %>,
+  BUS_WIDTH:      <%= bus_width %>,
+  DATA_WIDTH:     <%= width %>,
+  VALUE_WIDTH:    <%= value_width %>,
+  VALID_BITS:     <%= valid_bits %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  register_if:  <%= register_if %>,
+  bit_field_if: <%= bit_field_if %>
+);

data/lib/rggen/veryl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  veryl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/veryl/register/type.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  veryl do
+    base_feature do
+      include RgGen::SystemVerilog::RTL::RegisterType
+
+      private
+
+      def register_if
+        register_block.register_if[register.index]
+      end
+
+      def bit_field_if
+        register.bit_field_if
+      end
+    end
+
+    default_feature do
+      template = File.join(__dir__, 'type', 'default.erb')
+      main_code :register, from_template: template
+    end
+
+    factory do
+      def target_feature_key(_configuration, register)
+        type = register.type
+        return type if [:default, *target_features.keys].any? { type == _1 }
+
+        error "code generator for #{type} register type " \
+              'is not implemented'
+      end
+    end
+  end
+end

data/lib/rggen/veryl/register/veryl_top.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :veryl_top) do
+  veryl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    build do
+      unless register.bit_fields.empty?
+        interface :bit_field_if, {
+          name: 'bit_field_if', interface_type: 'rggen::rggen_bit_field_if',
+          param_values: { WIDTH: register.width },
+          variables: [
+            'valid', 'read_mask', 'write_mask', 'write_data', 'read_data', 'value'
+          ]
+        }
+      end
+    end
+
+    main_code :register_file do
+      local_scope("g_#{register.name}") do |s|
+        s.loop_size loop_size
+        s.variables variables
+        s.body { |c| body_code(c) }
+      end
+    end
+
+    private
+
+    def loop_size
+      return nil unless register.array?
+
+      local_loop_variables.zip(register.array_size).to_h
+    end
+
+    def variables
+      register.declarations[:variable]
+    end
+
+    def body_code(code)
+      register.generate_code(code, :register, :top_down)
+    end
+  end
+end

data/lib/rggen/veryl/register_block/protocol/apb.erb

@@ -0,0 +1,17 @@
+inst u_adapter: rggen::rggen_apb_adapter #(
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  apb_if:       <%= apb_if %>,
+  register_if:  <%= register_block.register_if %>
+);

data/lib/rggen/veryl/register_block/protocol/apb.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
+  veryl do
+    build do
+      modport :apb_if, {
+        name: 'apb_if',
+        interface_type: 'rggen::rggen_apb_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol/axi4lite.erb

@@ -0,0 +1,19 @@
+inst u_adapter: rggen::rggen_axi4lite_adapter #(
+  ID_WIDTH:             <%= id_width %>,
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>,
+  WRITE_FIRST:          <%= write_first %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  axi4lite_if:  <%= axi4lite_if %>,
+  register_if:  <%= register_block.register_if %>
+);

data/lib/rggen/veryl/register_block/protocol/axi4lite.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
+  veryl do
+    build do
+      param :id_width, {
+        name: 'ID_WIDTH', type: :u32, default: 0
+      }
+      param :write_first, {
+        name: 'WRITE_FIRST', type: :bit, default: 1
+      }
+      modport :axi4lite_if, {
+        name: 'axi4lite_if',
+        interface_type: 'rggen::rggen_axi4lite_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol/wishbone.erb

@@ -0,0 +1,18 @@
+inst u_adapter: rggen::rggen_wishbone_adapter #(
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>,
+  USE_STALL:            <%= use_stall %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  wishbone_if:  <%= wishbone_if %>,
+  register_if:  <%= register_block.register_if %>
+);

data/lib/rggen/veryl/register_block/protocol/wishbone.rb

@@ -0,0 +1,17 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  veryl do
+    build do
+      param :use_stall, {
+        name: 'USE_STALL', type: :bit, default: 1
+      }
+      modport :wishbone_if, {
+        name: 'wishbone_if', interface_type:
+        'rggen::rggen_wishbone_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register_block, :protocol) do
+  veryl do
+    shared_context.feature_registry(registry)
+
+    base_feature do
+      build do
+        param :address_width, {
+          name: 'ADDRESS_WIDTH', type: :u32, default: local_address_width
+        }
+        param :pre_decode, {
+          name: 'PRE_DECODE', type: :bit, default: 0
+        }
+        param :base_address, {
+          name: 'BASE_ADDRESS', type: :bit, width: address_width, default: all_bits_0
+        }
+        param :error_status, {
+          name: 'ERROR_STATUS', type: :bit, default: 0
+        }
+        param :default_read_data, {
+          name: 'DEFAULT_READ_DATA', type: :bit, width: bus_width, default: all_bits_0
+        }
+        param :insert_slicer, {
+          name: 'INSERT_SLICER', type: :bit, default: 0
+        }
+      end
+
+      private
+
+      def bus_width
+        configuration.bus_width
+      end
+
+      def local_address_width
+        register_block.local_address_width
+      end
+
+      def total_registers
+        register_block.files_and_registers.sum(&:count)
+      end
+
+      def byte_size
+        register_block.byte_size
+      end
+    end
+
+    factory do
+      def target_feature_key(configuration, _register_block)
+        configuration.protocol
+      end
+    end
+  end
+end

data/lib/rggen/veryl/register_block/veryl_top.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :veryl_top) do
+  veryl do
+    build do
+      input :clock, { name: 'i_clk', type: :clock }
+      input :reset, { name: 'i_rst', type: :reset }
+
+      interface :register_if, {
+        name: 'register_if', interface_type: 'rggen::rggen_register_if',
+        param_values: param_values, array_size: [total_registers], variables: ['value']
+      }
+    end
+
+    export def value_width
+      register_block.registers.max_by(&:width)&.width
+    end
+
+    export def total_registers
+      register_block.files_and_registers.sum(&:count)
+    end
+
+    write_file '<%= register_block.name %>.veryl' do |f|
+      f.body do |code|
+        code << module_definition(register_block.name) do |m|
+          m.package_imports packages
+          m.params params
+          m.ports ports
+          m.variables variables
+          m.body { |c| body_code(c) }
+        end
+      end
+    end
+
+    private
+
+    def param_values
+      { ADDRESS_WIDTH: address_width, BUS_WIDTH: bus_width, VALUE_WIDTH: value_width }
+    end
+
+    def address_width
+      register_block.local_address_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def packages
+      ['rggen::rggen_rtl_pkg', *register_block.package_imports(:register_block)]
+    end
+
+    def params
+      register_block.declarations[:parameter]
+    end
+
+    def ports
+      register_block.declarations[:port]
+    end
+
+    def variables
+      register_block.declarations[:variable]
+    end
+
+    def body_code(code)
+      { register_block: nil, register_file: 1 }.each do |kind, depth|
+        register_block.generate_code(code, kind, :top_down, depth)
+      end
+    end
+  end
+end

data/lib/rggen/veryl/register_file/veryl_top.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :veryl_top) do
+  veryl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |s|
+        s.loop_size loop_size
+        s.body { |c| body_code(c) }
+      end
+    end
+
+    private
+
+    def loop_size
+      return nil unless register_file.array?
+
+      local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end