rggen-systemverilog 0.25.1 → 0.27.0

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Files changed (49) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +3 -2
  4. data/lib/rggen/systemverilog/common/utility/identifier.rb +1 -1
  5. data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb +9 -0
  6. data/lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb +5 -0
  7. data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb +8 -0
  8. data/lib/rggen/systemverilog/ral/bit_field/type.rb +19 -6
  9. data/lib/rggen/systemverilog/ral/register_common.rb +1 -1
  10. data/lib/rggen/systemverilog/ral.rb +24 -27
  11. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +0 -16
  12. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +2 -0
  13. data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb} +8 -4
  14. data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb +40 -0
  15. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +5 -2
  16. data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb +10 -0
  17. data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.rb → row0trg_row1trg.rb} +10 -2
  18. data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb +21 -0
  19. data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb +52 -0
  20. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +2 -0
  21. data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb} +4 -2
  22. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb +46 -0
  23. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +2 -0
  24. data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +2 -0
  25. data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +2 -0
  26. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +2 -0
  27. data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +2 -0
  28. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +1 -0
  29. data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb +22 -0
  30. data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb +38 -0
  31. data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +2 -0
  32. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +15 -0
  33. data/lib/rggen/systemverilog/rtl/register/type/default.erb +0 -1
  34. data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -54
  35. data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +0 -1
  36. data/lib/rggen/systemverilog/rtl/register/type.rb +12 -0
  37. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +3 -60
  38. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +4 -118
  39. data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb +17 -0
  40. data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb +26 -0
  41. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -1
  42. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +12 -0
  43. data/lib/rggen/systemverilog/rtl.rb +38 -41
  44. data/lib/rggen/systemverilog/version.rb +1 -1
  45. metadata +22 -13
  46. data/lib/rggen/systemverilog/ral/setup.rb +0 -8
  47. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +0 -24
  48. data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +0 -28
  49. data/lib/rggen/systemverilog/rtl/setup.rb +0 -14
data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb DELETED
@@ -1,28 +0,0 @@
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- # frozen_string_literal: true
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-
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- RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
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- configuration do
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- property :fold_sv_interface_port?, default: true
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-
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- input_pattern [
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- /true|on|yes/i, /false|off|no/i
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- ], match_automatically: false
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-
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- ignore_empty_value false
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-
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- build do |value|
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- @fold_sv_interface_port =
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- if [true, false].include?(value)
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- value
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- elsif match_pattern(value)
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- [true, false][match_index]
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- else
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- error "cannot convert #{value.inspect} into boolean"
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- end
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- end
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-
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- printable :fold_sv_interface_port do
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- fold_sv_interface_port?
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- end
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- end
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- end
data/lib/rggen/systemverilog/rtl/setup.rb DELETED
@@ -1,14 +0,0 @@
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- # frozen_string_literal: true
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-
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- require 'rggen/systemverilog/rtl'
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-
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- RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
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- builder.enable :global, [
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- :array_port_format, :fold_sv_interface_port
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- ]
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- builder.enable :register_block, [:sv_rtl_top, :protocol]
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- builder.enable :register_block, :protocol, [:apb, :axi4lite]
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- builder.enable :register_file, [:sv_rtl_top]
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- builder.enable :register, [:sv_rtl_top]
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- builder.enable :bit_field, [:sv_rtl_top]
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- end