rggen-systemverilog 0.25.1 → 0.27.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +3 -2
- data/lib/rggen/systemverilog/common/utility/identifier.rb +1 -1
- data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb +9 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb +8 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +19 -6
- data/lib/rggen/systemverilog/ral/register_common.rb +1 -1
- data/lib/rggen/systemverilog/ral.rb +24 -27
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +0 -16
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb} +8 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb +40 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.rb → row0trg_row1trg.rb} +10 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb +21 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb +52 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb +46 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +1 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb +22 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb +38 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +15 -0
- data/lib/rggen/systemverilog/rtl/register/type/default.erb +0 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -54
- data/lib/rggen/systemverilog/rtl/register/type/indirect.erb +0 -1
- data/lib/rggen/systemverilog/rtl/register/type.rb +12 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +3 -60
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +4 -118
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb +26 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -1
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb +12 -0
- data/lib/rggen/systemverilog/rtl.rb +38 -41
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +22 -13
- data/lib/rggen/systemverilog/ral/setup.rb +0 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +0 -24
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +0 -28
- data/lib/rggen/systemverilog/rtl/setup.rb +0 -14
|
@@ -1,28 +0,0 @@
|
|
|
1
|
-
# frozen_string_literal: true
|
|
2
|
-
|
|
3
|
-
RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
|
|
4
|
-
configuration do
|
|
5
|
-
property :fold_sv_interface_port?, default: true
|
|
6
|
-
|
|
7
|
-
input_pattern [
|
|
8
|
-
/true|on|yes/i, /false|off|no/i
|
|
9
|
-
], match_automatically: false
|
|
10
|
-
|
|
11
|
-
ignore_empty_value false
|
|
12
|
-
|
|
13
|
-
build do |value|
|
|
14
|
-
@fold_sv_interface_port =
|
|
15
|
-
if [true, false].include?(value)
|
|
16
|
-
value
|
|
17
|
-
elsif match_pattern(value)
|
|
18
|
-
[true, false][match_index]
|
|
19
|
-
else
|
|
20
|
-
error "cannot convert #{value.inspect} into boolean"
|
|
21
|
-
end
|
|
22
|
-
end
|
|
23
|
-
|
|
24
|
-
printable :fold_sv_interface_port do
|
|
25
|
-
fold_sv_interface_port?
|
|
26
|
-
end
|
|
27
|
-
end
|
|
28
|
-
end
|
|
@@ -1,14 +0,0 @@
|
|
|
1
|
-
# frozen_string_literal: true
|
|
2
|
-
|
|
3
|
-
require 'rggen/systemverilog/rtl'
|
|
4
|
-
|
|
5
|
-
RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
|
|
6
|
-
builder.enable :global, [
|
|
7
|
-
:array_port_format, :fold_sv_interface_port
|
|
8
|
-
]
|
|
9
|
-
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
|
10
|
-
builder.enable :register_block, :protocol, [:apb, :axi4lite]
|
|
11
|
-
builder.enable :register_file, [:sv_rtl_top]
|
|
12
|
-
builder.enable :register, [:sv_rtl_top]
|
|
13
|
-
builder.enable :bit_field, [:sv_rtl_top]
|
|
14
|
-
end
|