rggen-systemverilog 0.25.1 → 0.27.0

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: 63eaedf2f45061b5af697700a3b577298c470cb078e45ae59e7dd41cf552f1607e9c5a553ecede94f1b3e49b96b386f0af6326fcdd0715b6a187a4c1aad954fa

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2021 Taichi Ishitani
+Copyright (c) 2019-2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -27,14 +27,15 @@ $ gem isntall rggen-systemverilog
 
 Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
 
-* [GitHub Issue Tracker](https://github.com/rggen/rggen-systemverilog/issues)
+* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
+* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
 * [Chat Room](https://gitter.im/rggen/rggen)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -96,7 +96,7 @@ module RgGen
 
           def __index_factors__
             Array.new(@array_size.size) do |i|
-              i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
+              i.zero? ? nil : __reduce_array__(@array_size[-i..], :*, 1)
             end
           end
 

data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rotrg, :rwtrg, :wotrg]) do
+  sv_ral do
+    access do
+      { rotrg: :ro, rwtrg: :rw, wotrg: :wo }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,8 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_ral do
+    access 'rowo'
+    model_name { 'rggen_ral_rowo_field' }
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -4,11 +4,20 @@ RgGen.define_list_feature(:bit_field, :type) do
   sv_ral do
     base_feature do
       define_helpers do
-        attr_setter :access
+        def access(access_type = nil, &block)
+          attribute_accessor('@access', access_type, &block)
+        end
 
         def model_name(name = nil, &block)
-          @model_name = name || block || @model_name
-          @model_name
+          attribute_accessor('@model_name', name, &block)
+        end
+
+        private
+
+        def attribute_accessor(variable_name, value, &block)
+          (new_value = value || block) &&
+            instance_variable_set(variable_name, new_value)
+          instance_variable_get(variable_name)
         end
       end
 
@@ -24,12 +33,11 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def access
-        (helper.access || bit_field.type).to_s.upcase
+        eval_attribute(:access, bit_field.type).to_s.upcase
       end
 
       def model_name
-        name = helper.model_name
-        name.is_a?(Proc) && instance_eval(&name) || name || 'rggen_ral_field'
+        eval_attribute(:model_name, 'rggen_ral_field')
       end
 
       def constructors
@@ -73,6 +81,11 @@ RgGen.define_list_feature(:bit_field, :type) do
           ''
         end
       end
+
+      def eval_attribute(attribute, default_value)
+        value = helper.__send__(attribute)
+        value.is_a?(Proc) && instance_eval(&value) || value || default_value
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -9,7 +9,7 @@ module RgGen
         def array_indices
           if component.array?
             index_table = component.array_size.map { |size| (0...size).to_a }
-            index_table[0].product(*index_table[1..-1])
+            index_table[0].product(*index_table[1..])
           else
             [nil]
           end

data/lib/rggen/systemverilog/ral.rb

@@ -4,33 +4,30 @@ require_relative 'common'
 require_relative 'ral/feature'
 require_relative 'ral/register_common'
 
-module RgGen
-  module SystemVerilog
-    module RAL
-      extend Core::Plugin
+RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
+  plugin.version RgGen::SystemVerilog::VERSION
 
-      setup_plugin :'rggen-sv-ral' do |plugin|
-        plugin.version SystemVerilog::VERSION
-
-        plugin.register_component :sv_ral do
-          component Common::Component, Common::ComponentFactory
-          feature Feature, Common::FeatureFactory
-        end
-
-        plugin.files [
-          'ral/bit_field/type',
-          'ral/bit_field/type/rof',
-          'ral/bit_field/type/rwc_rws',
-          'ral/bit_field/type/rwe_rwl',
-          'ral/bit_field/type/w0trg_w1trg',
-          'ral/register/type',
-          'ral/register/type/external',
-          'ral/register/type/indirect',
-          'ral/register_block/sv_ral_model',
-          'ral/register_block/sv_ral_package',
-          'ral/register_file/sv_ral_model'
-        ]
-      end
-    end
+  plugin.register_component :sv_ral do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RAL::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
   end
+
+  plugin.files [
+    'ral/register_block/sv_ral_package',
+    'ral/register_block/sv_ral_model',
+    'ral/register_file/sv_ral_model',
+    'ral/register/type',
+    'ral/register/type/external',
+    'ral/register/type/indirect',
+    'ral/bit_field/type',
+    'ral/bit_field/type/rof',
+    'ral/bit_field/type/rotrg_rwtrg_wotrg',
+    'ral/bit_field/type/row0trg_row1trg',
+    'ral/bit_field/type/rowo_rowotrg',
+    'ral/bit_field/type/rwc_rws',
+    'ral/bit_field/type/rwe_rwl',
+    'ral/bit_field/type/w0trg_w1trg'
+  ]
 end

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -36,10 +36,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       end
     end
 
-    pre_code :bit_field do |code|
-      code << bit_field_if_connection << nl
-    end
-
     def value(offsets = nil, width = nil)
       value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
@@ -113,17 +109,5 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     def body_code(code)
       bit_field.generate_code(code, :bit_field, :top_down)
     end
-
-    def bit_field_if_connection
-      macro_call(
-        'rggen_connect_bit_field_if',
-        [
-          register.bit_field_if,
-          bit_field.bit_field_sub_if,
-          bit_field.lsb(local_index),
-          bit_field.width
-        ]
-      )
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb}

@@ -1,10 +1,14 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
 ) u_bit_field (
-  .i_clk              ('0),
-  .i_rst_n            ('0),
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rotrg?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rotrg?
+      bit_field.type == :rotrg
+    end
+
+    def trigger
+      rotrg? && 1 || 0
+    end
+
+    def read_trigger_signal
+      rotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,10 +1,13 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1)
 ) u_bit_field (
   .i_clk              ('0),
   .i_rst_n            ('0),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_value      (<%= reference_or_value_in %>),
+  .o_trigger    (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.rb → row0trg_row1trg.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
   sv_rtl do
     build do
       unless bit_field.reference?
@@ -9,14 +9,22 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
           array_size: array_size, array_format: array_port_format
         }
       end
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
     end
 
     main_code :bit_field, from_template: true
 
     private
 
+    def trigger_value
+      bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
+    end
+
     def reference_or_value_in
-      bit_field.reference? && reference_bit_field || value_in[loop_variables]
+      reference_bit_field || value_in[loop_variables]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb

@@ -0,0 +1,21 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rowotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rowotrg?
+      bit_field.type == :rowotrg
+    end
+
+    def trigger
+      rowotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rowotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rowotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb}

@@ -1,12 +1,14 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .SW_READ_ACTION (<%= read_action %>),
-  .SW_WRITE_ONCE  (<%= write_once %>)
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def trigger
+      rwtrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :w1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= control_signal %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -5,6 +5,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  (<%= set_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb

@@ -5,5 +5,6 @@ rggen_bit_field_w01trg #(
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),
   .bit_field_if (<%= bit_field_if %>),
+  .i_value      ('0),
   .o_trigger    (<%= trigger[loop_variables] %>)
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb

@@ -0,0 +1,22 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (RGGEN_READ_NONE),
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def trigger
+      wotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :wo1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),