rggen-systemverilog 0.25.1 → 0.27.0

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_feature(:bit_field, :type) do
   sv_rtl do
     base_feature do
+      pre_code :bit_field do |code|
+        code << bit_field_if_connection << nl
+      end
+
       private
 
       def array_port_format
@@ -17,6 +21,10 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.width
       end
 
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
       def clock
         register_block.clock
       end
@@ -52,6 +60,13 @@ RgGen.define_list_feature(:bit_field, :type) do
       def loop_variables
         bit_field.loop_variables
       end
+
+      def bit_field_if_connection
+        macro_call(
+          'rggen_connect_bit_field_if',
+          [register.bit_field_if, bit_field_if, lsb, width]
+        )
+      end
     end
 
     factory do

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -5,7 +5,6 @@ rggen_default_register #(
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -3,63 +3,14 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :bus_if, {
-          name: "#{register.name}_bus_if",
-          interface_type: 'rggen_bus_if',
-          modport: 'master'
-        }
-      else
-        output :valid, {
-          name: "o_#{register.name}_valid", width: 1
-        }
-        output :access, {
-          name: "o_#{register.name}_access", width: '$bits(rggen_access)'
-        }
-        output :address, {
-          name: "o_#{register.name}_address", width: address_width
-        }
-        output :write_data, {
-          name: "o_#{register.name}_data", width: bus_width
-        }
-        output :strobe, {
-          name: "o_#{register.name}_strobe", width: byte_width
-        }
-        input :ready, {
-          name: "i_#{register.name}_ready", width: 1
-        }
-        input :status, {
-          name: "i_#{register.name}_status", width: 2
-        }
-        input :read_data, {
-          name: "i_#{register.name}_data", width: bus_width
-        }
-        interface :bus_if, {
-          name: 'bus_if', interface_type: 'rggen_bus_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'valid', 'access', 'address', 'write_data', 'strobe',
-            'ready', 'status', 'read_data'
-          ]
-        }
-      end
+      interface_port :bus_if, {
+        name: "#{register.name}_bus_if",
+        interface_type: 'rggen_bus_if',
+        modport: 'master'
+      }
     end
 
     main_code :register, from_template: true
-    main_code :register do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [valid, bus_if.valid],
-          [access, bus_if.access],
-          [address, bus_if.address],
-          [write_data, bus_if.write_data],
-          [strobe, bus_if.strobe],
-          [bus_if.ready, ready],
-          [bus_if.status, "rggen_status'(#{status})"],
-          [bus_if.read_data, read_data]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
 
     private
 

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -5,7 +5,6 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << tie_off_unused_signals << nl)
+      end
+
       private
 
       def register_if
@@ -14,6 +19,13 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_if
         register.bit_field_if
       end
+
+      def tie_off_unused_signals
+        macro_call(
+          'rggen_tie_off_unused_signals',
+          [width, valid_bits, bit_field_if]
+        )
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -21,68 +21,11 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
 
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
-        }
-      else
-        input :psel, {
-          name: 'i_psel', width: 1
-        }
-        input :penable, {
-          name: 'i_penable', width: 1
-        }
-        input :paddr, {
-          name: 'i_paddr', width: address_width
-        }
-        input :pprot, {
-          name: 'i_pprot', width: 3
-        }
-        input :pwrite, {
-          name: 'i_pwrite', width: 1
-        }
-        input :pstrb, {
-          name: 'i_pstrb', width: byte_width
-        }
-        input :pwdata, {
-          name: 'i_pwdata', width: bus_width
-        }
-        output :pready, {
-          name: 'o_pready', width: 1
-        }
-        output :prdata, {
-          name: 'o_prdata', width: bus_width
-        }
-        output :pslverr, {
-          name: 'o_pslverr', width: 1
-        }
-        interface :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
-            'pready', 'prdata', 'pslverr'
-          ]
-        }
-      end
+      interface_port :apb_if, {
+        name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [apb_if.psel, psel],
-          [apb_if.penable, penable],
-          [apb_if.paddr, paddr],
-          [apb_if.pprot, pprot],
-          [apb_if.pwrite, pwrite],
-          [apb_if.pstrb, pstrb],
-          [apb_if.pwdata, pwdata],
-          [pready, apb_if.pready],
-          [prdata, apb_if.prdata],
-          [pslverr, apb_if.pslverr]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -19,132 +19,18 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
-      if configuration.fold_sv_interface_port?
-        interface_port :axi4lite_if, {
-          name: 'axi4lite_if',
-          interface_type: 'rggen_axi4lite_if', modport: 'slave'
-        }
-      else
-        input :awvalid, {
-          name: 'i_awvalid', width: 1
-        }
-        output :awready, {
-          name: 'o_awready', width: 1
-        }
-        input :awid, {
-          name: 'i_awid', width: id_port_width
-        }
-        input :awaddr, {
-          name: 'i_awaddr', width: address_width
-        }
-        input :awprot, {
-          name: 'i_awprot', width: 3
-        }
-        input :wvalid, {
-          name: 'i_wvalid', width: 1
-        }
-        output :wready, {
-          name: 'o_wready', width: 1
-        }
-        input :wdata, {
-          name: 'i_wdata', width: bus_width
-        }
-        input :wstrb, {
-          name: 'i_wstrb', width: byte_width
-        }
-        output :bvalid, {
-          name: 'o_bvalid', width: 1
-        }
-        output :bid, {
-          name: 'o_bid', width: id_port_width
-        }
-        input :bready, {
-          name: 'i_bready', width: 1
-        }
-        output :bresp, {
-          name: 'o_bresp', width: 2
-        }
-        input :arvalid, {
-          name: 'i_arvalid', width: 1
-        }
-        output :arready, {
-          name: 'o_arready', width: 1
-        }
-        input :arid, {
-          name: 'i_arid', width: id_port_width
-        }
-        input :araddr, {
-          name: 'i_araddr', width: address_width
-        }
-        input :arprot, {
-          name: 'i_arprot', width: 3
-        }
-        output :rvalid, {
-          name: 'o_rvalid', width: 1
-        }
-        input :rready, {
-          name: 'i_rready', width: 1
-        }
-        output :rid, {
-          name: 'o_rid', width: id_port_width
-        }
-        output :rdata, {
-          name: 'o_rdata', width: bus_width
-        }
-        output :rresp, {
-          name: 'o_rresp', width: 2
-        }
-        interface :axi4lite_if, {
-          name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [id_width, address_width, bus_width],
-          variables: [
-            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
-            'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bid', 'bresp',
-            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
-          ]
-        }
-      end
+      interface_port :axi4lite_if, {
+        name: 'axi4lite_if',
+        interface_type: 'rggen_axi4lite_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
-    end
 
     private
 
     def id_port_width
       "((#{id_width}>0)?#{id_width}:1)"
     end
-
-    def assign_axi4lite_signals(code)
-      [
-        [axi4lite_if.awvalid, awvalid],
-        [awready, axi4lite_if.awready],
-        [axi4lite_if.awid, awid],
-        [axi4lite_if.awaddr, awaddr],
-        [axi4lite_if.awprot, awprot],
-        [axi4lite_if.wvalid, wvalid],
-        [wready, axi4lite_if.wready],
-        [axi4lite_if.wdata, wdata],
-        [axi4lite_if.wstrb, wstrb],
-        [bvalid, axi4lite_if.bvalid],
-        [axi4lite_if.bready, bready],
-        [bid, axi4lite_if.bid],
-        [bresp, axi4lite_if.bresp],
-        [axi4lite_if.arvalid, arvalid],
-        [arready, axi4lite_if.arready],
-        [axi4lite_if.arid, arid],
-        [axi4lite_if.araddr, araddr],
-        [axi4lite_if.arprot, arprot],
-        [rvalid, axi4lite_if.rvalid],
-        [axi4lite_if.rready, rready],
-        [rid, axi4lite_if.rid],
-        [rdata, axi4lite_if.rdata],
-        [rresp, axi4lite_if.rresp]
-      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb

@@ -0,0 +1,17 @@
+rggen_wishbone_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .USE_STALL            (<%= use_stall %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .wishbone_if  (<%= wishbone_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  configuration do
+    verify(:component) do
+      error_condition { configuration.bus_width > 64 }
+      message do
+        'bus width over 64 bit is not supported: ' \
+        "#{configuration.bus_width}"
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      parameter :use_stall, {
+        name: 'USE_STALL', data_type: :bit, default: 1
+      }
+      interface_port :wishbone_if, {
+        name: 'wishbone_if', interface_type: 'rggen_wishbone_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -8,7 +8,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     def available_protocols
       feature_registries
-        .map(&method(:collect_available_protocols)).inject(:&)
+        .map { |registry| registry.enabled_features(:protocol) }
+        .inject(:&)
     end
 
     private

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -7,3 +7,15 @@
   assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
   assign  RIF.value[LSB+:WIDTH]     = FIF.value;
 `endif
+`ifndef rggen_tie_off_unused_signals
+  `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
+  if (1) begin : __g_tie_off \
+    genvar  __i; \
+    for (__i = 0;__i < WIDTH;++__i) begin : g \
+      if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
+        assign  RIF.read_data[__i]  = 1'b0; \
+        assign  RIF.value[__i]      = 1'b0; \
+      end \
+    end \
+  end
+`endif

data/lib/rggen/systemverilog/rtl.rb

@@ -8,47 +8,44 @@ require_relative 'rtl/register_type'
 require_relative 'rtl/indirect_index'
 require_relative 'rtl/bit_field_index'
 
-module RgGen
-  module SystemVerilog
-    module RTL
-      extend Core::Plugin
+RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
+  plugin.version RgGen::SystemVerilog::VERSION
 
-      setup_plugin :'rggen-sv-rtl' do |plugin|
-        plugin.version SystemVerilog::VERSION
-
-        plugin.register_component :sv_rtl do
-          component Common::Component, Common::ComponentFactory
-          feature Feature, Common::FeatureFactory
-        end
-
-        plugin.files [
-          'rtl/bit_field/sv_rtl_top',
-          'rtl/bit_field/type',
-          'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-          'rtl/bit_field/type/ro',
-          'rtl/bit_field/type/rof',
-          'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
-          'rtl/bit_field/type/rw_w1_wo_wo1',
-          'rtl/bit_field/type/rwc',
-          'rtl/bit_field/type/rwe_rwl',
-          'rtl/bit_field/type/rws',
-          'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
-          'rtl/bit_field/type/w0t_w1t',
-          'rtl/bit_field/type/w0trg_w1trg',
-          'rtl/bit_field/type/wrc_wrs',
-          'rtl/global/array_port_format',
-          'rtl/global/fold_sv_interface_port',
-          'rtl/register/sv_rtl_top',
-          'rtl/register/type',
-          'rtl/register/type/external',
-          'rtl/register/type/indirect',
-          'rtl/register_block/protocol',
-          'rtl/register_block/protocol/apb',
-          'rtl/register_block/protocol/axi4lite',
-          'rtl/register_block/sv_rtl_top',
-          'rtl/register_file/sv_rtl_top'
-        ]
-      end
-    end
+  plugin.register_component :sv_rtl do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RTL::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
   end
+
+  plugin.files [
+    'rtl/global/array_port_format',
+    'rtl/register_block/sv_rtl_top',
+    'rtl/register_block/protocol',
+    'rtl/register_block/protocol/apb',
+    'rtl/register_block/protocol/axi4lite',
+    'rtl/register_block/protocol/wishbone',
+    'rtl/register_file/sv_rtl_top',
+    'rtl/register/sv_rtl_top',
+    'rtl/register/type',
+    'rtl/register/type/external',
+    'rtl/register/type/indirect',
+    'rtl/bit_field/sv_rtl_top',
+    'rtl/bit_field/type',
+    'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+    'rtl/bit_field/type/ro_rotrg',
+    'rtl/bit_field/type/rof',
+    'rtl/bit_field/type/row0trg_row1trg',
+    'rtl/bit_field/type/rowo_rowotrg',
+    'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+    'rtl/bit_field/type/rw_rwtrg_w1',
+    'rtl/bit_field/type/rwc',
+    'rtl/bit_field/type/rwe_rwl',
+    'rtl/bit_field/type/rws',
+    'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'rtl/bit_field/type/w0t_w1t',
+    'rtl/bit_field/type/w0trg_w1trg',
+    'rtl/bit_field/type/wo_wo1_wotrg',
+    'rtl/bit_field/type/wrc_wrs'
+  ]
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.25.1'
+    VERSION = '0.27.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.25.1
+  version: 0.27.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-16 00:00:00.000000000 Z
+date: 2022-07-05 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -56,6 +56,9 @@ files:
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
+- lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
@@ -71,20 +74,23 @@ files:
 - lib/rggen/systemverilog/ral/register_common.rb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
-- lib/rggen/systemverilog/ral/setup.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
@@ -97,12 +103,13 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
-- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
 - lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -117,19 +124,21 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/register_type.rb
-- lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
 licenses:
 - MIT
 metadata:
-  bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -140,15 +149,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.5'
+      version: '2.6'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.25.1
+summary: rggen-systemverilog-0.27.0
 test_files: []

data/lib/rggen/systemverilog/ral/setup.rb

@@ -1,8 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/systemverilog/ral'
-
-RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
-  builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
-  builder.enable :register_file, [:sv_ral_model]
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
-  sv_rtl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def read_action
-      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
-    end
-
-    def write_once
-      [:w1, :wo1].include?(bit_field.type) && 1 || 0
-    end
-  end
-end