rggen-systemverilog 0.16.0 → 0.21.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +13 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +8 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +21 -17
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +92 -16
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +3 -6
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +24 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +13 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +24 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +10 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -9
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +0 -14
@@ -8,6 +8,7 @@ RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
|
|
8
8
|
]
|
9
9
|
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
10
10
|
builder.enable :register_block, :protocol, [:apb, :axi4lite]
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11
|
+
builder.enable :register_file, [:sv_rtl_top]
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11
12
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builder.enable :register, [:sv_rtl_top]
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12
13
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builder.enable :bit_field, [:sv_rtl_top]
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13
14
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end
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metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
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name: rggen-systemverilog
|
3
3
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version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.21.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
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- Taichi Ishitani
|
8
8
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autorequire:
|
9
9
|
bindir: bin
|
10
10
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cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2020-07-22 00:00:00.000000000 Z
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12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: docile
|
@@ -54,7 +54,7 @@ dependencies:
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|
54
54
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version: '0'
|
55
55
|
description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
|
56
56
|
|
57
|
-
'
|
57
|
+
'
|
58
58
|
email:
|
59
59
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- rggen@googlegroups.com
|
60
60
|
executables: []
|
@@ -93,8 +93,12 @@ files:
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|
93
93
|
- lib/rggen/systemverilog/ral/register/type/external.rb
|
94
94
|
- lib/rggen/systemverilog/ral/register/type/indirect.erb
|
95
95
|
- lib/rggen/systemverilog/ral/register/type/indirect.rb
|
96
|
-
- lib/rggen/systemverilog/ral/register_block/
|
96
|
+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
|
97
|
+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
|
97
98
|
- lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
|
99
|
+
- lib/rggen/systemverilog/ral/register_common.rb
|
100
|
+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
|
101
|
+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
|
98
102
|
- lib/rggen/systemverilog/ral/setup.rb
|
99
103
|
- lib/rggen/systemverilog/rtl.rb
|
100
104
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- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
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@@ -109,8 +113,8 @@ files:
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109
113
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
110
114
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- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
|
111
115
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
|
112
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
113
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
116
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
|
117
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
|
114
118
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
|
115
119
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
|
116
120
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
|
@@ -128,6 +132,7 @@ files:
|
|
128
132
|
- lib/rggen/systemverilog/rtl/feature.rb
|
129
133
|
- lib/rggen/systemverilog/rtl/global/array_port_format.rb
|
130
134
|
- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
|
135
|
+
- lib/rggen/systemverilog/rtl/partial_sum.rb
|
131
136
|
- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
|
132
137
|
- lib/rggen/systemverilog/rtl/register/type.rb
|
133
138
|
- lib/rggen/systemverilog/rtl/register/type/default.erb
|
@@ -142,6 +147,8 @@ files:
|
|
142
147
|
- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
|
143
148
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
|
144
149
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
|
150
|
+
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
151
|
+
- lib/rggen/systemverilog/rtl/register_index.rb
|
145
152
|
- lib/rggen/systemverilog/rtl/setup.rb
|
146
153
|
- lib/rggen/systemverilog/version.rb
|
147
154
|
homepage: https://github.com/rggen/rggen-systemverilog
|
@@ -160,15 +167,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
160
167
|
requirements:
|
161
168
|
- - ">="
|
162
169
|
- !ruby/object:Gem::Version
|
163
|
-
version: '2.
|
170
|
+
version: '2.4'
|
164
171
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
165
172
|
requirements:
|
166
173
|
- - ">="
|
167
174
|
- !ruby/object:Gem::Version
|
168
175
|
version: '0'
|
169
176
|
requirements: []
|
170
|
-
rubygems_version: 3.
|
177
|
+
rubygems_version: 3.1.2
|
171
178
|
signing_key:
|
172
179
|
specification_version: 4
|
173
|
-
summary: rggen-systemverilog-0.
|
180
|
+
summary: rggen-systemverilog-0.21.0
|
174
181
|
test_files: []
|
@@ -1,11 +0,0 @@
|
|
1
|
-
function new(string name);
|
2
|
-
super.new(name);
|
3
|
-
endfunction
|
4
|
-
function void build();
|
5
|
-
<% reg_model_constructors.each do |constructor| %>
|
6
|
-
<%= constructor %>
|
7
|
-
<% end %>
|
8
|
-
endfunction
|
9
|
-
function uvm_reg_map create_default_map();
|
10
|
-
return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
|
11
|
-
endfunction
|
@@ -1,14 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
output :register_block, :value_out, {
|
7
|
-
name: "o_#{full_name}", data_type: :logic, width: width,
|
8
|
-
array_size: array_size, array_format: array_port_format
|
9
|
-
}
|
10
|
-
end
|
11
|
-
|
12
|
-
main_code :bit_field, from_template: true
|
13
|
-
end
|
14
|
-
end
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