rggen-systemverilog 0.16.0 → 0.21.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +13 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +8 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +21 -17
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +92 -16
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +3 -6
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +24 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +13 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +24 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +10 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -9
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +0 -14
@@ -3,6 +3,8 @@
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RgGen.define_list_feature(:register, :type) do
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sv_ral do
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base_feature do
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+
include RgGen::SystemVerilog::RAL::RegisterCommon
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+
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define_helpers do
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def model_name(&body)
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@model_name = body if block_given?
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@@ -14,14 +16,6 @@ RgGen.define_list_feature(:register, :type) do
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@offset_address
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end
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def unmapped
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@unmapped = true
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end
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def unmapped?
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!@unmapped.nil?
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-
end
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-
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def constructor(&body)
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@constructor = body if block_given?
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@constructor
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@@ -31,18 +25,14 @@ RgGen.define_list_feature(:register, :type) do
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export :constructors
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build do
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variable :
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name: register.name,
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-
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array_size: register.array_size,
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random: true
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variable :ral_model, {
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name: register.name, data_type: model_name,
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array_size: register.array_size, random: true
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}
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end
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def constructors
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-
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constructor_code(array_index, i)
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-
end
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array_indices.map.with_index(&method(:constructor_code))
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end
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private
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@@ -51,45 +41,25 @@ RgGen.define_list_feature(:register, :type) do
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if helper.model_name
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instance_eval(&helper.model_name)
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else
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"#{register.
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"#{register.full_name('_')}_reg_model"
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end
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end
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def array_index_list
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(register.array? || nil) &&
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begin
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index_table = register.array_size.map { |size| (0...size).to_a }
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index_table[0].product(*index_table[1..-1])
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end
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end
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-
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def constructor_code(array_index, index)
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if helper.constructor
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instance_exec(array_index, index, &helper.constructor)
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else
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macro_call(
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:rggen_ral_create_reg_model, arguments(array_index, index)
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)
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macro_call(:rggen_ral_create_reg, arguments(array_index, index))
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end
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end
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def arguments(array_index, index)
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[
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ral_model[array_index], array(array_index), offset_address(index),
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access_rights,
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string(access_rights), string(hdl_path(array_index))
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]
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end
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def offset_address(index = 0)
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address =
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if helper.offset_address
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instance_exec(index, &helper.offset_address)
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else
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register.offset_address + register.byte_width * index
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end
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hex(address, register_block.local_address_width)
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end
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-
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def access_rights
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if read_only?
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'RO'
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@@ -108,20 +78,8 @@ RgGen.define_list_feature(:register, :type) do
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register.writable? && !register.readable?
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end
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80
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def unmapped
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helper.unmapped? && 1 || 0
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-
end
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-
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def hdl_path(array_index)
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[
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"g_#{register.name}",
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*Array(array_index).map { |i| "g[#{i}]" },
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'u_register'
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].join('.')
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-
end
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-
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def variables
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register.declarations
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register.declarations[:variable]
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end
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def field_model_constructors
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@@ -3,15 +3,11 @@
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RgGen.define_list_item_feature(:register, :type, :external) do
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sv_ral do
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build do
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parameter :
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name: model_name,
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data_type: 'type',
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default: 'rggen_ral_block'
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parameter :model_type, {
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name: model_name, data_type: 'type', default: 'rggen_ral_block'
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}
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parameter :
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name: "INTEGRATE_#{model_name}",
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data_type: 'bit',
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default: 1
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parameter :integrate_model, {
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name: "INTEGRATE_#{model_name}", data_type: 'bit', default: 1
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}
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end
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@@ -19,8 +15,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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constructor do
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macro_call(
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'
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[ral_model, offset_address, 'this', integrate_model]
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'rggen_ral_create_block',
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[ral_model, offset_address(0), 'this', integrate_model]
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)
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end
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end
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@@ -4,10 +4,10 @@ endfunction
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function void build();
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<% field_model_constructors.each do |constructor| %>
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<%= constructor %>
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<% end%>
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<% end %>
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endfunction
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function void setup_index_fields();
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<% index_properties.each do |
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setup_index_field("<%=
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<% index_properties.each do |field_name, value| %>
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setup_index_field("<%= field_name %>", <%= value %>);
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<% end %>
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endfunction
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@@ -2,7 +2,6 @@
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RgGen.define_list_item_feature(:register, :type, :indirect) do
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sv_ral do
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unmapped
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offset_address { register.offset_address }
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main_code :ral_package do
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@@ -24,12 +23,16 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
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else
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"array_index[#{array_position += 1}]"
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end
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[field
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[field_full_name(field), value]
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end
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end
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def index_fields
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register.collect_index_fields(register_block.bit_fields)
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end
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+
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def field_full_name(field)
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[field.register.full_name('.'), field.name].join('.')
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end
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end
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end
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@@ -0,0 +1,36 @@
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# frozen_string_literal: true
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RgGen.define_simple_feature(:register_block, :sv_ral_model) do
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sv_ral do
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main_code :ral_package do
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class_definition(model_name) do |sv_class|
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sv_class.base 'rggen_ral_block'
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sv_class.parameters parameters
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sv_class.variables variables
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sv_class.body { process_template }
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end
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end
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private
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def model_name
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"#{register_block.name}_block_model"
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end
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def parameters
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register_block.declarations[:parameter]
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end
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def variables
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register_block.declarations[:variable]
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end
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+
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def byte_width
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configuration.byte_width
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end
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def child_model_constructors
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register_block.children.flat_map(&:constructors)
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end
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end
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end
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@@ -8,23 +8,12 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
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package.package_imports packages
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package.include_files include_files
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package.body do |code|
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register_block.generate_code(:ral_package, :bottom_up
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register_block.generate_code(code, :ral_package, :bottom_up)
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end
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end
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end
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end
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main_code :ral_package do
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class_definition(model_name) do |sv_class|
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sv_class.base 'rggen_ral_block'
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sv_class.parameters parameters
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sv_class.variables variables
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sv_class.body do
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process_template(File.join(__dir__, 'sv_ral_block_model.erb'))
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end
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end
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end
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-
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private
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def package_name
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@@ -41,25 +30,5 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
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41
30
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def include_files
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['uvm_macros.svh', 'rggen_ral_macros.svh']
|
43
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end
|
44
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-
|
45
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-
def model_name
|
46
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"#{register_block.name}_block_model"
|
47
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-
end
|
48
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-
|
49
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def parameters
|
50
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register_block.declarations(:register_block, :parameter)
|
51
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-
end
|
52
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-
|
53
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def variables
|
54
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register_block.declarations(:register_block, :variable)
|
55
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-
end
|
56
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-
|
57
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def reg_model_constructors
|
58
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register_block.registers.flat_map(&:constructors)
|
59
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-
end
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60
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-
|
61
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def byte_width
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configuration.byte_width
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-
end
|
64
33
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end
|
65
34
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end
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@@ -0,0 +1,46 @@
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1
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+
# frozen_string_literal: true
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2
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+
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3
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+
module RgGen
|
4
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+
module SystemVerilog
|
5
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+
module RAL
|
6
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+
module RegisterCommon
|
7
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+
private
|
8
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+
|
9
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+
def array_indices
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10
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+
if component.array?
|
11
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+
index_table = component.array_size.map { |size| (0...size).to_a }
|
12
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+
index_table[0].product(*index_table[1..-1])
|
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+
else
|
14
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[nil]
|
15
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+
end
|
16
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+
end
|
17
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+
|
18
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+
def offset_address(index)
|
19
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+
address =
|
20
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+
if register? && helper.offset_address
|
21
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+
instance_exec(index, &helper.offset_address)
|
22
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+
else
|
23
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+
default_offset_address(index)
|
24
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+
end
|
25
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+
hex(address, register_block.local_address_width)
|
26
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+
end
|
27
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+
|
28
|
+
def default_offset_address(index)
|
29
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+
component.offset_address + component.byte_size(false) * index
|
30
|
+
end
|
31
|
+
|
32
|
+
def hdl_path(array_index)
|
33
|
+
[
|
34
|
+
"g_#{component.name}",
|
35
|
+
*Array(array_index).map { |i| "g[#{i}]" },
|
36
|
+
*unit_instance_name
|
37
|
+
].join('.')
|
38
|
+
end
|
39
|
+
|
40
|
+
def unit_instance_name
|
41
|
+
register? && 'u_register' || nil
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
45
|
+
end
|
46
|
+
end
|
@@ -0,0 +1,57 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register_file, :sv_ral_model) do
|
4
|
+
sv_ral do
|
5
|
+
include RgGen::SystemVerilog::RAL::RegisterCommon
|
6
|
+
|
7
|
+
export :constructors
|
8
|
+
|
9
|
+
build do
|
10
|
+
variable :ral_model, {
|
11
|
+
name: register_file.name, data_type: model_name,
|
12
|
+
array_size: register_file.array_size, random: true
|
13
|
+
}
|
14
|
+
end
|
15
|
+
|
16
|
+
def constructors
|
17
|
+
array_indices.map.with_index(&method(:constructor_code))
|
18
|
+
end
|
19
|
+
|
20
|
+
main_code :ral_package do
|
21
|
+
class_definition(model_name) do |sv_class|
|
22
|
+
sv_class.base 'rggen_ral_reg_file'
|
23
|
+
sv_class.variables variables
|
24
|
+
sv_class.body { process_template }
|
25
|
+
end
|
26
|
+
end
|
27
|
+
|
28
|
+
private
|
29
|
+
|
30
|
+
def model_name
|
31
|
+
"#{register_file.full_name('_')}_reg_file_model"
|
32
|
+
end
|
33
|
+
|
34
|
+
def constructor_code(array_index, index)
|
35
|
+
macro_call(:rggen_ral_create_reg_file, arguments(array_index, index))
|
36
|
+
end
|
37
|
+
|
38
|
+
def arguments(array_index, index)
|
39
|
+
[
|
40
|
+
ral_model[array_index], array(array_index), offset_address(index),
|
41
|
+
string(hdl_path(array_index))
|
42
|
+
]
|
43
|
+
end
|
44
|
+
|
45
|
+
def variables
|
46
|
+
register_file.declarations[:variable]
|
47
|
+
end
|
48
|
+
|
49
|
+
def byte_width
|
50
|
+
configuration.byte_width
|
51
|
+
end
|
52
|
+
|
53
|
+
def child_model_constructors
|
54
|
+
register_file.children.flat_map(&:constructors)
|
55
|
+
end
|
56
|
+
end
|
57
|
+
end
|
@@ -3,5 +3,6 @@
|
|
3
3
|
require 'rggen/systemverilog/ral'
|
4
4
|
|
5
5
|
RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
|
6
|
-
builder.enable :register_block, [:sv_ral_package]
|
6
|
+
builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
|
7
|
+
builder.enable :register_file, [:sv_ral_model]
|
7
8
|
end
|
@@ -2,6 +2,8 @@
|
|
2
2
|
|
3
3
|
require_relative 'common'
|
4
4
|
require_relative 'rtl/feature'
|
5
|
+
require_relative 'rtl/partial_sum'
|
6
|
+
require_relative 'rtl/register_index'
|
5
7
|
|
6
8
|
module RgGen
|
7
9
|
module SystemVerilog
|
@@ -14,7 +16,7 @@ module RgGen
|
|
14
16
|
'rtl/bit_field/type/ro',
|
15
17
|
'rtl/bit_field/type/rof',
|
16
18
|
'rtl/bit_field/type/rs_w0s_w1s',
|
17
|
-
'rtl/bit_field/type/
|
19
|
+
'rtl/bit_field/type/rw_w1_wo_wo1',
|
18
20
|
'rtl/bit_field/type/rwc',
|
19
21
|
'rtl/bit_field/type/rwe',
|
20
22
|
'rtl/bit_field/type/rwl',
|
@@ -31,7 +33,8 @@ module RgGen
|
|
31
33
|
'rtl/register_block/protocol',
|
32
34
|
'rtl/register_block/protocol/apb',
|
33
35
|
'rtl/register_block/protocol/axi4lite',
|
34
|
-
'rtl/register_block/sv_rtl_top'
|
36
|
+
'rtl/register_block/sv_rtl_top',
|
37
|
+
'rtl/register_file/sv_rtl_top'
|
35
38
|
].freeze
|
36
39
|
|
37
40
|
def self.version
|
@@ -3,12 +3,26 @@
|
|
3
3
|
RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
4
4
|
sv_rtl do
|
5
5
|
export :local_index
|
6
|
+
export :local_indices
|
6
7
|
export :loop_variables
|
7
8
|
export :array_size
|
8
9
|
export :value
|
9
10
|
|
10
11
|
build do
|
11
|
-
|
12
|
+
if fixed_initial_value?
|
13
|
+
localparam :initial_value, {
|
14
|
+
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
15
|
+
array_size: initial_value_size, array_format: initial_value_format,
|
16
|
+
default: initial_value_lhs
|
17
|
+
}
|
18
|
+
elsif initial_value?
|
19
|
+
parameter :initial_value, {
|
20
|
+
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
21
|
+
array_size: initial_value_size, array_format: initial_value_format,
|
22
|
+
default: initial_value_lhs
|
23
|
+
}
|
24
|
+
end
|
25
|
+
interface :bit_field_sub_if, {
|
12
26
|
name: 'bit_field_sub_if',
|
13
27
|
interface_type: 'rggen_bit_field_if',
|
14
28
|
parameter_values: [bit_field.width]
|
@@ -18,6 +32,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
18
32
|
main_code :register do
|
19
33
|
local_scope("g_#{bit_field.name}") do |scope|
|
20
34
|
scope.loop_size loop_size
|
35
|
+
scope.parameters parameters
|
21
36
|
scope.variables variables
|
22
37
|
scope.body(&method(:body_code))
|
23
38
|
end
|
@@ -28,13 +43,12 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
28
43
|
end
|
29
44
|
|
30
45
|
def local_index
|
31
|
-
(
|
46
|
+
(index_name = local_index_name) &&
|
32
47
|
create_identifier(index_name)
|
33
48
|
end
|
34
49
|
|
35
|
-
def
|
36
|
-
|
37
|
-
loop_index(depth)
|
50
|
+
def local_indices
|
51
|
+
[*register.local_indices, local_index_name]
|
38
52
|
end
|
39
53
|
|
40
54
|
def loop_variables
|
@@ -44,34 +58,96 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
44
58
|
|
45
59
|
def array_size
|
46
60
|
(inside_loop? || nil) &&
|
47
|
-
[
|
61
|
+
[
|
62
|
+
*register_files.flat_map(&:array_size),
|
63
|
+
*register.array_size,
|
64
|
+
*bit_field.sequence_size
|
65
|
+
].compact
|
48
66
|
end
|
49
67
|
|
50
|
-
def value(
|
51
|
-
|
52
|
-
width
|
53
|
-
|
54
|
-
.register_if[register.index(register_offset)]
|
55
|
-
.value[bit_field.lsb(bit_field_offset), width]
|
68
|
+
def value(offsets = nil, width = nil)
|
69
|
+
value_lsb = bit_field.lsb(offsets&.last || local_index_name)
|
70
|
+
value_width = width || bit_field.width
|
71
|
+
register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
|
56
72
|
end
|
57
73
|
|
58
74
|
private
|
59
75
|
|
76
|
+
[:fixed_initial_value?, :initial_value_array?, :initial_value?].each do |m|
|
77
|
+
define_method(m) { bit_field.__send__(__method__) }
|
78
|
+
end
|
79
|
+
|
80
|
+
def local_index_name
|
81
|
+
(bit_field.sequential? || nil) &&
|
82
|
+
begin
|
83
|
+
depth = (register.loop_variables&.size || 0) + 1
|
84
|
+
loop_index(depth)
|
85
|
+
end
|
86
|
+
end
|
87
|
+
|
88
|
+
def register_if(offsets)
|
89
|
+
index = register.index(offsets || register.local_indices)
|
90
|
+
register_block.register_if[index]
|
91
|
+
end
|
92
|
+
|
93
|
+
def initial_value_name
|
94
|
+
identifiers = []
|
95
|
+
identifiers << bit_field.full_name('_') unless fixed_initial_value?
|
96
|
+
identifiers << 'initial_value'
|
97
|
+
identifiers.join('_').upcase
|
98
|
+
end
|
99
|
+
|
100
|
+
def initial_value_size
|
101
|
+
initial_value_array? && [bit_field.sequence_size] || nil
|
102
|
+
end
|
103
|
+
|
104
|
+
def initial_value_format
|
105
|
+
fixed_initial_value? && :unpacked ||
|
106
|
+
configuration.array_port_format
|
107
|
+
end
|
108
|
+
|
109
|
+
def initial_value_lhs
|
110
|
+
initial_value_array? && initial_value_array_lhs || sized_initial_value
|
111
|
+
end
|
112
|
+
|
113
|
+
def initial_value_array_lhs
|
114
|
+
if fixed_initial_value?
|
115
|
+
array(sized_initial_values)
|
116
|
+
elsif initial_value_format == :unpacked
|
117
|
+
array(default: sized_initial_value)
|
118
|
+
else
|
119
|
+
repeat(bit_field.sequence_size, sized_initial_value)
|
120
|
+
end
|
121
|
+
end
|
122
|
+
|
123
|
+
def sized_initial_value
|
124
|
+
bit_field.initial_value &&
|
125
|
+
hex(bit_field.initial_value, bit_field.width)
|
126
|
+
end
|
127
|
+
|
128
|
+
def sized_initial_values
|
129
|
+
bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
|
130
|
+
end
|
131
|
+
|
60
132
|
def inside_loop?
|
61
133
|
register.array? || bit_field.sequential?
|
62
134
|
end
|
63
135
|
|
64
136
|
def loop_size
|
65
|
-
(
|
66
|
-
{
|
137
|
+
(loop_variable = local_index_name) &&
|
138
|
+
{ loop_variable => bit_field.sequence_size }
|
139
|
+
end
|
140
|
+
|
141
|
+
def parameters
|
142
|
+
bit_field.declarations[:parameter]
|
67
143
|
end
|
68
144
|
|
69
145
|
def variables
|
70
|
-
bit_field.declarations
|
146
|
+
bit_field.declarations[:variable]
|
71
147
|
end
|
72
148
|
|
73
149
|
def body_code(code)
|
74
|
-
bit_field.generate_code(:bit_field, :top_down
|
150
|
+
bit_field.generate_code(code, :bit_field, :top_down)
|
75
151
|
end
|
76
152
|
|
77
153
|
def bit_field_if_connection
|