origen_sim 0.16.1 → 0.20.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 51be12abd354fc71656f9fd5931460deecd27102072858c29eecac293eb01d1b
-  data.tar.gz: 26a6bccbbf6c72375853bcc8b5ed940e9484754e282b23699aec0c87d0fc4449
+  metadata.gz: 0dc77dd81416662c4ecff9e01c03a7ed7a01cc31d79087ec6c9340cd72e0dd7f
+  data.tar.gz: 223d8e87547338de2ddf5061c5789b2f09c576e4acb448d666d9f4305db6acbe
 SHA512:
-  metadata.gz: 00db8e5cd0f05f678a7acafed75edea1623db71175c40e0b51bdcf5c074a973a88e6ff31b32d7ff005560172bafa9fe6ae7eda78c55cf27d0742cbfae801537d
-  data.tar.gz: 4dcb3cf9b28e516d76270a7d7b3891f141b326b8dc55b3975d740bf5492edafbeca6889a05f07a7a5613c9dbbf01b1b1e01bbbe1bac229a1a053b78b7830a707
+  metadata.gz: f29952826fecf63d1e7c96f96ebee945a0d48685ac21771138ea7c4dca51f0c433e2ea1198c9ea76068fb28528fc3af1320131dca5fb4ef0db8527494f8a7c56
+  data.tar.gz: 00db5869a5ebb43ae9138011ac0c36a649547fb37a9fb86f1b32bdf96588815fb4a11f78c0535b8ab258117011d001dac6030044dff266c6aaf503e5c4be1d12

data/config/application.rb

@@ -36,10 +36,12 @@ class OrigenSimApplication < Origen::Application
         section.page :introduction, heading: "Introduction"
         section.page :howitworks, heading: "How It Works"
         section.page :compiling, heading: "Compiling the DUT"
+        section.page :ams, heading: "AMS Support"
         section.page :environment, heading: "Environment Setup"
         section.page :app, heading: "Application Setup"
         section.page :patterns, heading: "Simulating Patterns"
         section.page :flows, heading: "Simulating Flows"
+        section.page :direct, heading: "Direct DUT Manipulation"
         section.page :log, heading: "Simulator Log Output"
         section.page :artifacts, heading: "Artifacts"
         section.page :debugging, heading: "Debugging"

data/config/commands.rb

@@ -17,33 +17,42 @@ case @command
 # in here or you can require an external file if preferred.
 when "sim:build_example"
   Dir.chdir(Origen.root) do
-    output = `origen sim:build  #{Origen.app.remotes_dir}/example_rtl/dut1/dut1.v`
+    cmd = "origen sim:build  #{Origen.app.remotes_dir}/example_rtl/dut1/stub.v"
+    if ARGV.include?('-e') || ARGV.include?('--environment')
+      index = ARGV.index('-e') || ARGV.index('--environment')
+      ARGV.delete_at(index)
+      Origen.environment.temporary = ARGV.delete_at(index)
+    end
+    cmd += ' ' + ARGV.join(' ') unless ARGV.empty?
+    # Enable wreal pins in the DUT RTL
+    cmd += '  --define ORIGEN_WREAL' if ARGV.include?('--wreal')
+    output = `#{cmd}`
     puts output
     Origen.load_target
     dir = "simulation/default/#{tester.simulator.config[:vendor]}"
-    FileUtils.rm_rf(dir) if File.exist?(dir)
     FileUtils.mkdir_p(dir)
-    case tester.simulator.config[:vendor]
-    when :icarus
-      output =~ /  (cd .*)\n/
-      system $1
-      FileUtils.mv "#{Origen.config.output_directory}/origen.vpi", "simulation/default/icarus"
-      output =~ /\n(.*iverilog .*)\n/
-      system $1
-      FileUtils.mv "origen.vvp", "simulation/default/icarus"
+    Dir.chdir dir do
+      case tester.simulator.config[:vendor]
+      when :icarus
+        output =~ /  (cd .*)\n/
+        system $1.gsub('stub', 'dut1')
+        FileUtils.mv "#{Origen.config.output_directory}/origen.vpi", '.'
+        output =~ /\n(.*iverilog .*)\n/
+        system $1.gsub('stub', 'dut1')
 
-    when :cadence
-      output =~ /\n(.*irun .*)\n/
-      system $1
-      FileUtils.mv "INCA_libs", "simulation/default/cadence"
+      when :cadence
+        output =~ /\n(.*irun .*)\n/
+        system $1.gsub('stub', 'dut1')
 
-    when :synopsys
-      output =~ /\n(.*vcs .*)\n/
-      system $1
-      FileUtils.mv "simv", "simulation/default/synopsys"
-      FileUtils.mv "simv.daidir", "simulation/default/synopsys"
-      FileUtils.rm_rf "csrc"
+      when :synopsys
+        if tester.simulator.config[:verdi]
+          output =~ /\n(.*vcs .*ORIGEN_FSDB.*)\n/
+        else
+          output =~ /\n(.*vcs .*ORIGEN_VPD.*)\n/
+        end
+        system $1.gsub('stub', 'dut1')
 
+      end
     end
 
     puts

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 16
-  BUGFIX = 1
+  MINOR = 20
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/ext/bridge.c

@@ -723,18 +723,25 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
           end_simulation();
           return 0;
         // Peek
-        //   Returns the current value of the given net
+        //   Returns the current value of the given net, the 2nd argument specifies whether to
+        //   return an integer or a float/real value
         //
-        //   9^origen.debug.errors
+        //   9^origen.debug.errors^i
+        //   9^origen.dut.my_real_val^f
         case '9' :
           arg1 = strtok(NULL, "^");
+          arg2 = strtok(NULL, "^");
           handle = vpi_handle_by_name(arg1, NULL);
           if (handle) {
-            //v.format = vpiDecStrVal; // Seems important to set this before get
-            v.format = vpiBinStrVal;
-            vpi_get_value(handle, &v);
-            //DEBUG("%s\n", v.value.str);
-            sprintf(msg, "%s\n", v.value.str);
+            if (*arg2 == 'i') {
+              v.format = vpiBinStrVal;
+              vpi_get_value(handle, &v);
+              sprintf(msg, "%s\n", v.value.str);
+            } else {
+              v.format = vpiRealVal;
+              vpi_get_value(handle, &v);
+              sprintf(msg, "%f\n", v.value.real);
+            }
             client_put(msg);
           } else {
             client_put("FAIL\n");
@@ -751,17 +758,25 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
           vpi_put_value(handle, &v, NULL, vpiNoDelay);
           break;
         // Poke
-        //   Sets the given value on the given net, the number should be
-        //   given as a decimal string
+        //   Sets the given value on the given net, the number should be given
+        //   as a decimal string, an integer or a float, and the 2nd argument specifies
+        //   which has been given
         //
-        //   b^origen.debug.errors^15
+        //   b^origen.debug.errors^i^15
+        //   b^origen.dut.my_real_val^f^1.12
         case 'b' :
           arg1 = strtok(NULL, "^");
           arg2 = strtok(NULL, "^");
+          arg3 = strtok(NULL, "^");
           handle = vpi_handle_by_name(arg1, NULL);
           if (handle) {
-            v.format = vpiDecStrVal;
-            v.value.str = arg2;
+            if (*arg2 == 'i') {
+              v.format = vpiDecStrVal;
+              v.value.str = arg3;
+            } else {
+              v.format = vpiRealVal;
+              v.value.real = strtof(arg3, NULL);
+            }
             vpi_put_value(handle, &v, NULL, vpiNoDelay);
           }
           break;
@@ -917,6 +932,41 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
             match_loop_open = false;
           }
           break;
+        // Force
+        //   Forces the given value on the given net, the number should be given
+        //   as a decimal string, an integer or a float, and the 2nd argument specifies
+        //   which has been given
+        //
+        //   r^origen.dut.some.net^i^1^
+        //   r^origen.dut.some.net^f^1.25
+        case 'r' :
+          arg1 = strtok(NULL, "^");
+          arg2 = strtok(NULL, "^");
+          arg3 = strtok(NULL, "^");
+          handle = vpi_handle_by_name(arg1, NULL);
+          if (handle) {
+            if (*arg2 == 'i') {
+              v.format = vpiDecStrVal;
+              v.value.str = arg3;
+            } else {
+              v.format = vpiRealVal;
+              v.value.real = strtof(arg3, NULL);
+            }
+            vpi_put_value(handle, &v, NULL, vpiForceFlag);
+          }
+          break;
+        // Release
+        //   Releases an existing force on the given net
+        //
+        //   s^origen.dut.some.net
+        //   s^origen.dut.some.net
+        case 's' :
+          arg1 = strtok(NULL, "^");
+          handle = vpi_handle_by_name(arg1, NULL);
+          if (handle) {
+            vpi_put_value(handle, &v, NULL, vpiReleaseFlag);
+          }
+          break;
         default :
           origen_log(LOG_ERROR, "Illegal message received from Origen: %s", orig_msg);
           runtime_errors += 1;
@@ -1034,7 +1084,11 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
 
     vpi_free_object(argv);
 
-    origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received %d", pin_name, expected, received);
+    if (received) {
+      origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received %d", pin_name, expected, received);
+    } else {
+      origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received X or Z", pin_name, expected);
+    }
 
     error_count++;
 
@@ -1062,7 +1116,11 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
         strcpy((*miscompare).pin_name, pin_name);
         (*miscompare).cycle = cycle_count;
         (*miscompare).expected = expected;
-        (*miscompare).received = received;
+        if (received) {
+          (*miscompare).received = received;
+        } else {
+          (*miscompare).received = -1;
+        }
       }
       transaction_error_count++;
     }

data/ext/origen.c

@@ -3,6 +3,7 @@
 /// this extension into the simulation
 ///
 #include "origen.h"
+#include "defines.h"
 #include "bridge.h"
 #include "client.h"
 #include <string.h>
@@ -12,12 +13,38 @@ static void init(void);
 
 static void init() {
   register_callback(cbStartOfSimulation, origen_startup);
-
   register_callback(cbEndOfSimulation, origen_shutdown);
-
   bridge_register_system_tasks();
 }
 
+// This function is provided as another way to initialize Origen, by calling this manually
+PLI_INT32 origen_init(p_cb_data data) {	
+  vpi_printf("Origen Initialized!\n");	
+  init();	
+  return 0;	
+}
+
+// Some legacy simulators require this manual initialization function to be called bootstrap, but
+// otherwise equivalent to the origen_init() function
+PLI_INT32 bootstrap(p_cb_data data) {	
+  vpi_printf("Origen Initialized!\n");	
+  init();	
+  return 0;	
+}
+
+#ifdef ORIGEN_VCS
+// Origen will be initialized by calling the $origen_vcs_init task from the testbench, this is required
+// for VCS since it does not allow multiple definitions of vlog_startup_routine, which is the
+// conventional way of registering a VPI plugin.
+PLI_INT32 origen_vcs_init(PLI_BYTE8 * user_dat) {
+  register_callback(cbEndOfSimulation, origen_shutdown);
+  return origen_startup(user_dat);
+}
+#else
+// This is the standard way to initialize Origen, by registering this init function through the
+// vlog_startup_routines. The simulator will then call this init function at simulation startup
+void (*vlog_startup_routines[])(void) = { init, 0 };
+#endif
 
 /// Returns the value of the given argument, or NULL if not supplied.
 /// This example: 
@@ -87,15 +114,6 @@ PLI_INT32 origen_shutdown(p_cb_data data) {
   return 0;
 }
 
-/// Function to call the init PLI's init function
-/// Some toolchains will call this automatically, some will not
-/// Available here for those which do not automatically call init() for each PLI 
-PLI_INT32 bootstrap(p_cb_data data) {
-  vpi_printf("Origen Bootstrap Called!\n");
-  init();
-  return 0;
-}
-
 ///
 /// Registers a very basic VPI callback with reason and handler.
 ///
@@ -112,9 +130,3 @@ static void register_callback(PLI_INT32 aReason, PLI_INT32 (*aHandler)(p_cb_data
 
     vpi_free_object(vpi_register_cb(&call));
 }
-
-
-///
-/// Bootstrap vector, make the simulator execute init() on startup
-///
-void (*vlog_startup_routines[])(void) = { init, 0 };

data/ext/origen.h

@@ -2,8 +2,14 @@
 #define ORIGEN_H
 
 #include "common.h"
+#include "defines.h"
 
 PLI_INT32 origen_startup(p_cb_data);
 PLI_INT32 origen_shutdown(p_cb_data);
+#ifdef ORIGEN_VCS
+PLI_INT32 origen_vcs_init(PLI_BYTE8*);
+#endif
+PLI_INT32 origen_init(p_cb_data);
+PLI_INT32 bootstrap(p_cb_data);
 
 #endif

data/ext/origen_tasks.tab

@@ -0,0 +1,2 @@
+$bridge_on_miscompare call=bridge_on_miscompare
+$origen_vcs_init call=origen_vcs_init

data/lib/origen_sim/commands/build.rb

@@ -23,6 +23,7 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
     options[:source_dirs] << path
   end
   opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t }
+  opts.on('--wreal', 'Enable real number modeling support on DUT pins defined as real wires (wreal)') { |t| options[:wreal] = t }
   opts.on('--verilog_top_output_name NAME', 'Renames the output filename from origen.v to NAME.v') do |name|
     options[:verilog_top_output_name] = name
   end
@@ -95,7 +96,7 @@ candidates = ast.top_level_modules
 candidates = ast.modules if candidates.empty?
 
 if candidates.size == 0
-  puts "Sorry, couldn't find any Verilog module declarations in that file"
+  puts "Sorry, couldn't find any Verilog module declarations in that file (this could be due to a parse error)"
   _exit_fail_
 elsif candidates.size > 1
   if options[:top_level_name]
@@ -116,7 +117,7 @@ rtl_top_module = mod.name
 
 mod.to_top_level # Creates dut
 
-# Update the pins with any setings from the command line
+# Update the pins with any settings from the command line
 options[:initial_pin_states].each do |pin, state|
   dut.pins(pin).meta[:origen_sim_init_pin_state] = state
 end
@@ -157,51 +158,97 @@ else
 
   dut.export(rtl_top_module, dir: "#{output_directory}", namespace: nil)
 
+  SYNOPSYS_SWITCHES = %W(
+    #{output_directory}/#{output_name}
+    #{output_directory}/bridge.c
+    #{output_directory}/client.c
+    -P\ #{output_directory}/origen_tasks.tab
+    -CFLAGS\ "-std=c99 -DORIGEN_VCS"
+    +vpi
+    #{output_directory}/origen.c
+    +define+ORIGEN_VCS
+    -debug_access+all
+    -timescale=1ns/1ns
+    -v2005
+    -full64
+  )
+
+  if options[:wreal]
+    SYNOPSYS_SWITCHES += %w(
+      +define+ORIGEN_WREAL
+      -realport
+      -sverilog
+      -wreal\ res_max
+    )
+  end
+
+  SYNOPSYS_DVE_SWITCHES = SYNOPSYS_SWITCHES + %w(
+    +define+ORIGEN_VPD
+  )
+
+  SYNOPSYS_VERDI_SWITCHES = SYNOPSYS_SWITCHES + %W(
+    +define+ORIGEN_FSDB
+    -kdb
+    -P\ #{ENV['VERDI_HOME'] || '$VERDI_HOME'}/share/PLI/VCS/LINUX64/novas.tab
+    #{ENV['VERDI_HOME'] || '$VERDI_HOME'}/share/PLI/VCS/LINUX64/pli.a
+  )
+
+  CADENCE_SWITCHES = %W(
+    #{output_directory}/#{output_name}
+    #{output_directory}/*.c
+    -ccargs\ "-std=c99"
+    -top\ origen
+    -elaborate
+    -snapshot\ origen
+    -access\ +rw
+    -timescale\ 1ns/1ns
+  )
+
+  if options[:wreal]
+    CADENCE_SWITCHES += %w(
+      +define+ORIGEN_WREAL
+      -ams
+    )
+  end
+
   puts
   puts
   puts '-----------------------------------------------------------'
-  puts 'Cadence Incisive (irun)'
+  puts 'Icarus Verilog'
   puts '-----------------------------------------------------------'
   puts
+  puts 'Compile the VPI extension using the following command:'
+  puts
+  puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
+  puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
   puts "  #{output_directory}/#{output_name} \\"
-  puts "  #{output_directory}/*.c \\"
-  puts '  -ccargs "-std=c99" \\'
-  puts '  -top origen \\'
-  puts '  -elaborate  \\'
-  puts '  -snapshot origen \\'
-  puts '  -access +rw \\'
-  puts '  -timescale 1ns/1ns'
+  puts '  -o origen.vvp \\'
+  puts '  -DORIGEN_VCD'
   puts
-  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+  puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
+  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
   puts
-  puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
+  puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
   puts
-  puts '  INCA_libs'
+  puts "  #{output_directory}/origen.vpi"
+  puts '  origen.vvp'
   puts
   puts '-----------------------------------------------------------'
-  puts 'Synopsys VCS'
+  puts 'Synopsys VCS w/ DVE Waveviewer'
   puts '-----------------------------------------------------------'
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/#{output_name} \\"
-  puts "  #{output_directory}/bridge.c \\"
-  puts "  #{output_directory}/client.c \\"
-  puts '  -CFLAGS "-std=c99" \\'
-  puts '  +vpi \\'
-  puts "  #{output_directory}/origen.c \\"
-  puts '  +define+ORIGEN_VPD=1 \\'
-  puts '  -debug_access+all \\'
-  puts '  -PP \\'
-  puts '  -timescale=1ns/1ns'
+  SYNOPSYS_DVE_SWITCHES.each do |switch|
+    puts "  #{switch} \\"
+  end
   puts
-  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_DVE_SWITCHES.join(' ')
   puts
   puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
   puts
@@ -209,57 +256,41 @@ else
   puts '  simv.daidir'
   puts
   puts '-----------------------------------------------------------'
-  puts 'Icarus Verilog'
+  puts 'Synopsys VCS w/ Verdi Waveviewer'
   puts '-----------------------------------------------------------'
   puts
-  puts 'Compile the VPI extension using the following command:'
-  puts
-  puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
-  puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/#{output_name} \\"
-  puts '  -o origen.vvp \\'
-  puts '  -DORIGEN_VCD'
+  SYNOPSYS_VERDI_SWITCHES.each do |switch|
+    puts "  #{switch} \\"
+  end
   puts
-  puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
+  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_VERDI_SWITCHES.join(' ')
   puts
-  puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
+  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
   puts
-  puts "  #{output_directory}/origen.vpi"
-  puts '  origen.vvp'
+  puts '  simv'
+  puts '  simv.daidir'
   puts
   puts '-----------------------------------------------------------'
-  puts 'Verdi w/ Synopsys VCS'
+  puts 'Cadence Incisive (irun)'
   puts '-----------------------------------------------------------'
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/#{output_name} \\"
-  puts "  #{output_directory}/brdige.c \\"
-  puts "  #{output_directory}/client.c \\"
-  puts '  -CFLAGS "-std=c99" \\'
-  puts '  +vpi \\'
-  puts "  #{output_directory}/origen.c \\"
-  puts '  +define+ORIGEN_FSDB=1 \\'
-  puts '  -debug_access+all \\'
-  puts '  +lint=all,noVCDE,noIWU,noVNGS,noCAWM-L,noPORTFRC,noZERO,noNS \\'
-  puts '  -PP \\'
-  puts '  -timescale=1ns/100ps \\'
-  puts '  -full64 \\'
-  puts '  -lca \\'
-  puts '  -kdb \\'
+  CADENCE_SWITCHES.each do |switch|
+    puts "  #{switch} \\"
+  end
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c +define+ORIGEN_FSDB=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all +lint=all,noVCDE,noIWU,noVNGS,noCAWM-L,noPORTFRC,noZERO,noNS -PP -timescale=1ns/100ps -full64 -lca -kdb"
+  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} -incdir #{Pathname.new(rtl_top).dirname} " + CADENCE_SWITCHES.join(' ')
   puts
-  puts 'Copy the following files (produced by vcs) to simulation/<target>/verdi/. within your Origen application:'
+  puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
   puts
-  puts '  simv'
-  puts '  simv.daidir'
+  puts '  INCA_libs'
   puts
   puts '-----------------------------------------------------------'
   puts

data/lib/origen_sim/origen/pins/pin.rb

@@ -51,6 +51,44 @@ module Origen
         @simulator_value = nil
       end
 
+      def driver_net
+        @driver_net ||= "#{tester.simulator.testbench_top}.pins.#{rtl_name}"
+      end
+
+      alias_method :_orig_drive, :drive
+      def drive(*args)
+        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+          tester.poke("#{driver_net}.drive_en", 1)
+          tester.poke("#{driver_net}.drive", args.first + 0.0)
+        else
+          _orig_drive(*args)
+        end
+      end
+      alias_method :write, :drive
+
+      alias_method :_orig_assert, :assert
+      def assert(*args)
+        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+          drive_enabled = tester.peek("#{driver_net}.drive_en").to_i
+          if drive_enabled == 1
+            tester.poke("#{driver_net}.drive_en", 0)
+            tester.cycle
+          end
+          measured = tester.peek("#{driver_net}.pin", true)
+          # Could implement checking/limits here in future
+        else
+          _orig_assert(*args)
+        end
+      end
+      alias_method :compare, :assert
+      alias_method :expect, :assert
+      alias_method :read, :assert
+      alias_method :measure, :assert
+
+      def _analog_pin_?
+        type == :analog || is_a?(Origen::Pins::PowerPin) || is_a?(Origen::Pins::GroundPin)
+      end
+
       def apply_force
         if force
           simulator.put("2^#{simulation_index}^#{force}")

data/lib/origen_sim/origen/top_level.rb

@@ -3,12 +3,17 @@ module Origen
   module TopLevel
     # Like pins, except removes any pins which have their rtl_name
     # attribute set to 'nc'
-    def rtl_pins
-      @rtl_pins ||= begin
+    # Optionally pass in a type: option set to either :analog or :digital to
+    # have only the pins with that type returned
+    def rtl_pins(options = {})
+      @rtl_pins ||= {}
+      @rtl_pins[options[:type]] ||= begin
+        opts = options.dup
         p = []
         pins.each do |name, pin|
           options = {}
-          unless pin.rtl_name.to_s.downcase == 'nc'
+          unless pin.rtl_name.to_s.downcase == 'nc' ||
+                 (opts[:type] && pin.type && opts[:type] != pin.type)
             if pin.primary_group
               options[:group] = true
             end

data/lib/origen_sim/simulation.rb

@@ -78,7 +78,7 @@ module OrigenSim
           if Origen.debugger_enabled?
             Origen.log.error 'The simulation failed to get underway!'
           else
-            Origen.log.error 'The simulation failed to get underway! (run again with -d to see why)'
+            Origen.log.error 'The simulation failed to get underway! (run again with -verbose to see why)'
           end
         else
           if in_progress

data/lib/origen_sim/simulator/user_details.rb

@@ -63,7 +63,6 @@ module OrigenSim
       #  to be defined. This should be a comma-separeted string of the available values.
       #  It will be assumed that each details will be defined in the snapshot.
       def fetch
-        puts 'FETCHING!'.cyan
         # Read the available details.
         # names = str_peek("#{debug_module}.PARAMETER_NAMES").split(',')
         names = @simulator.peek_str(detail_names_net)