origen_sim 0.16.1 → 0.20.0

data/lib/origen_sim/simulator.rb

@@ -428,8 +428,8 @@ module OrigenSim
         edir = Pathname.new(wave_config_dir).relative_path_from(Pathname.pwd)
         cmd = "cd #{edir} && "
         if configuration[:verdi]
-          unless ENV['VCS_HOME'] && ENV['LD_LIBRARY_PATH']
-            puts 'Please make sure the VCS_HOME and LD_LIBRARY PATH are setup correctly before using Verdi'
+          unless ENV['VCS_HOME']
+            Origen.log.warning "Your environment doesn't define VCS_HOME, you will probably need that to run Verdi"
           end
           edir = Pathname.new(wave_config_dir).relative_path_from(Pathname.pwd)
           cmd = "cd #{edir} && "
@@ -778,7 +778,7 @@ module OrigenSim
     # set up internal handles to efficiently access them
     def define_pins
       @pins_by_rtl_name = {}
-      dut.rtl_pins.each_with_index do |(name, pin), i|
+      dut.rtl_pins(type: :digital).each_with_index do |(name, pin), i|
         @pins_by_rtl_name[pin.rtl_name] = pin
         pin.simulation_index = i
         put("0^#{pin.rtl_name}^#{i}^#{pin.drive_wave.index}^#{pin.compare_wave.index}")
@@ -865,6 +865,7 @@ module OrigenSim
 
     def error(message)
       simulation.logged_errors = true
+      poke "#{testbench_top}.debug.errors", error_count + 1
       log message, :error
     end
 
@@ -877,87 +878,82 @@ module OrigenSim
     # resolve to a valid node
     #
     # The value is returned as an instance of Origen::Value
-    def peek(net)
-      # The Verilog spec does not specify that underlying VPI put method should
-      # handle a part select, so some simulators do not handle it. Therefore we
-      # deal with it here to ensure cross simulator compatibility.
-
-      # http://rubular.com/r/eTVGzrYmXQ
-      if net =~ /(.*)\[(\d+):?(\.\.)?(\d*)\]$/
-        net = Regexp.last_match(1)
-        msb = Regexp.last_match(2).to_i
-        lsb = Regexp.last_match(4)
-        lsb = lsb.empty? ? nil : lsb.to_i
-      end
-
+    def peek(net, real = false)
       sync_up
-      put("9^#{clean(net)}")
-      m = get.strip
+      if dut_version > '0.19.0'
+        if real
+          put("9^#{clean(net)}^f")
+          m = get.strip
+          if m == 'FAIL'
+            return nil
+          else
+            m.to_f
+          end
+        else
+          put("9^#{clean(net)}^i")
+          m = get.strip
 
-      if m == 'FAIL'
-        return nil
-      else
-        if msb
-          # Setting a range of bits
-          if lsb
-            Origen::Value.new('b' + m[(m.size - 1 - msb)..(m.size - 1 - lsb)])
+          if m == 'FAIL'
+            Origen.log.warning "Peek of net #{net} failed to return any data!"
+            return nil
           else
-            Origen::Value.new('b' + m[m.size - 1 - msb])
+            Origen::Value.new('b' + m)
           end
+        end
+      else
+        put("9^#{clean(net)}")
+        m = get.strip
+
+        if m == 'FAIL'
+          Origen.log.warning "Peek of net #{net} failed to return any data!"
+          return nil
         else
           Origen::Value.new('b' + m)
         end
       end
     end
 
+    def peek_real(net)
+      peek(net, true)
+    end
+
     # Forces the given value to the given net.
     # Note that no error checking is done and no error will be communicated if an illegal
     # net is supplied. The user should follow up with a peek if they want to verify that
     # the poke was applied.
     def poke(net, value)
-      # The Verilog spec does not specify that underlying VPI put method should
-      # handle a part select, so some simulators do not handle it. Therefore we
-      # deal with it here to ensure cross simulator compatibility.
-
-      # http://rubular.com/r/eTVGzrYmXQ
-      if !config[:vendor] == :synopsys && net =~ /(.*)\[(\d+):?(\.\.)?(\d*)\]$/
-        path = Regexp.last_match(1)
-        msb = Regexp.last_match(2).to_i
-        lsb = Regexp.last_match(4)
-        lsb = lsb.empty? ? nil : lsb.to_i
-
-        v = peek(path)
-        return nil unless v
-        # Setting a range of bits
-        if lsb
-          upper = v >> (msb + 1)
-          # Make sure value does not overflow
-          value = value[(msb - lsb)..0]
-          if lsb == 0
-            value = (upper << (msb + 1)) | value
-          else
-            lower = v[(lsb - 1)..0]
-            value = (upper << (msb + 1)) |
-                    (value << lsb) | lower
-          end
+      sync_up
+      if dut_version > '0.19.0'
+        if value.is_a?(Integer)
+          put("b^#{clean(net)}^i^#{value}")
+        else
+          put("b^#{clean(net)}^f^#{value}")
+        end
+      else
+        put("b^#{clean(net)}^#{value}")
+      end
+    end
 
-        # Setting a single bit
+    def force(net, value)
+      sync_up
+      if dut_version > '0.19.0'
+        if value.is_a?(Integer)
+          put("r^#{clean(net)}^i^#{value}")
         else
-          if msb == 0
-            upper = v >> 1
-            value = (upper << 1) | value[0]
-          else
-            lower = v[(msb - 1)..0]
-            upper = v >> (msb + 1)
-            value = (upper << (msb + 1)) |
-                    (value[0] << msb) | lower
-          end
+          put("r^#{clean(net)}^f^#{value}")
         end
-        net = path
+      else
+        OrigenSim.error 'Your DUT needs to be recompiled with OrigenSim >= 0.20.0 to support forcing, force not applied!'
       end
+    end
 
+    def release(net)
       sync_up
-      put("b^#{clean(net)}^#{value}")
+      if dut_version > '0.19.0'
+        put("s^#{clean(net)}")
+      else
+        OrigenSim.error 'Your DUT needs to be recompiled with OrigenSim >= 0.20.0 to support releasing, force not released!'
+      end
     end
 
     def interactive_shutdown
@@ -1124,17 +1120,13 @@ module OrigenSim
     end
 
     def peek_str(signal)
-      val = tester.simulator.peek(signal)
+      val = peek(signal)
       unless val.nil?
-        puts val
-        puts val.class
         # All zeros seems to be what an empty string is returned from the VPI,
         # Otherwise, break the string up into 8-bit chunks and decode the ASCII>
         val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join)
       end
       val
-      # puts "Peaking #{signal}: #{a}: #{a.class}"
-      # tester.simulator.peek(signal).to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join
     end
     alias_method :str_peek, :peek_str
     alias_method :peek_string, :peek_str
@@ -1161,8 +1153,8 @@ module OrigenSim
         errors = []
         error_count.times do |i|
           data = get  # => "tdo,648,1,0\n"
-          pin_name, cycle, expected, recieved = *(data.strip.split(','))
-          errors << { pin_name: pin_name, cycle: cycle.to_i, expected: expected.to_i, recieved: recieved.to_i }
+          pin_name, cycle, expected, received = *(data.strip.split(','))
+          errors << { pin_name: pin_name, cycle: cycle.to_i, expected: expected.to_i, received: received.to_i }
         end
         [true, error_count > max_errors, errors]
       end
@@ -1175,6 +1167,14 @@ module OrigenSim
       get.strip.to_i
     end
 
+    # Returns true if the snapshot has been compiled with WREAL support
+    def wreal?
+      return @wreal if defined?(@wreal)
+      @wreal = (dut_version > '0.19.0' &&
+                peek("#{testbench_top}.debug.wreal_enabled").to_i == 1)
+    end
+    alias_method :wreal_enabled?, :wreal?
+
     private
 
     # Will be called when the simulator has aborted due to the max error count being exceeded

data/lib/origen_sim/tester.rb

@@ -16,6 +16,7 @@ module OrigenSim
       simulator.configure(opts, &block)
       @comment_buffer = []
       @last_comment_size = 0
+      @execution_time_in_ns = 0
       super()
     end
 
@@ -38,9 +39,9 @@ module OrigenSim
       end
       @sync_pins.map do |pin|
         if @sync_cycles.size == 1
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory[0]")
+          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")[0]
         else
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory[#{@sync_cycles - 1}:0]")
+          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory").to_i[(@sync_cycles - 1)..0]
         end
       end
     end
@@ -80,11 +81,13 @@ module OrigenSim
         unless options[:timeset]
           puts 'No timeset defined!'
           puts 'Add one to your top level startup method or target like this:'
-          puts '$tester.set_timeset("nvmbist", 40)   # Where 40 is the period in ns'
+          puts 'tester.set_timeset("nvmbist", 40)   # Where 40 is the period in ns'
           exit 1
         end
         flush_comments unless @comment_buffer.empty?
-        simulator.cycle(options[:repeat] || 1)
+        repeat = options[:repeat] || 1
+        simulator.cycle(repeat)
+        @execution_time_in_ns += repeat * tester.timeset.period_in_ns
         if @after_next_vector
           @after_next_vector.call(@after_next_vector_args)
           @after_next_vector = nil
@@ -94,6 +97,7 @@ module OrigenSim
 
     def c1(msg, options = {})
       if @step_comment_on
+        PatSeq.add_thread(msg) unless options[:no_thread_id]
         simulator.log msg
         @comment_buffer << msg
       end
@@ -293,7 +297,7 @@ module OrigenSim
                 if c = read_reg_cycles[error[:cycle]]
                   if p = c[simulator.pins_by_rtl_name[error[:pin_name]]]
                     if p[:position]
-                      diffs << [p[:position], error[:recieved], error[:expected]]
+                      diffs << [p[:position], error[:received], error[:expected]]
                     end
                   end
                 end
@@ -301,6 +305,7 @@ module OrigenSim
               if diffs.empty?
                 if @read_reg_meta_supplied
                   Origen.log.warning 'It looks like the miscompare(s) occurred on pins/cycles that are not associated with register data'
+                  non_data_miscompare = true
                 else
                   Origen.log.warning 'It looks like your current read register driver does not provide the necessary meta-data to map these errors to an actual register value'
                 end
@@ -323,7 +328,11 @@ module OrigenSim
                 end
 
                 diffs.each do |position, received, expected|
-                  reg_or_val[position].data = received
+                  if received == -1
+                    reg_or_val[position].unknown = true
+                  else
+                    reg_or_val[position].data = received
+                  end
                 end
 
                 actual = bit_names.map do |name|
@@ -357,7 +366,8 @@ module OrigenSim
                   Origen.log.error msg
                 end
               else
-                msg += " received #{expected}" if @read_reg_meta_supplied
+                # This means that the correct data was read, but errors occurred on other pins/cycles during the transaction
+                msg += " received #{expected}" if non_data_miscompare
                 Origen.log.error msg
               end
             end
@@ -367,7 +377,10 @@ module OrigenSim
             if actual_data_available
               actual = reg_or_val
               diffs.each do |position, received, expected|
-                if received == 1
+                if received == -1
+                  actual = '?' * reg_or_val.to_s(16).size
+                  break
+                elsif received == 1
                   actual |= (1 << position)
                 else
                   lower = actual[(position - 1)..0]
@@ -376,9 +389,14 @@ module OrigenSim
                   actual |= lower
                 end
               end
-              msg += " received #{actual.to_s(16).upcase}"
+              if actual.is_a?(String)
+                msg += " received #{actual}"
+              else
+                msg += " received #{actual.to_s(16).upcase}"
+              end
             else
-              msg += " received #{reg_or_val.to_s(16).upcase}" if @read_reg_meta_supplied
+              # This means that the correct data was read, but errors occurred on other pins/cycles during the transaction
+              msg += " received #{reg_or_val.to_s(16).upcase}" if non_data_miscompare
             end
             Origen.log.error msg
           end
@@ -409,6 +427,31 @@ module OrigenSim
       @read_reg_meta_supplied = val
     end
 
+    # Shorthand for simulator.poke
+    def poke(*args)
+      simulator.poke(*args)
+    end
+
+    # Shorthand for simulator.peek
+    def peek(*args)
+      simulator.peek(*args)
+    end
+
+    # Shorthand for simulator.peek_real
+    def peek_real(*args)
+      simulator.peek_real(*args)
+    end
+
+    # Shorthand for simulator.force
+    def force(*args)
+      simulator.force(*args)
+    end
+
+    # Shorthand for simulator.release
+    def release(*args)
+      simulator.release(*args)
+    end
+
     private
 
     def flush_comments

data/lib/origen_sim_dev/dut.rb

@@ -26,6 +26,8 @@ module OrigenSimDev
       add_pin :v2, rtl_name: :nc
       add_pin :done
       add_pin :not_present
+      add_power_pin :vdd
+      add_pin :ana, type: :analog
 
       timeset :func do |t|
         # Generate a clock pulse on TCK
@@ -73,6 +75,15 @@ module OrigenSimDev
         reg.bits 2..0, :b6
       end
 
+      add_reg :ana_test, 0x1C do |reg|
+        reg.bit 0, :vdd_valid, access: :ro
+        reg.bit 1, :bgap_out
+        reg.bit 2, :osc_out
+        reg.bit 3, :vdd_div4
+      end
+
+      add_reg :x_reg, 0x20
+
       sub_block :ip1, class_name: 'IP'
       sub_block :ip2, class_name: 'IP'
     end
@@ -84,6 +95,10 @@ module OrigenSimDev
       end
     end
 
+    def simulation_startup
+      power_pin(:vdd).drive(0)
+    end
+
     def startup(options = {})
       # tester.simulator.log_messages = true
       tester.set_timeset('func', 100)
@@ -101,60 +116,65 @@ module OrigenSimDev
     end
 
     def write_register(reg, options = {})
-      if reg.path =~ /ip(\d)/
-        ir_val = 0b0100 | Regexp.last_match(1).to_i
-        jtag.write_ir(ir_val, size: 4)
-        ip = reg.parent
-        ip.dr.bits(:write).write(1)
-        ip.dr.bits(:address).write(reg.address)
-        ip.dr.bits(:data).write(reg.data)
-        jtag.write_dr(ip.dr)
-      # Write to top-level reg
-      else
-        jtag.write_ir(0x8, size: 4)
-        dr.rg_enable.write(1)
-        dr.rg_read.write(0)
-        dr.rg_addr.write(reg.address)
-        dr.rg_data.write(reg.data)
-        jtag.write_dr(dr)
+      PatSeq.serialize :jtag do
+        if reg.path =~ /ip(\d)/
+          ir_val = 0b0100 | Regexp.last_match(1).to_i
+          jtag.write_ir(ir_val, size: 4)
+          ip = reg.parent
+          ip.dr.bits(:write).write(1)
+          ip.dr.bits(:address).write(reg.address)
+          ip.dr.bits(:data).write(reg.data)
+          jtag.write_dr(ip.dr)
+        # Write to top-level reg
+        else
+          jtag.write_ir(0x8, size: 4)
+          dr.rg_enable.write(1)
+          dr.rg_read.write(0)
+          dr.rg_addr.write(reg.address)
+          dr.rg_data.write(reg.data)
+          jtag.write_dr(dr)
+        end
       end
     end
 
     def read_register(reg, options = {})
-      tester.read_register(reg, options) do
-        # Special read for this register to test sync'ing over a parallel
-        if reg.id == :parallel_read
-          pins = []
-          reg.shift_out_with_index do |bit, i|
-            if bit.is_to_be_stored?
-              pins << dut.pins(:dout)[i]
+      PatSeq.serialize :jtag do
+        tester.read_register(reg, options) do
+          # Special read for this register to test sync'ing over a parallel port
+          if reg.id == :parallel_read
+            pins = []
+            reg.shift_out_with_index do |bit, i|
+              if bit.is_to_be_stored?
+                pins << dut.pins(:dout)[i]
+              end
             end
-          end
-          tester.store_next_cycle(*pins.reverse)
-          1.cycle
-          dut.pins(:dout).dont_care
-        else
-          if reg.path =~ /ip(\d)/
-            ir_val = 0b0100 | Regexp.last_match(1).to_i
-            jtag.write_ir(ir_val, size: 4)
-            ip = reg.parent
-            ip.dr.bits(:write).write(0)
-            ip.dr.bits(:address).write(reg.address)
-            ip.dr.bits(:data).write(0)
-            jtag.write_dr(ip.dr)
-            ip.dr.bits(:data).copy_all(reg)
-            jtag.read_dr(ip.dr)
+            tester.store_next_cycle(*pins.reverse)
+            1.cycle
+            dut.pins(:dout).dont_care
           else
-            jtag.write_ir(0x8, size: 4)
-            dr.rg_enable.write(1)
-            dr.rg_read.write(1)
-            dr.rg_addr.write(reg.address)
-            jtag.write_dr(dr)
-            dr.rg_enable.write(0)
-            dr.rg_data.copy_all(reg)
-            jtag.read_dr(dr)
+            if reg.path =~ /ip(\d)/
+              ir_val = 0b0100 | Regexp.last_match(1).to_i
+              jtag.write_ir(ir_val, size: 4)
+              ip = reg.parent
+              ip.dr.bits(:write).write(0)
+              ip.dr.bits(:address).write(reg.address)
+              ip.dr.bits(:data).write(0)
+              jtag.write_dr(ip.dr)
+              ip.dr.bits(:data).copy_all(reg)
+              jtag.read_dr(ip.dr)
+            else
+              jtag.write_ir(0x8, size: 4)
+              dr.rg_enable.write(1)
+              dr.rg_read.write(1)
+              dr.rg_addr.write(reg.address)
+              jtag.write_dr(dr)
+              dr.rg_enable.write(0)
+              dr.rg_data.copy_all(reg)
+              jtag.read_dr(dr)
+            end
           end
         end
+        reg.clear_flags
       end
     end
   end

data/lib/origen_sim_dev/ip.rb

@@ -33,14 +33,21 @@ module OrigenSimDev
 
     def execute_cmd(code)
       ss "Execute command #{code}"
-      # Verify that no command is currently running
-      status.read!(0)
-
-      cmd.write!(code)
-      10.cycles
-      # Verify that the command has started
-
-      status.busy.read!(1)
+      PatSeq.reserve :jtag do
+        # This is redundant, but added as a test that if an embedded reservation is made to the same
+        # resource then the end of the inner block does not release the reservation before completion
+        # of the outer block
+        PatSeq.reserve :jtag do
+          # Verify that no command is currently running
+          status.read!(0)
+        end
+
+        cmd.write!(code)
+        10.cycles
+        # Verify that the command has started
+
+        status.busy.read!(1)
+      end
 
       # Wait for the command to complete, a 'command' lasts for
       # 1000 cycles times the command code

data/pattern/concurrent_ip.rb

@@ -0,0 +1,17 @@
+Pattern.sequence do |seq|
+  1.cycle
+
+  dut.ip1.communication_test
+
+  seq.run :ip1_test
+
+  seq.run :ip2_test
+
+  seq.in_parallel :ip1 do
+    seq.run :ip1_test
+  end
+
+  seq.in_parallel :ip2 do
+    seq.run :ip2_test
+  end
+end