origen_sim 0.16.1 → 0.20.0

data/pattern/test.rb

@@ -2,6 +2,30 @@ Pattern.create do
   IDCODE = 0b0010
   DEBUG  = 0b1000
 
+  # Peeks the given net and will fail if the returned value does not equal the expected
+  def peek(net, expected)
+    if expected.is_a?(Integer)
+      actual = tester.peek(net)
+    else
+      actual = tester.peek_real(net)
+    end
+    if actual
+      if expected.is_a?(Integer)
+        actual = actual.to_i
+        actual_str = actual.try(:to_hex) || 'nil'
+        expected_str = expected.to_hex
+      else
+        actual_str = actual ? actual.to_s : 'nil'
+        expected_str = expected.to_s
+      end
+      unless actual == expected
+        OrigenSim.error "Expected to peek #{expected_str} from #{net}, got #{actual_str}!"
+      end
+    else
+      OrigenSim.error "Nothing returned from peek of #{net}!"
+    end
+  end
+
   ss "Some basic shift operations to verify functionality"
   dut.jtag.write_ir(0x0, size: 4)
   dut.jtag.read_ir(0x0, size: 4)
@@ -39,26 +63,111 @@ Pattern.create do
   dut.cmd.read!(0x1234_5678)
 
   if tester.sim?
+    ss "Test poking a register value"
     tester.simulator.poke("dut.cmd", 0x1122_3344)
     dut.cmd.read!(0x1122_3344)
+
+    ss "Test peeking a register value"
+    peek("dut.cmd", 0x1122_3344)
+
+    ss "Test forcing a value"
+    tester.force("dut.cmd", 0x2222_3333)
+    dut.cmd.read!(0x2222_3333)
+    peek("dut.cmd", 0x2222_3333)
+    dut.cmd.write!(0x1234_5678)
+    dut.cmd.read!(0x2222_3333)
+
+    ss "Test releasing a forced value"
+    tester.release("dut.cmd")
+    dut.cmd.write!(0x1234_5678)
+    dut.cmd.read!(0x1234_5678)
+
+    ss "Test poking a real value"
+    tester.poke("dut.real_val", 1.25)
+    10.cycles
+
+    ss "Verify that the memory can be accessed"
+    dut.mem(0x1000_0000).write!(0x1234_5678)
+    dut.mem(0x1000_0000).read!(0x1234_5678)
+
+    ss "Test poking a memory"
+    tester.poke("dut.mem[1]", 0x1111_2222)
+    dut.mem(0x1000_0004).read!(0x1111_2222)
+
+    ss "Test peeking a memory"
+    tester.poke("dut.mem[2]", 0x1111_2222)
+    peek("dut.mem[2]", 0x1111_2222)
+
+    ss "Test peeking and poking a wide memory"
+    tester.poke("dut.wide_mem[2]", 0x1FF_1111_2222_3333_4444_5555_6666_7777_8888)
+    peek("dut.wide_mem[2]", 0x1FF_1111_2222_3333_4444_5555_6666_7777_8888)
+
+    # Peek (or force?) a real value not working on Icarus, can't get it to work but not
+    # spending much time on it since this is mainly useful in a WREAL simulation and other
+    # things don't work that are blocking that anyway
+    unless tester.simulator.config[:vendor] == :icarus
+      ss "Test peeking a real value"
+      peek("dut.real_val", 1.25)
+      10.cycles
+
+      ss "Test forcing a real value"
+      tester.force("dut.real_val", 2.25)
+      10.cycles
+      peek("dut.real_val", 2.25)
+
+      ss "Test releasing a forced real value"
+      tester.poke("dut.real_val", 1.25)
+      10.cycles
+      peek("dut.real_val", 2.25)
+      tester.release("dut.real_val")
+      10.cycles
+      peek("dut.real_val", 2.25)
+      tester.poke("dut.real_val", 1.25)
+      10.cycles
+      peek("dut.real_val", 1.25)
+    end
+
+    if tester.simulator.wreal?
+      ss "Test analog pin API by ramping dut.vdd"
+      v = 0
+      dut.power_pin(:vdd).drive!(v)
+      dut.ana_test.vdd_valid.read!(0)
+      until v >= 1.25
+        v += 0.05
+        dut.power_pin(:vdd).drive!(v)
+      end
+      dut.ana_test.vdd_valid.read!(1)
+      100.cycles
+
+      ss "Test analog pin measure API"
+      dut.ana_test.vdd_div4.write!(1)
+      measured = dut.pin(:ana).measure
+      if measured != 0.3125
+        OrigenSim.error "Expected to measure 0.3125V from the ana pin, got #{measured}V!"
+      end
+
+      ss "Test the different analog mux functions"
+      dut.ana_test.write(0)
+      dut.ana_test.vdd_div4.write!(1)
+      1000.cycles
+      dut.ana_test.write(0)
+      dut.ana_test.bgap_out.write!(1)
+      1000.cycles
+      dut.ana_test.write(0)
+      dut.ana_test.osc_out.write!(1)
+      1000.cycles
+    end
   end
 
   ss "Test storing a register"
   dut.cmd.write!(0x2244_6688)
   Origen.log.info "Should be within 'Test storing a register'"
   dut.cmd.store!
-
   if tester.sim?
-    sim = tester.simulator
-    capture_value = sim.peek("origen.pins.tdo.memory").to_i[31..0]
-    unless capture_value == 0x11662244 # 0x2244_6688 reversed
-      if capture_value
-        OrigenSim.error "Captured #{capture_value.to_hex} instead of 0x11662244!"
-      else
-        OrigenSim.error "Nothing captured instead of 0x11662244!"
-      end
-    end
+    peek("origen.pins.tdo.memory", 0x11662244) # 0x2244_6688 reversed
+  end
 
+  if tester.sim?
     ss "Test sync of a register"
     dut.cmd.write(0) # Make Origen forget the actual value
     dut.cmd.sync
@@ -75,6 +184,9 @@ Pattern.create do
     unless dut.parallel_read.data == 0x7707_7077
       OrigenSim.error "PARALLEL_READ register did not sync from simulation"
     end
+
+    #ss "Test reading an X register value"
+    #dut.x_reg.read!(0)
   end
 
   ss "Do some operations with the counter, just for fun"

data/templates/empty.rc

@@ -1,12 +1,10 @@
 Magic 271485
-Revision Verdi_N-2017.12-SP2
+Revision Verdi_O-2018.09-SP2-1
 
 ; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
-viewPort 0 28 1450 327 288 65
 
 ; File list:
 ; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
-openDirFile -d / "" ""
 
 ; file time scale:
 ; fileTimeScale ### s|ms|us|ns|ps
@@ -18,16 +16,11 @@ signalSpacing 5
 windowTimeUnit 1ns
 
 ; waveform viewport range
-zoom 0.000000 4013756.949425 1n
-cursor 10096.000000
-marker 0.000000
 
 ; user define markers
 ; userMarker time_pos marker_name color linestyle
 ; visible top row signal index
-top 0
 ; marker line index
-markerPos 6
 
 ; event list
 ; addEvent event_name event_expression
@@ -47,37 +40,34 @@ COMPLEX_EVENT_END
 curSTATUS ByChange
 
 
-activeDirFile "" ""
 addGroup "Debug"
-addSignal -h 15 -UNSIGNED -HEX -holdScope errors[31:0]
+addSignal -h 15 /origen/debug/marker[15:0]
+addSignal -h 15 -holdScope handshake
 addSignal -h 15 -UNSIGNED -ASC -holdScope pattern[1023:0]
-addGroup "Comments"
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[0]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[1]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[2]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[3]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[4]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[5]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[6]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[7]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[8]
-addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments[9]
+addSubGroup "Comments"
+addSignal -h 15 -UNSIGNED -ASC /origen/debug/comments0[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments1[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments2[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments3[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments4[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments5[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments6[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments7[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments8[1023:0]
+addSignal -h 15 -UNSIGNED -ASC -holdScope comments9[1023:0]
+endSubGroup "Comments"
+addSignal -h 15 -UNSIGNED -UDEC /origen/debug/errors[31:0]
 addGroup "DUT"
 
 ; getSignalForm Scope Hierarchy Status
 ; active file of getSignalForm
-activeDirFile "" ""
 
 GETSIGNALFORM_SCOPE_HIERARCHY_BEGIN
 getSignalForm close
 
-"/FSN_DLLDELAY_1"
 "/origen"
 
 SCOPE_LIST_BEGIN
-"/testbench/msf1"
-"/FSN_DLLDELAY_1"
-"/testbench"
 "/origen"
 "/origen/dut"
 "/origen/debug"

data/templates/origen_guides/simulation/ams.md.erb

@@ -0,0 +1,141 @@
+% render "layouts/guides.html" do
+
+OrigenSim supports analog/mixed-signal (AMS) simulations via real-number modeling (RNM), whereby
+top-level pins can be defined as real wire types (WREALs) and then Origen APIs can be used to drive
+and measure real number values from them.
+
+By default, OrigenSim's built in simulation setups will run a digital simulation, allowing such real number
+inputs to be used by behavioral models within that DUT which can themselves output real numbers to be
+observed on the DUT's pins by Origen APIs.
+
+The DUT could also contain full electical models which consume the real number inputs, in that 
+case a [custom simulation configuration](<%= path "guides/simulation/environment/#Custom_Simulator_Configuration" %>)
+will be required to define the run command to start the simulation.
+
+#### Building Support for AMS Simulation
+
+AMS support must be added in when building the testbench, this is done by adding the `--wreal` switch to the
+`sim:build` command:
+
+~~~text
+origen sim:build path/to/my_dut.v --wreal
+~~~
+
+By adding this switch, any pins which are defined as `wreal` types within the given top level will be assigned
+an analog pin driver by the testbench rather than a digital driver which is the default.
+
+Pins can be defined as a `wreal` type either by adding the `real` type to their definition:
+
+~~~verilog
+input real vddc,
+~~~
+
+or by adding a `wreal` wire within the module body:
+
+~~~verilog
+wreal vddc;
+~~~
+
+Here is an example which uses both approaches to declare the `vdd` and `ana` pins as analog pins whenever
+the `USE_WREAL` define is enabled:
+
+~~~verilog
+module my_dut(
+  input tck, tdi, tms, trstn,
+  input rstn,
+  input [31:0] din,
+  input p1,
+  input p2,
+  `ifdef USE_WREAL
+  inout real vdd,
+  `else
+  inout vdd,
+  `endif
+
+  output tdo,
+  output done,
+  output [15:0] test_bus,
+  output [31:0] dout,
+  output ana
+);
+
+`ifdef USE_WREAL
+  wreal ana;
+`endif
+endmodule
+~~~
+
+A digital testbench for this would be built via this command:
+
+~~~text
+origen sim:build path/to/my_dut.v
+~~~
+
+while AMS support would be added by running:
+
+~~~text
+origen sim:build path/to/my_dut.v --wreal --define USE_WREAL
+~~~
+
+#### Origen Application Configuration
+
+Within the corresponding Origen DUT model of the design, the wreal pins should be declared as either an
+analog, power or ground pins.
+
+From the above example, the wreal pins could be modeled like this:
+
+~~~ruby
+add_power_pin :vdd    # Could also be a regular analog pin too, if you prefer
+
+add_pin :ana, type: :analog
+~~~
+
+See the [Pins Guide](<%= path "guides/models/pins" %>) for more information on modeling pins in Origen.
+
+#### AMS APIs
+
+With all of the AMS configuration done, real values can now be driven and read from Origen application code
+during a simulation like this:
+
+~~~ruby
+dut.power_pin(:vdd).drive(1.25)
+
+dut.pin(:ana).read     # => 0.7
+
+# .measure is available as an alias of read for analog pins
+dut.pin(:ana).measure  # => 0.7
+~~~
+
+The `peek`, `poke` and `force` methods from [the Direct DUT Manipulation APIs](<%= path "guides/simulation/direct" %>) are
+also available to manipulate real valued nets during simulation.
+
+The analog pin APIs will not work correctly when generating a pattern for an ATE and the application code is 
+responsible for handling them safely, typically like this:
+
+~~~ruby
+# Example of a simulation-only assertion
+if tester.sim?
+  measured = dut.pin(:ana).measure
+  if measured != 0.3125
+    OrigenSim.error "Expected to measure 0.3125V from the ana pin, got #{measured}V!"
+  end
+end
+~~~
+
+It is easy to build more complex functionality in your application code from these simple APIs, for example to
+ramp a vdd pin:
+
+~~~ruby
+# Ramp up the power on VDD
+v = 0
+dut.power_pin(:vdd).drive!(v)
+until v >= 1.25
+  v += 0.05
+  dut.power_pin(:vdd).drive!(v)   # Note the use of drive! here which will generate a cycle
+end
+~~~
+
+It is hoped that the community will contribute plugins that contain higher-level functionality like this
+to make such functions available off-the-shelf in the future.
+
+% end

data/templates/origen_guides/simulation/compiling.md.erb

@@ -81,7 +81,55 @@ origen sim:build path/to/my_top_level.v
 top-level pin interface and reducing the amount of superfluous design code will reduce the chance
 of parse errors during this step.**
 
-Multiple files can be passed in, for example to include a defines file:
+For example, something like this is sufficient to be able to generate an Origen test bench:
+
+~~~verilog
+module my_dut(
+  input tck, tdi, tms, trstn,
+  input rstn,
+  input [31:0] din,
+  input p1,
+  input p2,
+  inout vdd,
+
+  output tdo,
+  output done,
+  output [15:0] test_bus,
+  output [31:0] dout,
+  output ana
+);
+
+endmodule
+~~~
+
+If you find that it does choke on your design files please do enter a ticket describing the code
+which failed to parse here - <https://github.com/Origen-SDK/origen_verilog/issues>
+
+In most cases any parse issues can be resolved by moving to a stub model like above or by simply removing the
+offending code to create a partial stub.
+
+The `sim:build` command does have some rudimentary support for evaluating and applying Verilog compiler
+directive rules, though at the time of writing it does not evaluate Verilog parameters.
+
+For example if your code contained something like this:
+
+~~~verilog
+output [`DATA_WIDTH-1:0] dout;
+~~~
+
+Then you can define it on the command line like this:
+
+~~~text
+origen sim:build path/to/my_dut.v --define DATA_WIDTH=8
+~~~
+
+Multiple defines should be specified like this:
+
+~~~text
+origen sim:build path/to/my_dut.v --define DATA_WIDTH=8 --define WREAL
+~~~
+
+Multiple files can be passed in, for example to include defines contained in a file rather than via the command line:
 
 ~~~text
 origen sim:build path/to/my_defines.v path/to/my_top_level.v
@@ -93,14 +141,11 @@ If you prefer, it also works by supplying the source file directory path(s) sepa
 origen sim:build my_defines.v my_top_level.v -s path/to
 ~~~
 
-The `sim:build` command does have some rudimentary support for evaluating and applying Verilog compiler
-directive rules, though at the time of writing it does not evaluate Verilog parameters.
+Run `origen sim:build -h` to see the additional switches that are supported.
 
-If you find that it does choke on your design files please do enter a ticket describing the code
-which failed to parse here - <https://github.com/Origen-SDK/origen_verilog/issues>
+Also refer to [AMS Support](<%= path "guides/simulation/ams" %>) for details on how to enable analog/mixed-signal support when
+building the testbench.
 
-In most cases any parse issues can be resolved by moving to a stub model or by simply removing the
-offending code to create a partial stub.
 
 Once you see a message like this, you are ready to move onto the next step:
 

data/templates/origen_guides/simulation/debugging.md.erb

@@ -160,7 +160,7 @@ Note that flushing will internally call a `sync_up` so you don't have to do both
 The methods `tester.simulator.peek` and `tester.simulator.poke` are available for reading and writing values
 to internal DUT nets respectively.
 
-See the section on [Creating Simulation-Only Assertions](<%= path "guides/simulation/patterns/#Creating_Simulation-Only_Assertions" %>)
+See the section on [Direct DUT Manipulation](<%= path "guides/simulation/direct" %>)
 for more details on these.
 
 #### Register Reading (and Writing)

data/templates/origen_guides/simulation/direct.md.erb

@@ -0,0 +1,112 @@
+% render "layouts/guides.html" do
+
+A number of methods exist to directly manipulate the state of the DUT during a simulation, in all
+cases these methods do not re-target to the ATE because they rely on being able to directly look inside
+and manipulate the DUT which is not possible in the physical world.
+
+The user is responsible for ensuring that the use of these APIs is safely handled when generating for
+an ATE or other non-simulation target, normally via one of these constructs:
+
+~~~ruby
+# Simply skip this unless simulating
+unless tester.sim?
+  tester.peek # ...
+end
+  
+# Implement differently for ATE
+if tester.sim?
+  tester.poke # ...
+else
+  dut.do_something
+end
+~~~
+
+#### Poke
+
+Poking is the term commonly given to changing the value of a register or other variable, i.e. poking a new
+value into an existing storage element.
+
+To use the `poke` method, supply the net path of the storage element to be changed and the value you want to
+change it to:
+
+~~~ruby
+# Poking a register
+tester.poke("dut.my_ip.user_regs.some_reg", 0x1111)
+
+# Poking a memory
+tester.poke("dut.my_ip.mem[15]", 0x1111_2222)
+~~~
+
+The poke method can be used on real variables too, in that case a float should be given as the second
+argument instead of an integer to indicate to Origen that a real value net is being poked. e.g. to poke
+the value `1` to a real value net then supply `1.0` as the value argument instead of `1`.
+
+~~~ruby
+tester.poke("dut.my_ip.my_real_var", 1.25)
+~~~
+
+#### Peek
+
+Peeking allows you to read the value of an internal register or other variable.
+
+The value returned from the `peek` method will be
+an instance of [Origen::Value](<%= path "api/Origen/Value.html" %>) which can also handle
+`X` or `Z` values.
+
+Normally, if you don't care about catching `Z` or `X` cases you can simply call `to_i` on the value
+returned from `peek`, here are some examples:
+
+~~~ruby
+# Peeking a register
+tester.peek("dut.my_ip.user_regs.some_reg").to_i   # => 0x1111
+
+# Peeking a memory
+tester.peek("dut.my_ip.mem[15]").to_i   # => 0x1111_2222
+~~~
+
+When peeking a real number, `X` or `Z` states are not supported and a float will be returned.
+
+You must indicate to Origen that you are peeking a real value by supplying a second argument of `true`,
+or for convenience calling `peek_real` instead:
+
+~~~ruby
+tester.peek("dut.my_ip.my_real_var", true)   # => 1.25
+
+tester.peek_real("dut.my_ip.my_real_var")    # => 1.25
+~~~
+
+#### Force
+
+When poking the DUT, you are changing the value
+of a reg or other variable which provides drive. i.e. as soon as the `poke` operation is done, the responsibility
+for maintaining and driving the new value is down to the DUT.
+For this reason, you cannot just poke any net, only those which can store/drive state. In Verilog terms, you can
+poke a register but you can't poke a wire.
+
+With a force, the simulator provides infinite drive/storage of the forced value and this will override any drive
+produced in the DUT.
+So when you force a value on a net, that will persist there for the entire simulation regardless of what goes on
+in the DUT until the force is released.
+
+The `force` method has the same arguments as the `peek` method:
+
+~~~ruby
+# Forcing a register
+tester.force("dut.my_ip.user_regs.some_reg", 0x1111)
+
+# Forcing a memory
+tester.force("dut.my_ip.mem[15]", 0x1111_2222)
+
+# Forcing a real value
+tester.force("dut.my_ip.my_real_var", 1.25)
+~~~
+
+A force can be released by calling the `release` method and supplying the net reference:
+
+~~~ruby
+# Releasing an existing force
+tester.release("dut.my_ip.user_regs.some_reg")
+~~~
+
+
+% end

data/templates/origen_guides/simulation/environment.md.erb

@@ -115,9 +115,12 @@ OrigenSim.cadence do |sim|
 end
 ~~~
 
-#### Generic and Advanced Simulator Configuration
+#### Custom Simulator Configuration
 
-A generic simulator configuration allows you to use a tool that is not supported out of the box by <code>OrigenSim</code>. For these, it 
+A custom simulator configuration allows you to use a tool that is not supported out of the box by <code>OrigenSim</code>,
+or to setup a more advanced simulation run command such as that required to run an analog-digital co-simulation if your
+DUT contains full electrical models of some IPs.
+For these, it 
 is your responsibility to provide the command to start the simulation process, however, this allows for arbitrary commands to
 start the process and allows end users to still use <code>origen g</code> as if with a fully <code>OrigenSim</code> supported
 simulator configuration.
@@ -139,7 +142,7 @@ Here is an example using the predecessor of the supported Cadence tool <code>iru
 OrigenSim.generic do |sim|
   sim.testbench_top 'na_origen'
   sim.generic_run_cmd do |s|
-    "ncsim na_origen -loadpli origen.so:bootstrap +socket+#{s.socket_id}"
+    "ncsim na_origen -loadpli origen.so:origen_init +socket+#{s.socket_id}"
   end
 end
 ~~~

data/templates/origen_guides/simulation/patterns.md.erb

@@ -217,12 +217,7 @@ unless tester.simulator.peek("origen.dut.path.to.net")[4].z?
 end
 ~~~
 
-It is also possible to force nets within the DUT via a corresponding `poke` method:
-
-~~~ruby
-if tester.sim?
-  test.simulator.poke "path.to.some.net[15:8]", 0x51
-end
-~~~
+See the [Direct DUT Manipulation](<%= path "guides/simulation/direct" %>) guide for more details on these
+APIs.
 
 % end