origen_sim 0.20.6 → 0.21.0

data/templates/rtl_v/origen.v.erb

@@ -1,4 +1,53 @@
-%#`include "<%= options[:top] %>"
+// This is an auto-generated file from OrigenSim
+//   (https://origen-sdk.org/origen/guides/simulation/introduction/)
+// This file was generated with this command:
+//   <%= options[:build_cmd] %>
+
+% pins_by_type = [[nil]]
+% type = nil
+% dut.rtl_pins.each do |n, p|
+%  if p.type == type
+%    pins_by_type.last << p
+%  else
+%    pins_by_type << [p.type, p]
+%    type = p.type
+%  end
+% end
+
+// Utility Macros
+// Cast define value as a string.
+`define ORIGEN_SIM_TO_S(s) `"s`"
+
+// Indicate the target vendor
+% if options[:vendor] == :cadence
+`define ORIGEN_SIM_CADENCE
+% elsif options[:vendor] == :synopsis
+`define ORIGEN_SIM_SYNOPSIS
+% elsif options[:vendor] == :icarus
+`define ORIGEN_SIM_ICARUS
+% end
+
+// Indicate the file type, without resorting to System Verilog or vendor-specific functions
+% if options[:file_type] == :sv
+`define ORIGEN_SV_FILE
+% elsif options[:file_type] == :vams
+`define ORIGEN_VAMS_FILE
+% else
+`define ORIGEN_V_FILE
+% end
+
+`ifdef ORIGEN_WREAL
+  `define ORIGEN_USE_REAL
+  `define ORIGEN_REAL_TYPE wreal
+`elsif ORIGEN_WREALAVG
+  `define ORIGEN_USE_REAL
+  `define ORIGEN_REAL_TYPE wrealavg
+  `ifdef ORIGEN_SIM_CADENCE
+    import cds_rnm_pkg::*;
+  `elsif ORIGEN_SIM_SYNOPSIS
+    import snps_msv_nettype_pkg::*;
+  `endif
+`endif
 
 // To create the big fonts - http://patorjk.com/software/taag/#p=display&f=Big
 
@@ -103,7 +152,7 @@ module pin_driver(pin, sync);
 endmodule
 
 
-`ifdef ORIGEN_WREAL 
+`ifdef ORIGEN_USE_REAL
 //                       _               _____ _         _____       _                
 //     /\               | |             |  __ (_)       |  __ \     (_)               
 //    /  \   _ __   __ _| | ___   __ _  | |__) | _ __   | |  | |_ __ ___   _____ _ __ 
@@ -113,13 +162,13 @@ endmodule
 //                                __/ |                                               
 //                               |___/                                                
 
-// A simple WREAL pin driver that can drive real value on a pin or else hi-Z, when the driver is in
+// A simple WREAL/WREALAVG pin driver that can drive real value on a pin or else hi-Z, when the driver is in
 // hi-Z mode the value applied by any other driver connected to the pin can be measured by peeking
 // the value on pin
 module ana_pin_driver(pin);
   inout pin;
 
-  wreal pin;
+  `ORIGEN_REAL_TYPE pin;
 
   reg drive_en = 0;
   real drive = 0.0;      // Value that will be driven on pin when drive is enabled
@@ -140,36 +189,52 @@ endmodule
 // drivers are therefore accessible via origen.pins.my_pin_name
 module pin_drivers(<%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" }.join(', ') %>);
 
-% dut.rtl_pins.each do |name, pin, options|
-%   if pin.type == :analog
-`ifdef ORIGEN_WREAL 
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
   inout <%= pin.id %>_o;
+%     end
 `else
+%     group[1..-1].each do |pin|
   output <%= pin.id %>_o;
+%     end
 `endif
 %   else
+%     group[1..-1].each do |pin|
   output <%= pin.id %>_o;
+%     end
 %   end
 % end
 
-`ifdef ORIGEN_WREAL 
+`ifdef ORIGEN_USE_REAL 
 % dut.rtl_pins(type: :analog).each do |name, pin, options|
-  wreal <%= pin.id %>_o;
+  `ORIGEN_REAL_TYPE <%= pin.id %>_o;
 % end
 `endif
 
   reg sync = 0;
 
-% dut.rtl_pins.each do |name, pin, options|
-%   unless pin.meta[:origen_sim_init_pin_state] == -2
-%     if pin.type == :analog
-`ifdef ORIGEN_WREAL 
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   ana_pin_driver <%= pin.id %>(.pin(<%= pin.id %>_o));
+%       end
+%     end
 `else
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   pin_driver #(<%= pin.meta[:origen_sim_init_pin_state].nil? ? '' : ".init_drive(#{pin.meta[:origen_sim_init_pin_state]}), "%>.pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .sync(sync));
+%       end
+%     end
 `endif
-%     else
+%   else
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   pin_driver #(<%= pin.meta[:origen_sim_init_pin_state].nil? ? '' : ".init_drive(#{pin.meta[:origen_sim_init_pin_state]}), "%>.pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .sync(sync));
+%       end
 %     end
 %   end
 % end
@@ -224,7 +289,7 @@ endmodule
 
 // Instantiated as origen.debug, this module contains the error count, current pattern name and comments,
 // metadata associated with the snapshot build, and other debug information
-module debug;
+module <%= options[:debug_module_name] %>;
   reg [31:0] errors = 0;
   reg [15:0] marker = 0;
   reg [31:0] match_errors = 0;
@@ -238,10 +303,16 @@ module debug;
 
   snapshot_details snapshot_details();
 
-`ifdef ORIGEN_WREAL 
-  reg wreal_enabled = 1;
+`ifdef ORIGEN_USE_REAL 
+  reg real_enabled = 1;
+`ifdef ORIGEN_SV_FILE
+  reg [1023:0] real_type = `ORIGEN_SIM_TO_S(`ORIGEN_REAL_TYPE`);
+`else
+  reg [1023:0] real_type = "wreal";
+`endif
 `else
-  reg wreal_enabled = 0;
+  reg real_enabled = 0;
+  reg [1023:0] real_type = 0;
 `endif
   
 endmodule
@@ -255,19 +326,25 @@ endmodule
 //            | |                                                 
 //            |_|                                                 
 
-module origen;
+module <%= options[:testbench] %>;
 
-  reg finish = 0;
+  reg <%= options[:finish_signal] %> = 0;
 
-% dut.rtl_pins.each do |name, pin, options|
-%   if pin.type == :analog
-`ifdef ORIGEN_WREAL 
-  wreal <%= pin.id %>;
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
+  `ORIGEN_REAL_TYPE <%= pin.id %>;
+%     end
 `else
+%     group[1..-1].each do |pin|
   wire <%= pin.id %>;
+%     end
 `endif
 %   else
+%     group[1..-1].each do |pin|
   wire <%= pin.id %>;
+%     end
 %   end
 % end
 
@@ -278,13 +355,7 @@ module origen;
   );
 
   // Instantiate the DUT
-  <%= options[:top].sub(/\..*/, '') %> dut (
-% dut.power_pins.each do |name, pin, options|
-    .<%= pin.id %>(<%= pin.id %>),
-% end
-% dut.ground_pins.each do |name, pin, options|
-    .<%= pin.id %>(<%= pin.id %>),
-% end
+  <%= options[:top].sub(/\..*/, '') %> <%= options[:top_level_name] %> (
 % # Keep track of the primary groups seen.
 % seen_groups = []
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
@@ -303,7 +374,7 @@ module origen;
 % end
   );
 
-  debug debug ();
+  <%= options[:debug_module_name] %> <%= options[:debug_module_name] %> ();
 
   initial
   begin
@@ -319,12 +390,11 @@ module origen;
     $vcdplusmemon;
 `endif
 `ifdef ORIGEN_FSDB
-    $fsdbDumpfile("origen.fsdb");
     $fsdbDumpvars(0, "+all");
 `endif
   end
 
-  always @(posedge finish) begin
+  always @(posedge <%= options[:finish_signal] %>) begin
     $finish(2);
   end
 

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.20.6
+  version: 0.21.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-08-02 00:00:00.000000000 Z
+date: 2025-02-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.6.2
+        version: 0.6.3
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.6.2
+        version: 0.6.3
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -147,8 +147,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: 1.8.11
 requirements: []
-rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 3.1.6
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns