origen_sim 0.20.6 → 0.21.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/config/commands.rb

@@ -23,13 +23,36 @@ when "sim:build_example"
       ARGV.delete_at(index)
       Origen.environment.temporary = ARGV.delete_at(index)
     end
+    if ['cadence'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_CADENCE'
+    elsif ['synopsys', 'synopsys_verdi'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_SYNOPSIS'
+    elsif ['icarus'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_ICARUS'
+    end
+
+    clean = false
+    if ARGV.include?('--clean')
+      ARGV.delete_at(ARGV.index('--clean'))
+      clean = true
+    end
     cmd += ' ' + ARGV.join(' ') unless ARGV.empty?
+
+
     # Enable wreal pins in the DUT RTL
     cmd += '  --define ORIGEN_WREAL' if ARGV.include?('--wreal')
+    #cmd += "  --define ORIGEN_WREALAVG --sv --force_pin_type vdd:real --force_pin_type ana:real --passthrough \"-sysv_ext +.v -define ORIGEN_WREALAVG +define+ORIGEN_SIM_CADENCE #{Origen.app.root}/top.scs\"" if ARGV.include?('--wrealavg')
+    cmd += "  --define ORIGEN_WREALAVG --sv --force_pin_type vdd:real --force_pin_type ana:real --passthrough \"+define+ORIGEN_SIM_SYNOPSIS\"" if ARGV.include?('--wrealavg')
     output = `#{cmd}`
     puts output
     Origen.load_target
     dir = "simulation/default/#{tester.simulator.config[:vendor]}"
+    
+    if clean
+      puts "Cleaning directory: #{dir}"
+      FileUtils.rm_r(dir)
+    end
+    
     FileUtils.mkdir_p(dir)
     Dir.chdir dir do
       case tester.simulator.config[:vendor]
@@ -42,7 +65,10 @@ when "sim:build_example"
 
       when :cadence
         output =~ /\n(.*irun .*)\n/
-        system $1.gsub('stub', 'dut1')
+        compile_cmd = $1.gsub('stub', 'dut1')
+        compile_cmd.gsub!('origen.v', 'origen.sv') if cmd.include?('--define ORIGEN_SV')
+        puts compile_cmd.green
+        system compile_cmd
 
       when :synopsys
         if tester.simulator.config[:verdi]

data/config/shared_commands.rb

@@ -48,7 +48,7 @@ when "sim:unpack"
 when "sim:run"
   OrigenSim.run_source(ARGV[0])
   exit 0
-  
+
 #when "sim:list"
 #  require "#{Origen.root!}/lib/origen_sim/commands/pack"
 #  OrigenSim::Commands::Pack.list
@@ -60,7 +60,14 @@ else
  sim:co       Checkout a simulation snapshot
  sim:pack     Packs the snapshot into a compressed directory
  sim:unpack   Unpacks a snapshot
- sim:list     List the available snapshot packs
   EOT
+ # sim:list     List the available snapshot packs
+  
+ if OrigenTesters.respond_to?(:decompile)
+  @plugin_commands << <<-EOT
+ sim:run      Simulates the given source without using any of Origen's 'startup' collateral.
+              Requires: a decompiler for the given source and timing information setup beforehand. 
+  EOT
+ end
 
 end

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 20
-  BUGFIX = 6
+  MINOR = 21
+  BUGFIX = 0
   DEV = nil
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/ext/bridge.c

@@ -29,6 +29,7 @@ typedef struct Pin {
   int compare_wave_pos;  // Position of the pin in the compare_wave's active pin array
   int index;             // The pin's index in the pins array
   int previous_state;    // Used to keep track of whether the pin was previously driving or comparing
+  int drive_data;        // Used to hold the new drive data for this pin until needed by the drive wave
   bool capture_en;       // Used to indicated when compare data should be captured instead of compared
   bool present;          // Set to true if the pin is present in the testbench
 } Pin;
@@ -108,13 +109,14 @@ static void define_pin(char * name, char * pin_ix, char * drive_wave_ix, char *
   (*pin).compare_wave = atoi(compare_wave_ix);
   (*pin).previous_state = 0;
   (*pin).capture_en = false;
+  (*pin).drive_data = 0;
 
 
-  char * driver = (char *) malloc(strlen(name) + 16);
+  char * driver = (char *) malloc(strlen(name) + ORIGEN_SIM_TB_NAME_LEN + 7); // testbench name + . + 'pins.' + '\0'
   strcpy(driver, ORIGEN_SIM_TESTBENCH_CAT("pins."));
   strcat(driver, name);
 
-  char * data = (char *) malloc(strlen(driver) + 16);
+  char * data = (char *) malloc(strlen(driver) + 6);
   strcpy(data, driver);
   strcat(data, ".data");
   (*pin).data = vpi_handle_by_name(data, NULL);
@@ -127,25 +129,25 @@ static void define_pin(char * name, char * pin_ix, char * drive_wave_ix, char *
     (*pin).present = true;
   }
 
-  char * drive = (char *) malloc(strlen(driver) + 16);
+  char * drive = (char *) malloc(strlen(driver) + 7);
   strcpy(drive, driver);
   strcat(drive, ".drive");
   (*pin).drive = vpi_handle_by_name(drive, NULL);
   free(drive);
 
-  char * force = (char *) malloc(strlen(driver) + 16);
+  char * force = (char *) malloc(strlen(driver) + 12);
   strcpy(force, driver);
   strcat(force, ".force_data");
   (*pin).force_data = vpi_handle_by_name(force, NULL);
   free(force);
 
-  char * compare = (char *) malloc(strlen(driver) + 16);
+  char * compare = (char *) malloc(strlen(driver) + 9);
   strcpy(compare, driver);
   strcat(compare, ".compare");
   (*pin).compare = vpi_handle_by_name(compare, NULL);
   free(compare);
 
-  char * capture = (char *) malloc(strlen(driver) + 16);
+  char * capture = (char *) malloc(strlen(driver) + 9);
   strcpy(capture, driver);
   strcat(capture, ".capture");
   (*pin).capture = vpi_handle_by_name(capture, NULL);
@@ -326,9 +328,15 @@ static void drive_pin(char * index, char * val) {
   s_vpi_value v = {vpiIntVal, {0}};
 
   if ((*pin).present) {
+    // Store the pin drive data to be applied at the data edge
+    (*pin).drive_data = (val[0] - '0');
+    
     // Apply the data value to the pin's driver
-    v.value.integer = (val[0] - '0');
-    vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    if (is_drive_whole_cycle(pin)) {
+      v.value.integer = (*pin).drive_data;
+      vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    }
+    
     // Make sure not comparing
     v.value.integer = 0;
     vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
@@ -431,6 +439,7 @@ static void dont_care_pin(char * index) {
 PLI_INT32 apply_wave_event_cb(p_cb_data data) {
   s_vpi_value v = {vpiIntVal, {0}};
   s_vpi_value v2 = {vpiIntVal, {0}};
+  s_vpi_value v3 = {vpiIntVal, {0}};
 
   int * wave_ix  = (int*)(&(data->user_data[0]));
   int * event_ix = (int*)(&(data->user_data[sizeof(int)]));
@@ -486,6 +495,11 @@ PLI_INT32 apply_wave_event_cb(p_cb_data data) {
       case 'D' :
         d = 0;
         on = 1;
+        // Apply the data value to the pin's driver
+	for (int i = 0; i < (*wave).active_pin_count; i++) {
+          v3.value.integer = (*(*wave).active_pins[i]).drive_data;
+          vpi_put_value((*(*wave).active_pins[i]).data, &v3, NULL, vpiNoDelay);
+	}
         break;
       case 'X' :
         d = 0;
@@ -750,7 +764,7 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
         // Set Pattern Name
         //   a^atd_ramp_25mhz
         case 'a' :
-          handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.pattern"), NULL);
+          handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("pattern")), NULL);
           arg1 = strtok(NULL, "^");
 
           v.format = vpiStringVal;
@@ -786,7 +800,7 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
           arg1 = strtok(NULL, "^");
           arg2 = strtok(NULL, "^");
 
-          strcpy(comment, ORIGEN_SIM_TESTBENCH_CAT("debug.comments"));
+          strcpy(comment, ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("comments")));
           strcat(comment, arg1);
 
           handle = vpi_handle_by_name(comment, NULL);
@@ -989,7 +1003,7 @@ static void end_simulation() {
   s_vpi_value v;
 
   // Setting this node will cause the testbench to call $finish
-  handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("finish"), NULL);
+  handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_FINISH_SIG_NAME), NULL);
   v.format = vpiDecStrVal;
   v.value.str = "1";
   vpi_put_value(handle, &v, NULL, vpiNoDelay);
@@ -1057,7 +1071,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
   if (match_loop_open) {
     match_loop_error_count++;
 
-    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.match_errors"), NULL);
+    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("match_errors")), NULL);
     val.format = vpiIntVal;
     val.value.integer = match_loop_error_count;
     vpi_put_value(handle, &val, NULL, vpiNoDelay);
@@ -1094,7 +1108,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
 
     error_count++;
 
-    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.errors"), NULL);
+    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("errors")), NULL);
     val.format = vpiIntVal;
     val.value.integer = error_count;
     vpi_put_value(handle, &val, NULL, vpiNoDelay);

data/ext/common.h

@@ -14,6 +14,7 @@
 /// Prepends the testbench name to the signal.
 /// e.g.: TESTBENCH_CAT(pins) => TESTBENCH_NAME.pins => origen.pins
 #define ORIGEN_SIM_TESTBENCH_CAT(signal) ORIGEN_SIM_TESTBENCH_NAME "." signal
+#define ORIGEN_SIM_DEBUG_MODULE_CAT(signal) ORIGEN_SIM_DEBUG_MODULE_NAME "." signal
 
 #ifdef ENABLE_DEBUG
 /* #define DEBUG(fmt, args...) fprintf(stderr, "DEBUG: %s:%d:%s(): " fmt, \

data/ext/defines.h.erb

@@ -1,8 +1,11 @@
 #ifndef DEFINES_H
 #define DEFINES_H
 
+#define ORIGEN_FINISH_SIG_NAME "<%= options[:finish_signal] %>"
 #define ORIGEN_SIM_VERSION "<%= OrigenSim::VERSION %>"
 #define ORIGEN_SIM_TESTBENCH_NAME "<%= options[:testbench_name] %>"
+#define ORIGEN_SIM_DEBUG_MODULE_NAME "<%= options[:debug_module_name] %>"
+#define ORIGEN_SIM_TB_NAME_LEN <%= options[:testbench_name].size %>
 #define LOG_DEBUG 0
 #define LOG_INFO 1
 #define LOG_WARN 2

data/lib/origen_sim/commands/build.rb

@@ -3,7 +3,22 @@ require 'origen_sim'
 require_relative '../../../config/version'
 require 'origen_verilog'
 
-options = { incl_files: [], source_dirs: [], testbench_name: 'origen', defines: [], user_details: {}, initial_pin_states: {}, verilog_top_output_name: 'origen' }
+options = {
+  incl_files:              [],
+  source_dirs:             [],
+  testbench_name:          'origen',
+  defines:                 [],
+  user_details:            {},
+  initial_pin_states:      {},
+  forced_pin_types:        {},
+  verilog_top_output_name: 'origen',
+  file_type:               :v,
+  power_pins:              [],
+  ground_pins:             [],
+  virtual_pins:            [],
+  other_pins:              [],
+  passthrough:             []
+}
 
 # App options are options that the application can supply to extend this command
 app_options = @application_options || []
@@ -22,8 +37,9 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
     options[:source_dirs] << path
   end
-  opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t }
+  opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t; options[:file_type] = :sv }
   opts.on('--wreal', 'Enable real number modeling support on DUT pins defined as real wires (wreal)') { |t| options[:wreal] = t }
+  opts.on('--wrealavg', 'Enable real number modeling support on DUT pins defined as real wires - averaged (wrealavg)') { |t| options[:wrealavg] = t }
   opts.on('--verilog_top_output_name NAME', 'Renames the output filename from origen.v to NAME.v') do |name|
     options[:verilog_top_output_name] = name
   end
@@ -39,7 +55,25 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
     end
     (options[:initial_pin_states])[name.to_sym] = OrigenSim::INIT_PIN_STATE_MAPPING[state]
   end
-  opts.on('--include FILE' 'Specify files to include in the top verilog file.') { |f| options[:incl_files] << f }
+  opts.on('--force_pin_type PIN_AND_TYPE', 'Overwrite the pin driver discerned from DUT module') do |pin_and_type|
+    name, type = pin_and_type.split(':')
+    (options[:forced_pin_types])[name] = OrigenSim::FORCE_PIN_TYPES_MAPPING[type]
+  end
+  opts.on('--power_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are power pins, seperated by tildas') do |str_or_regex|
+    options[:power_pins] << str_or_regex
+  end
+  opts.on('--ground_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are ground pins, seperated by tildas') do |str_or_regex|
+    options[:ground_pins] << str_or_regex
+  end
+  opts.on('--virtual_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are virtual pins, seperated by tildas') do |str_or_regex|
+    options[:virtual_pins] << str_or_regex
+  end
+  opts.on('--other_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are \'other\' pins, seperated by tildas') do |str_or_regex|
+    options[:other_pins] << str_or_regex
+  end
+  opts.on('--include FILE', 'Specify files to include in the top verilog file.') { |f| options[:incl_files] << f }
+  opts.on('--vendor VENDOR', 'Specify the target vendor (Cadence, Synopsis, Icarus') { |v| options[:vendor] = v.downcase.to_sym }
+  opts.on('--passthrough SWITCHES', 'Raw switches that will be ignored by OrigenSim, but appear in the final build command') { |s| options[:passthrough] << s }
 
   # Specifying snapshot details
   opts.on('--device_name NAME', '(Snapshot Detail) Specify a device name') { |n| options[:device_name] = n }
@@ -48,6 +82,9 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('--revision_note REV_NOTE', '(Snapshot Detail) Specify a brief note on this revision of the snapshot') { |n| options[:revision_note] = n }
   opts.on('--author AUTHOR', '(Snapshot Detail) Specify the author of the snapshot (default is just Origen.current_user)') { |a| options[:author] = a }
 
+  opts.on('--finish_signal FINISH_SIGNAL', 'Specify the finish signal') { |f| options[:finish_signal] = f }
+  opts.on('--debug_module_name MOD_NAME', 'Specify the debug module name') { |d| options[:debug_module_name] = d }
+
   # User-defined snapshot details
   opts.on('--USER_DETAIL NAME_AND_VALUE', 'Specify custom user-defined details to build into the snapshot details. Format as NAME:VALUE, e.g.: \'--USER_DETAIL BUILD_TYPE:RTL\'') do |name_and_value|
     name, value = name_and_value.split(':')
@@ -68,8 +105,41 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-h', '--help', 'Show this message') { puts opts; exit 0 }
 end
 
+build_cmd = 'origen sim:build ' + ARGV.map do |arg|
+  # Command-line-ify some of the argument values.
+  if arg.include?(' ') || (arg[0] == '/' && arg[1] == '/' && arg.size > 1)
+    # if the argument is a string, wrap it in quotes.
+    # Likewise, if the argument looks like a regex, wrap it in quotes as well.
+    arg = "\"#{arg}\""
+  end
+
+  # If the argument includes any !s, escape them
+  arg = arg.gsub('!', '\!')
+
+  arg
+end.join(' ')
 opt_parser.parse! ARGV
 
+options.select { |k, v| [:power_pins, :ground_pins, :virtual_pins, :other_pins].include?(k) }.each do |k, pins_or_regexes|
+  options[k] = pins_or_regexes.map { |input| input.split('~') }.flatten.map do |p|
+    if p.start_with?('/') && p.end_with?('/')
+      Regexp.new(p[1..-2])
+    else
+      p
+    end
+  end
+end
+
+options[:forced_pin_types] = options[:forced_pin_types].map do |pin_or_regex, type|
+  if pin_or_regex.start_with?('/') && pin_or_regex.end_with?('/')
+    # run this as a regex, not as a single pin name
+    # Cut out the leading / and trailing / characters though
+    [Regexp.new(pin_or_regex.to_s[1..-2]), type]
+  else
+    [pin_or_regex, type]
+  end
+end.to_h
+
 def _exit_fail_
   if $_testing_build_return_dut_
     return nil
@@ -115,7 +185,7 @@ end
 
 rtl_top_module = mod.name
 
-mod.to_top_level # Creates dut
+mod.to_top_level(options) # Creates dut
 
 # Update the pins with any settings from the command line
 options[:initial_pin_states].each do |pin, state|
@@ -138,15 +208,22 @@ else
                            quiet:             true,
                            preserve_target:   true,
                            options:           {
-                             vendor:            :cadence,
+                             vendor:            options[:vendor],
                              top:               dut.name,
+                             testbench_name:    options[:testbench_name],
                              incl:              options[:incl_files],
                              device_name:       options[:device_name],
                              revision:          options[:revision],
                              revision_note:     options[:revision_note],
                              parent_tb_version: options[:testbench_version],
                              user_details:      options[:user_details],
-                             author:            options[:author]
+                             author:            options[:author],
+                             build_cmd:         build_cmd,
+                             file_type:         options[:file_type],
+                             testbench:         options[:testbench_name] || 'origen',
+                             top_level_name:    options[:top_level_name] || 'dut',
+                             finish_signal:     options[:finish_signal] || 'finish',
+                             debug_module_name: options[:debug_module_name] || 'debug'
                            }
 
   Origen.app.runner.launch action:            :compile,
@@ -182,6 +259,16 @@ else
     )
   end
 
+  if options[:wrealavg]
+    SYNOPSYS_SWITCHES += %w(
+      +define+ORIGEN_WREALAVG
+      -realport
+      -sverilog
+      -lca
+      -xlrm\ coerce_nettype
+    )
+  end
+
   SYNOPSYS_DVE_SWITCHES = SYNOPSYS_SWITCHES + %w(
     +define+ORIGEN_VPD
   )
@@ -211,96 +298,108 @@ else
     )
   end
 
-  puts
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Icarus Verilog'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Compile the VPI extension using the following command:'
-  puts
-  puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  puts "  #{output_directory}/#{output_name} \\"
-  puts '  -o origen.vvp \\'
-  puts '  -DORIGEN_VCD'
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
-  puts
-  puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
-  puts
-  puts "  #{output_directory}/origen.vpi"
-  puts '  origen.vvp'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Synopsys VCS w/ DVE Waveviewer'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  SYNOPSYS_DVE_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:wrealavg]
+    CADENCE_SWITCHES += %w(
+      +define+ORIGEN_WREALAVG
+    )
   end
+
   puts
-  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_DVE_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
-  puts
-  puts '  simv'
-  puts '  simv.daidir'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Synopsys VCS w/ Verdi Waveviewer'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  SYNOPSYS_VERDI_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:vendor].nil? || options[:vendor] == :icarus
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Icarus Verilog'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Compile the VPI extension using the following command:'
+    puts
+    puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    puts "  #{output_directory}/#{output_name} \\"
+    puts '  -o origen.vvp \\'
+    puts '  -DORIGEN_VCD'
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
+    puts
+    puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
+    puts
+    puts "  #{output_directory}/origen.vpi"
+    puts '  origen.vvp'
   end
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_VERDI_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
-  puts
-  puts '  simv'
-  puts '  simv.daidir'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Cadence Incisive (irun)'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  CADENCE_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:vendor].nil? || options[:vendor] == :synopsis
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Synopsys VCS w/ DVE Waveviewer'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    SYNOPSYS_DVE_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_DVE_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
+    puts
+    puts '  simv'
+    puts '  simv.daidir'
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Synopsys VCS w/ Verdi Waveviewer'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    SYNOPSYS_VERDI_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_VERDI_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
+    puts
+    puts '  simv'
+    puts '  simv.daidir'
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Cadence Incisive (irun)'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+  end
+  if options[:vendor].nil? || options[:vendor] == :cadence
+    puts
+    CADENCE_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} -incdir #{Pathname.new(rtl_top).dirname} " + CADENCE_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
+    puts
+    puts '  INCA_libs'
+    puts
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Testbench and VPI extension created!'
+    puts
+    puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
+    puts
+    puts "  #{output_directory}/#{rtl_top_module}.rb"
+    puts
+    puts 'See above for what to do now to create an Origen-enabled simulation object for your particular simulator.'
   end
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} -incdir #{Pathname.new(rtl_top).dirname} " + CADENCE_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
-  puts
-  puts '  INCA_libs'
-  puts
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Testbench and VPI extension created!'
-  puts
-  puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
-  puts
-  puts "  #{output_directory}/#{rtl_top_module}.rb"
-  puts
-  puts 'See above for what to do now to create an Origen-enabled simulation object for your particular simulator.'
   puts
 
 end

data/lib/origen_sim/origen/pins/pin.rb

@@ -57,7 +57,7 @@ module Origen
 
       alias_method :_orig_drive, :drive
       def drive(*args)
-        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+        if _analog_pin_? && simulation_running? && tester.simulator.real?
           tester.poke("#{driver_net}.drive_en", 1)
           tester.poke("#{driver_net}.drive", args.first + 0.0)
         else
@@ -68,11 +68,11 @@ module Origen
 
       alias_method :_orig_assert, :assert
       def assert(*args)
-        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+        if _analog_pin_? && simulation_running? && tester.simulator.real?
           drive_enabled = tester.peek("#{driver_net}.drive_en").to_i
           if drive_enabled == 1
-            tester.poke("#{driver_net}.drive_en", 0)
-            tester.cycle
+            # tester.poke("#{driver_net}.drive_en", 0)
+            # tester.cycle
           end
           measured = tester.peek("#{driver_net}.pin", true)
           # Could implement checking/limits here in future