origen_sim 0.20.6 → 0.21.0

data/lib/origen_sim/origen/top_level.rb

@@ -6,18 +6,27 @@ module Origen
     # Optionally pass in a type: option set to either :analog or :digital to
     # have only the pins with that type returned
     def rtl_pins(options = {})
+      _add_rtl_pin_ = lambda do |name, pin, opts, p|
+        options = {}
+        unless pin.rtl_name.to_s.downcase == 'nc' ||
+               (opts[:type] && pin.type && opts[:type] != pin.type) ||
+               (pin.meta[:origen_sim_init_pin_state] && pin.meta[:origen_sim_init_pin_state] == -2)
+          if pin.primary_group
+            options[:group] = true
+          end
+          p << [name, pin, options]
+        end
+      end
+
+      pin_roles = [:pins, :power_pins, :ground_pins, :virtual_pins, :other_pins]
       @rtl_pins ||= {}
       @rtl_pins[options[:type]] ||= begin
         opts = options.dup
         p = []
-        pins.each do |name, pin|
-          options = {}
-          unless pin.rtl_name.to_s.downcase == 'nc' ||
-                 (opts[:type] && pin.type && opts[:type] != pin.type)
-            if pin.primary_group
-              options[:group] = true
-            end
-            p << [name, pin, options]
+        # pins.each do |name, pin|
+        pin_roles.each do |role|
+          dut.send(role).each do |name, pin|
+            _add_rtl_pin_.call(name, pin, opts, p)
           end
         end
         p

data/lib/origen_sim/origen_testers/api.rb

@@ -26,7 +26,7 @@ module OrigenTesters
       if @sim_capture || @sim_delay
         fail 'Nesting of sim_capture and/or sim_delay blocks is not yet supported!'
       end
-      Origen::OrgFile.open(id, path: OrigenSim.capture_dir) do |org_file|
+      Origen::OrgFile.open(id, path: (options[:path] || OrigenSim.capture_dir)) do |org_file|
         @org_file = org_file
         if update_capture?
           @sim_delay = true

data/lib/origen_sim/simulator.rb

@@ -21,7 +21,7 @@ module OrigenSim
 
     # These config attributes are accepted by OrigenSim, but cannot be
     # 'Marshal-ed'.
-    NON_DATA_CONFIG_ATTRIBUTES = [:post_process_run_cmd]
+    NON_DATA_CONFIG_ATTRIBUTES = [:post_process_run_cmd, :post_process_view_wave_cmd, :post_process_probe_cmd]
 
     TIMESCALES = { -15 => '1fs',
                    -14 => '10fs',
@@ -86,6 +86,26 @@ module OrigenSim
       config[:post_process_run_cmd]
     end
 
+    def post_process_view_wave_cmd
+      config[:post_process_view_wave_cmd]
+    end
+
+    def post_process_probe_cmd
+      config[:post_process_probe_cmd]
+    end
+
+    def post_process_probe_cmd?
+      !post_process_probe_cmd.nil?
+    end
+
+    def force_config_update?
+      !!config[:force_config_update]
+    end
+
+    def debug_path
+      config[:debug_module_path] || 'debug'
+    end
+
     def fetch_simulation_objects(options = {})
       sid = options[:id] || id
       ldir = "#{Origen.root}/simulation/#{sid}"
@@ -166,8 +186,8 @@ module OrigenSim
       clear_artifacts
 
       # Add any artifacts in the given artifact path
-      if Dir.exist?(default_artifact_dir)
-        default_artifact_dir.children.each { |a| artifact(a.basename.to_s, target: a) }
+      if Dir.exist?(self.class.default_artifact_dir)
+        self.class.default_artifact_dir.children.each { |a| artifact(a.basename.to_s, target: a) }
       end
 
       # Add any artifacts from the target-specific path (simulation/<target>/artifacts). Files of the same name
@@ -197,7 +217,7 @@ module OrigenSim
       self
     end
 
-    def default_artifact_dir
+    def self.default_artifact_dir
       # Removed this from a constant at the top of the file since it gave boot errors when the file was
       # being required while Origen.app was still loading
       Pathname("#{Origen.app.root}/simulation/application/artifacts")
@@ -212,7 +232,7 @@ module OrigenSim
     end
 
     def target_artifact_dir
-      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/#{id}/artifacts")
+      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/").join("#{id}/artifacts")
     end
 
     def artifact_run_dir
@@ -253,9 +273,11 @@ module OrigenSim
     # be checked into your Origen app's repository
     def compiled_dir
       @compiled_dir ||= begin
-        d = "#{Origen.root}/simulation/#{id}/#{config[:vendor]}"
-        FileUtils.mkdir_p(d)
-        d
+        config[:compiled_dir] || begin
+          d = "#{Origen.root}/simulation/#{id}/#{config[:vendor]}"
+          FileUtils.mkdir_p(d)
+          d
+        end
       end
     end
 
@@ -323,24 +345,46 @@ module OrigenSim
       when :cadence
         input_file = "#{tmp_dir}/#{wave_file_basename}.tcl"
         if !File.exist?(input_file) || config_changed?
+          probe_cmd = "probe -create -shm #{testbench_top} -depth all -database waves"
+          if post_process_probe_cmd?
+            probe_cmd = post_process_probe_cmd.call(probe_cmd, self, fast_probe: false)
+          end
+
           Origen.app.runner.launch action:            :compile,
                                    files:             "#{Origen.root!}/templates/probe.tcl.erb",
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: :all },
+                                   options:           { dir:        wave_dir,
+                                                        wave_file:  wave_file_basename,
+                                                        force:      config[:force],
+                                                        setup:      config[:setup],
+                                                        tcl_inputs: config[:tcl_inputs],
+                                                        probe_cmd:  probe_cmd
+                                                      },
                                    output_file_name:  "#{wave_file_basename}.tcl",
                                    preserve_target:   true
         end
+
         input_file_fast = "#{tmp_dir}/#{wave_file_basename}_fast.tcl"
         if !File.exist?(input_file_fast) || config_changed?
           fast_probe_depth = config[:fast_probe_depth] || 1
+          probe_cmd = "probe -create -shm #{testbench_top} -depth #{fast_probe_depth} -database waves"
+          if post_process_probe_cmd?
+            probe_cmd = post_process_probe_cmd.call(probe_cmd, self, fast_probe: true)
+          end
+
           Origen.app.runner.launch action:            :compile,
                                    files:             "#{Origen.root!}/templates/probe.tcl.erb",
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: fast_probe_depth },
+                                   options:           { dir:       wave_dir,
+                                                        wave_file: wave_file_basename,
+                                                        force:     config[:force],
+                                                        setup:     config[:setup],
+                                                        probe_cmd: probe_cmd
+                                                      },
                                    output_file_name:  "#{wave_file_basename}_fast.tcl",
                                    preserve_target:   true
         end
@@ -353,10 +397,11 @@ module OrigenSim
         cmd += " -nclibdirpath #{compiled_dir}"
 
       when :synopsys
+        syn_comp_n = config[:synopsys_compiled_name] || 'simv'
         if configuration[:verdi]
-          cmd = "#{compiled_dir}/simv +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{id}/#{wave_file_basename}.fsdb +memcbk +vcsd"
+          cmd = "#{compiled_dir}/#{syn_comp_n} +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{id}/#{wave_file_basename}.fsdb +memcbk +vcsd"
         else
-          cmd = "#{compiled_dir}/simv +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
+          cmd = "#{compiled_dir}/#{syn_comp_n} +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
         end
 
       when :generic
@@ -478,6 +523,10 @@ module OrigenSim
         Origen.log.warn "OrigenSim does not know the command to view waveforms for vendor :#{config[:vendor]}!"
 
       end
+
+      cmd = post_process_view_wave_cmd.call(cmd, self) if post_process_view_wave_cmd
+      fail "OrigenSim: :post_process_view_wave_cmd returned object of class #{cmd.class}. Must return a String." unless cmd.is_a?(String)
+
       cmd
     end
 
@@ -894,13 +943,13 @@ module OrigenSim
 
     def error(message)
       simulation.logged_errors = true
-      poke "#{testbench_top}.debug.errors", error_count + 1
+      poke "#{testbench_top}.#{debug_path}.errors", error_count + 1
       log message, :error
     end
 
     # Returns the current simulation error count
     def error_count
-      peek("#{testbench_top}.debug.errors").to_i
+      peek("#{testbench_top}.#{debug_path}.errors").to_i
     end
 
     # Returns the current value of the given net, or nil if the given path does not
@@ -1079,7 +1128,7 @@ module OrigenSim
 
     # Returns true if the config has been changed since the last time we called save_config_signature
     def config_changed?
-      Origen.app.session.origen_sim["#{id}_config"] != config.except(*NON_DATA_CONFIG_ATTRIBUTES)
+      config[:force_config_update] || Origen.app.session.origen_sim["#{id}_config"] != config.except(*NON_DATA_CONFIG_ATTRIBUTES)
     end
 
     # Locally saves a signature for the current config, this will cause config_changed? to return false
@@ -1142,7 +1191,7 @@ module OrigenSim
 
     def match_errors
       if dut_version > '0.15.0'
-        peek("#{testbench_top}.debug.match_errors").to_i
+        peek("#{testbench_top}.#{debug_path}.match_errors").to_i
       else
         peek("#{testbench_top}.pins.match_errors").to_i
       end
@@ -1153,7 +1202,7 @@ module OrigenSim
       unless val.nil?
         # All zeros seems to be what an empty string is returned from the VPI,
         # Otherwise, break the string up into 8-bit chunks and decode the ASCII>
-        val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join)
+        val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).select { |char| char != '00000000' }.collect { |char| char.to_i(2).chr }.join)
       end
       val
     end
@@ -1167,7 +1216,7 @@ module OrigenSim
     end
 
     def marker=(val)
-      poke("#{testbench_top}.debug.marker", val)
+      poke("#{testbench_top}.#{debug_path}.marker", val)
     end
 
     def start_read_reg_transaction
@@ -1204,14 +1253,73 @@ module OrigenSim
       end
     end
 
+    # Returns true if the snapshot has been compiled with some kind of REAL support.
+    # Not picky about what type of real support though.
+    def real?
+      @real ||= begin
+        if dut_version > '0.19.0' && dut_version < '0.20.3'
+          # These versions of OrigenSim only support WREAL
+          if wreal?
+            @real_type = :wreal
+            true
+          else
+            false
+          end
+        elsif dut_version >= '0.20.3'
+          # These versions support multiple REAL types.
+          if peek_str("#{testbench_top}.#{debug_path}.real_type").nil?
+            @real_type = false
+          else
+            @real_type = peek_str("#{testbench_top}.#{debug_path}.real_type").to_sym
+            peek("#{testbench_top}.#{debug_path}.real_enabled").to_i == 1
+          end
+        else
+          # Older version don't support REAL at all
+          @real_type = false
+          false
+        end
+      end
+    end
+    alias_method :real_enabled?, :real?
+
+    # Returns the type of REAL support or <code>false</code> if no REAL support is enabled.
+    # @note Calling {#real?} will set the value of <code>real_type</code> appropriately
+    def real_type
+      @real_type || begin
+        real?
+        @real_type
+      end
+    end
+
     # Returns true if the snapshot has been compiled with WREAL support
     def wreal?
-      return @wreal if defined?(@wreal)
-      @wreal = (dut_version > '0.19.0' &&
-                peek("#{testbench_top}.debug.wreal_enabled").to_i == 1)
+      if dut_version > '0.19.0' && dut_version < '0.20.3'
+        @wreal ||= peek("#{testbench_top}.#{debug_path}.wreal_enabled").to_i == 1
+      elsif dut_version >= '0.20.3'
+        puts 'wreal?'.cyan
+        puts @real_type.class
+        puts @real_type[0]
+        puts @real_type.to_s.size
+        puts 'wreal'.size
+        puts @real_type.to_s == 'wreal'
+        (@real_type || begin
+          real?
+          @real_type
+        end) == :wreal
+      else
+        false
+      end
     end
     alias_method :wreal_enabled?, :wreal?
 
+    def wrealavg?
+      (@real_type || begin
+        real?
+        @real_type
+      end) == :wrealavg
+    end
+    alias_method :wrealavg_enabled?, :wrealavg?
+
     private
 
     # Will be called when the simulator has aborted due to the max error count being exceeded

data/lib/origen_sim/tester.rb

@@ -41,9 +41,25 @@ module OrigenSim
       end
       @sync_pins.map do |pin|
         if @sync_cycles.size == 1
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")[0]
+          b = simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")[0]
+          if b.is_a?(Integer)
+            b
+          else
+            Origen.log.warning "The data captured on pin #{pin.id} was undefined (X or Z), the captured value is not correct!"
+            0
+          end
         else
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory").to_i[(@sync_cycles - 1)..0]
+          val = 0
+          mem = simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")
+          @sync_cycles.times do |i|
+            b = mem[i]
+            if b.is_a?(Integer)
+              val |= b << i
+            else
+              Origen.log.warning "The data captured on cycle #{i} of pin #{pin.id} was undefined (X or Z), the captured value is not correct!"
+            end
+          end
+          val
         end
       end
     end
@@ -65,11 +81,15 @@ module OrigenSim
       simulator.flush(*args)
     end
 
-    def set_timeset(name, period_in_ns)
+    def set_timeset(name, period_in_ns = nil)
       super
+
       # Need to remove this once OrigenTesters does it
-      dut.timeset = name
-      dut.current_timeset_period = period_in_ns
+      # OrigenTesters with decompiler supports this.
+      if period_in_ns
+        dut.timeset = name
+        dut.current_timeset_period = period_in_ns
+      end
 
       # Now update the simulator with the new waves
       simulator.on_timeset_changed
@@ -166,25 +186,21 @@ module OrigenSim
       if options[:pin2]
         expected_val2 = options[:state2] == :high ? 1 : 0
       end
-      timed_out = true
-      10.times do
-        (timeout_in_cycles / 10).cycles
+      matched = false
+      start_cycle = cycle_count
+      resolution = match_loop_resolution(timeout_in_cycles, options)
+      until matched || cycle_count > start_cycle + timeout_in_cycles
+        resolution.cycles
         current_val = simulator.peek("dut.#{pin.rtl_name}").to_i
         if options[:pin2]
           current_val2 = simulator.peek("dut.#{options[:pin2].rtl_name}").to_i
-          if current_val == expected_val || current_val2 == expected_val2
-            timed_out = false
-            break
-          end
+          matched = current_val == expected_val || current_val2 == expected_val2
         else
-          if current_val == expected_val
-            timed_out = false
-            break
-          end
+          matched = current_val == expected_val
         end
       end
       # Final assertion to make the pattern fail if the loop timed out
-      if timed_out
+      unless matched
         pin.restore_state do
           pin.assert!(expected_val)
         end
@@ -207,23 +223,22 @@ module OrigenSim
       else
         match_conditions.add(&block)
       end
-      timed_out = true
+      matched = false
+      start_cycle = cycle_count
+      resolution = match_loop_resolution(timeout_in_cycles, options)
       simulator.match_loop do
-        10.times do
-          (timeout_in_cycles / 10).cycles
+        until matched || cycle_count > start_cycle + timeout_in_cycles
+          resolution.cycles
           # Consider the match resolved if any condition can execute without generating errors
-          if match_conditions.any? do |condition|
+          matched = match_conditions.any? do |condition|
             e = simulator.match_errors
             condition.call
             e == simulator.match_errors
           end
-            timed_out = false
-            break
-          end
         end
       end
       # Final execution to make the pattern fail if the loop timed out
-      if timed_out
+      unless matched
         if fail_conditions.instance_variable_get(:@block_args).empty?
           match_conditions.each(&:call)
         else
@@ -232,6 +247,27 @@ module OrigenSim
       end
     end
 
+    # @api private
+    def match_loop_resolution(timeout_in_cycles, options)
+      if options[:resolution]
+        if options[:resolution].is_a?(Hash)
+          return time_to_cycles(options[:resolution])
+        else
+          return options[:resolution]
+        end
+      else
+        # Used to use the supplied timeout / 10, thinking that the supplied number would be
+        # roughly how long it would take. However, found that when users didn't know the timeout
+        # they would just put in really large numbers, like 1sec, which would mean we would not
+        # check until 100ms for an operation that might be done after 100us.
+        # So now if the old default comes out less than the new one, then use it, otherwise use
+        # the newer more fine-grained default.
+        old_default = timeout_in_cycles / 10
+        new_default = time_to_cycles(time_in_us: 100)
+        return old_default < new_default ? old_default : new_default
+      end
+    end
+
     def wait(*args)
       super
       if Origen.running_interactively? ||

data/lib/origen_sim.rb

@@ -64,6 +64,15 @@ module OrigenSim
     'disconnected'   => -2
   }
 
+  FORCE_PIN_TYPES_MAPPING = {
+    'real'    => :analog,
+    'ana'     => :analog,
+    'analog'  => :analog,
+
+    'dig'     => :digital,
+    'digital' => :digital
+  }
+
   def self.__instantiate_simulator__
     @simulator ||= Simulator.new
   end
@@ -216,6 +225,10 @@ module OrigenSim
     Origen.load_application
     Origen.app.load_target!
 
+    unless tester.simulator?
+      Origen.app!.fail!(message: 'OrigenSim.run cannot be used when the simulator is not the current tester!')
+    end
+
     # Start up the simulator and run whatever's in the target block.
     # After the block completes, shutdown the simulator
     tester.simulator.setup_simulation(name)

data/lib/origen_sim_dev/dut.rb

@@ -35,6 +35,10 @@ module OrigenSimDev
           w.drive 0, at: 0
           w.drive :data, at: 'period / 2'
         end
+        # Generate drive timing that has only a data event which isn't at t0
+        t.wave :din_port do |w|
+          w.drive :data, at: 'period / 2'
+        end
       end
 
       add_reg :dr, 0x0, size: 66 do |reg|

data/pattern/test.rb

@@ -127,7 +127,7 @@ Pattern.create do
       peek("dut.real_val", 1.25)
     end
 
-    if tester.simulator.wreal?
+    if tester.simulator.wreal? || tester.simulator.wrealavg?
       ss "Test analog pin API by ramping dut.vdd"
       v = 0
       dut.power_pin(:vdd).drive!(v)
@@ -218,6 +218,13 @@ Pattern.create do
     60.cycles
   end
 
+  ss "Test timing implementation - drive timing, single data event only, not at t0"
+  dut.pins(:din_port).dont_care
+  tester.cycle
+  dut.pins(:din_port).drive! 1
+  dut.pins(:din_port).drive! 0
+  dut.pins(:din_port).drive! 1
+
   ss "Test the command works with static vectors"
   dut.pin(:done).assert!(1)
   dut.pin(:done).dont_care
@@ -262,7 +269,7 @@ Pattern.create do
   5.cycles
   dut.pin(:done).assert!(0)
   dut.pin(:done).dont_care
-  tester.wait match: true, time_in_cycles: 2000 do
+  tester.wait match: true, time_in_s: 2 do
     dut.pin(:done).assert!(1)
   end
   dut.pin(:done).assert!(1)

data/templates/origen_guides/simulation/patterns.md.erb

@@ -28,6 +28,14 @@ normally have two options:
 Both of these are fully supported by OrigenSim, see the
 [Timing and Waiting guide](<%= path "guides/pattern/timing" %>) for more information on these APIs.
 
+<div class="alert alert-info" role="alert"> <strong>A Note on Match Loops</strong>
+  <br>
+  When waiting for a match, the DUT will be polled every 100us by default or timeout / 10 if that
+  is less than 100us.
+  If you need it to poll more often (at the expense of simulation speed) then a `:resolution` option can
+  be supplied in the same way as described for the `sim_delay` method below.
+</div>
+
 However, if your pattern generation flow is going to be supported by simulation, then you also have
 a third option - to derive the required wait time from the simulation itself.
 

data/templates/probe.tcl.erb

@@ -1,6 +1,5 @@
 database -open waves -into <%= options[:dir] %>/<%= options[:wave_file] %> -default -event
-probe -create -shm origen -depth <%= options[:depth] %> -database waves
-#probe -create -assertions -transaction origen -depth all -database waves
+<%= options[:probe_cmd] %>
 % Array(options[:tcl_inputs]).each do |line|
 <%= line %>
 % end