origen_arm_debug 0.10.1 → 1.0.0.pre1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/config/application.rb +3 -3
- data/config/boot.rb +5 -0
- data/config/commands.rb +14 -9
- data/config/version.rb +4 -4
- data/lib/origen_arm_debug.rb +7 -11
- data/lib/origen_arm_debug/ap.rb +14 -0
- data/lib/origen_arm_debug/ap_controller.rb +27 -0
- data/lib/origen_arm_debug/dap.rb +89 -0
- data/lib/origen_arm_debug/dap_controller.rb +14 -0
- data/lib/origen_arm_debug/dp_controller.rb +17 -0
- data/lib/origen_arm_debug/helpers.rb +28 -0
- data/lib/origen_arm_debug/jtag_ap.rb +10 -0
- data/lib/origen_arm_debug/jtag_ap_controller.rb +6 -0
- data/lib/origen_arm_debug/jtag_dp.rb +59 -0
- data/lib/origen_arm_debug/jtag_dp_controller.rb +140 -0
- data/lib/origen_arm_debug/mem_ap.rb +33 -283
- data/lib/origen_arm_debug/mem_ap_controller.rb +81 -0
- data/lib/origen_arm_debug/sw_dp.rb +65 -0
- data/lib/origen_arm_debug/sw_dp_controller.rb +47 -0
- data/lib/{origen_arm_debug → origen_arm_debug_dev}/dut.rb +11 -15
- data/lib/origen_arm_debug_dev/dut_jtag.rb +32 -0
- data/lib/{origen_arm_debug → origen_arm_debug_dev}/dut_swd.rb +7 -1
- data/pattern/workout.rb +61 -0
- data/templates/web/index.md.erb +16 -4
- metadata +38 -48
- data/config/development.rb +0 -17
- data/config/environment.rb +0 -3
- data/config/users.rb +0 -19
- data/lib/origen_arm_debug/driver.rb +0 -113
- data/lib/origen_arm_debug/dut_jtag.rb +0 -19
- data/lib/origen_arm_debug/swj_dp.rb +0 -426
- data/pattern/read_write_reg.rb +0 -33
- data/pattern/read_write_reg_jtag.rb +0 -17
- data/pattern/read_write_reg_swd.rb +0 -22
@@ -1,304 +1,54 @@
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require 'origen_arm_debug/mem_ap_controller'
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module OrigenARMDebug
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#
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# SWJ-DP object.
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class MemAP
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# Memory Access Port (MEM-AP)
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class MemAP < AP
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include Origen::Model
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#
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#
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#
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#
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# Latency to write a memory resource
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attr_reader :latency
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# Wait states for data to be transferred from Memory Resource to DRW on
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# read request. Should be added to apreg_access_wait for complete transaction
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# time of memory read (read data path: memory->drw->rdbuff)
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attr_reader :apmem_access_wait
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def initialize(options = {})
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super
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@latency = options[:latency] || 0
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@apmem_access_wait = options[:apmem_access_wait] || 0
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# ARM Debug Interface v5.1
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reg :csw, 0x00, size: 32, reset: 0x00000000 do |reg|
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reg :csw, 0x0 do |reg|
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reg.bit 31, :dbg_sw_enable
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reg.bit 30..24, :prot
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reg.bit 23, :spiden
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reg.bit 11..8, :mode
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reg.bit 7, :tr_in_prog
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reg.bit 6, :device_en
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reg.bit 5..4, :addr_inc
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reg.bit 2..0, :size
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end
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add_reg :tar, 0x04, 32, data: { pos: 0, bits: 32 }, reset: 0xffffffff
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add_reg :drw, 0x0C, 32, data: { pos: 0, bits: 32 }, reset: 0x00000000
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end
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# Shortcut name to SWJ-DP Debug Port
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def debug_port
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parent.swj_dp
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end
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alias_method :dp, :debug_port
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# -----------------------------------------------------------------------------
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# User API
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# -----------------------------------------------------------------------------
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def write_register(reg_or_val, options = {})
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if reg_or_val.respond_to?(:data)
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addr = reg_or_val.addr
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data = reg_or_val.data
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else
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addr = options[:address]
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data = reg_or_val
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end
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size = options[:size] || 32
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msg = "Arm Debug: Shift in data to write: #{data.to_hex}"
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options = { arm_debug_comment: msg }.merge(options)
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set_size(size)
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set_addr(addr)
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reg(:drw).data = get_wdata(size, addr, data)
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debug_port.write_ap(reg(:drw).address, reg(:drw).data, options)
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increment_addr
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cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
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"addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
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"data=0x#{reg(:drw).data.to_s(16).rjust(size / 4, '0')}"
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apply_latency
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end
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def read_register(reg_or_val, options = {})
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if reg_or_val.respond_to?(:data)
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addr = reg_or_val.addr
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data = reg_or_val.data
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options[:mask] = reg_or_val.enable_mask(:read)
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options[:store] = reg_or_val.enable_mask(:store)
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else
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addr = options[:address]
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data = reg_or_val
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end
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size = options[:size] || 32
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msg = 'Arm Debug: Shift out data for reading'
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options = { arm_debug_comment: msg }.merge(options)
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set_size(size)
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set_addr(addr)
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reg(:drw).data = get_rdata(size, addr, data)
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debug_port.read_ap(reg(:drw).address, reg(:drw).data, options)
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increment_addr
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cc "MEM-AP(#{@name}): R-#{size.to_s(10)}: "\
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"addr=0x#{addr.to_s(16).rjust(size / 4, '0')}"
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apply_latency
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end
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# -----------------------------------------------------------------------------
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# Legacy Support (to be phased out)
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# -----------------------------------------------------------------------------
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# Method to read from a mem_ap register (DEPRECATED)
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#
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# @param [Integer] addr Address of register to be read from
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# @param [Hash] options Options to customize the operation
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#
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# @example
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# # don't care what data actually is
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# mem_ap.read(0x2000000, size: 32)
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#
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# # expect read data to be = 0x5a5a5a5a
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# mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a)
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#
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# # expect read data to be = 0xXXXXXX5a (mask out all bits except [7:0])
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# mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a, r_mask: 0x000000ff)
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#
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# Returns nothing.
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def read(addr, options = {})
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# Warn caller that this method is being deprecated
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msg = 'Use mem_ap.read_register(reg_or_val, options) instead of read(addr, options)'
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Origen.deprecate msg
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# Convert old style (addr, options) to (data, options) before passing on to new method
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data = options.delete(:edata) || 0x00000000
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mask = options.delete(:r_mask) || 0xFFFFFFFF
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options = { address: addr, mask: mask }.merge(options)
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if mask == 'store'
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options = { store: 0xFFFFFFFF }.merge(options)
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read_register(data, options)
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else
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read_register(data, options)
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end
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end
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# Method to write to a mem_ap register (DEPRECATED)
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#
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# @param [Integer] addr Address of register to be read from
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# @param [Integer] wdata Data to be written
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# @param [Hash] options Options to customize the operation
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#
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# @example
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# mem_ap.write(0x2000000, 0xc3c3a5a5, size: 32)
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#
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# Returns nothing.
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def write(addr, wdata, options = {});
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# Warn caller that this method is being deprecated
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msg = 'Use mem_ap.write_register(reg_or_val, options) instead of write(addr, wdata, options)'
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Origen.deprecate msg
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# Convert old style (addr, wdata, options) to (data, options) before passing on to new method
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data = wdata
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options = { address: addr }.merge(options)
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write_register(data, options)
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end
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# Method to write and then read from a mem_ap register (DEPRECATED)
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#
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# @param [Integer] addr Address of register to be read from
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# @param [Integer] wdata Data to be written
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# @param [Hash] options Options to customize the operation
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#
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# @example
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# # don't care what read-back data actually is
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# mem_ap.write_read(0x2000000, 0xc3c3a5a5, size: 32)
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#
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# # expect read-back data to be same as write data = 0xc3c3a5a5
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# mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5)
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#
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# # expect read-back data to be = 0xXXXXXXa5 (mask out all bits except [7:0])
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# mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5, r_mask: 0x000000ff)
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#
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# Returns nothing.
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def write_read(addr, wdata, options = {})
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# Warn caller that this method is being deprecated
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msg = 'Use mem_ap.write_read_register(reg_or_val, options) instead of write_read(addr, options)'
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Origen.deprecate msg
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# Convert old style (addr, wdata, options) to (data, options) before passing on to new method
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data = wdata
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mask = options.delete(:r_mask) || 0xFFFFFFFF
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options = { address: addr, mask: mask }.merge(options)
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write_register(data, options)
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data = options[:edata] || wdata
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read_register(data, options)
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end
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# -----------------------------------------------------------------------------
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# Support Code
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# -----------------------------------------------------------------------------
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private
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# Sets the size of the data (by writing to the CSW size bits). It will only
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# write to the size if the size from the previous transaction has changed
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#
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# @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
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def set_size(size)
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case size
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when 8 then new_size = 0b00
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when 16 then new_size = 0b01
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when 32 then new_size = 0b10
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reg.bit 5..4, :addr_inc
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reg.bit 2..0, :size
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end
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reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
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# Doesn't really reset to all 1's, but just to make sure the address
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# optimization logic does not kick in on the first transaction
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add_reg :tar, 0x04, reset: 0xFFFFFFFF
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add_reg :drw, 0x0C, reset: :undefined
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add_reg :bd0, 0x10, reset: :undefined
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add_reg :bd1, 0x14, reset: :undefined
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add_reg :bd2, 0x18, reset: :undefined
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add_reg :bd3, 0x1C, reset: :undefined
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reg
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debug_port.write_ap(reg(:csw).address, reg(:csw).data)
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reg :cfg, 0xF4, access: :ro do |reg|
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reg.bit 0, :big_endian
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end
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end
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# Sets the addr of the transaction.
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#
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# @param [Integer] addr Address of data to be read from or written to
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def set_addr(addr)
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arm_debug_comment = "Arm Debug: Shift in read/write address: #{addr.to_hex}"
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options = { arm_debug_comment: arm_debug_comment }
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reg :base, 0xF8, access: :ro do |reg|
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reg.bit 31..12, :baseaddr
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reg.bit 1, :format, reset: 1
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reg.bit 0, :entry_present
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end
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reg(:tar).data = addr;
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end
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# Increment the address for the next transaction.
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def increment_addr
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if reg(:csw).bits(:addr_inc).data == 1
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case reg(:csw).bits(:size)
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when 0 then reg(:tar).data += 1 # Increment single
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when 1 then reg(:tar).data += 2 # Increment single
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when 2 then reg(:tar).data += 4 # Increment single
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end
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elsif reg(:csw).bits(:addr_inc).data == 2
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reg(:tar).data += 4 # Increment packed
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end
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if reg(:csw).bits(:addr_inc) && ((reg(:tar).data & 0xfffffc00) == 0xffffffff)
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# reset tar when attempting to increment past 1kB boundary
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reg(:tar).data = 0xffffffff
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end
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end
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# Create a bit-wise read-data based on size, address and rdata parameters.
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#
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# @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
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# @param [Integer] addr Address of data to be read from or written to
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# @param [Integer] rdata Full data for read, used to create nibble read data
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def get_rdata(size, addr, rdata)
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addr_1_0 = addr & 0x00000003
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case size
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when 8
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case addr_1_0
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when 0 then rdata = 0x000000ff & rdata
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when 1 then rdata = 0x000000ff & (rdata >> 8)
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when 2 then rdata = 0x000000ff & (rdata >> 16)
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when 3 then rdata = 0x000000ff & (rdata >> 24)
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end
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when 16
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case addr_1_0
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when 0 then rdata = 0x0000ffff & rdata
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when 2 then rdata = 0x0000ffff & (rdata >> 16)
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end
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when 32
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rdata = rdata
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end
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rdata
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end
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# Create a bit-wise read-data based on size, address and wdata parameters.
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#
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# @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
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# @param [Integer] addr Address of data to be read from or written to
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# @param [Integer] wdata Full data for write, used to create nibble write data
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def get_wdata(size, addr, wdata);
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addr_1_0 = addr & 0x00000003
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case size
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when 8
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case addr_1_0
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when 0 then wdata = 0x000000ff & wdata
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when 1 then wdata = 0x0000ff00 & (wdata << 8)
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when 2 then wdata = 0x00ff0000 & (wdata << 16)
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when 3 then wdata = 0xff000000 & (wdata << 24)
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end
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when 16
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case addr_1_0
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when 0 then wdata = 0x0000ffff & wdata
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when 2 then wdata = 0xffff0000 & (wdata << 16)
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end
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when 32
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wdata = wdata
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end
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294
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-
wdata
|
295
|
-
end
|
296
50
|
|
297
|
-
|
298
|
-
#
|
299
|
-
# @param [Hash] options Options to customize the operation
|
300
|
-
def apply_latency(options = {})
|
301
|
-
Origen.tester.cycle(repeat: parent.latency)
|
51
|
+
add_reg :idr, 0xFC, access: :ro
|
302
52
|
end
|
303
53
|
end
|
304
54
|
end
|
@@ -0,0 +1,81 @@
|
|
1
|
+
module OrigenARMDebug
|
2
|
+
class MemAPController < APController
|
3
|
+
def write_register(reg_or_val, options = {})
|
4
|
+
if reg_or_val.try(:owner) == model
|
5
|
+
log "Write MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{reg_or_val.data.to_hex}" do
|
6
|
+
parent.dp.write_register(reg_or_val, options)
|
7
|
+
apreg_access_wait.cycles
|
8
|
+
end
|
9
|
+
else
|
10
|
+
|
11
|
+
addr = extract_address(reg_or_val, options)
|
12
|
+
data = extract_data(reg_or_val, options)
|
13
|
+
ovl = options.delete(:overlay)
|
14
|
+
unless ovl.nil?
|
15
|
+
Origen.log.warn '[ARM Debug] Overlays only supported through register model'
|
16
|
+
end
|
17
|
+
|
18
|
+
log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
|
19
|
+
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
20
|
+
tar.write!(addr) unless tar.data == addr
|
21
|
+
drw.reset
|
22
|
+
drw.overlay(nil)
|
23
|
+
drw.copy_all(reg_or_val)
|
24
|
+
drw.write!(options)
|
25
|
+
latency.cycles
|
26
|
+
end
|
27
|
+
increment_addr
|
28
|
+
end
|
29
|
+
end
|
30
|
+
|
31
|
+
def read_register(reg_or_val, options = {})
|
32
|
+
if reg_or_val.try(:owner) == model
|
33
|
+
apacc_wait_states = reg_or_val.name == :drw ? (apmem_access_wait + apreg_access_wait) : apreg_access_wait
|
34
|
+
log "Read MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{Origen::Utility.read_hex(reg_or_val)}" do
|
35
|
+
parent.dp.read_register(reg_or_val, options.merge(apacc_wait_states: apacc_wait_states))
|
36
|
+
end
|
37
|
+
|
38
|
+
else
|
39
|
+
|
40
|
+
addr = extract_address(reg_or_val, options)
|
41
|
+
|
42
|
+
log "Read MEM-AP (#{model.name}) address #{addr.to_hex}: #{Origen::Utility.read_hex(reg_or_val)}" do
|
43
|
+
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
44
|
+
unless tar.data == addr
|
45
|
+
tar.write!(addr)
|
46
|
+
end
|
47
|
+
drw.reset
|
48
|
+
drw.overlay(nil)
|
49
|
+
drw.copy_all(reg_or_val)
|
50
|
+
parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
|
51
|
+
end
|
52
|
+
increment_addr
|
53
|
+
end
|
54
|
+
end
|
55
|
+
|
56
|
+
def address_increment_enabled?
|
57
|
+
d = csw.addr_inc.data
|
58
|
+
d == 1 || d == 2
|
59
|
+
end
|
60
|
+
|
61
|
+
private
|
62
|
+
|
63
|
+
# Update the model if the address is auto-incrementing on chip
|
64
|
+
def increment_addr
|
65
|
+
if address_increment_enabled?
|
66
|
+
case csw.bits(:size).data
|
67
|
+
when 0 then tar.data += 1 # Increment single
|
68
|
+
when 1 then tar.data += 2 # Increment single
|
69
|
+
when 2 then tar.data += 4 # Increment single
|
70
|
+
end
|
71
|
+
elsif csw.addr_inc.data == 2
|
72
|
+
tar.data += 4 # Increment packed
|
73
|
+
end
|
74
|
+
|
75
|
+
# Reset tar if just crossed a 1kB boundary
|
76
|
+
if address_increment_enabled? && (tar[9..0].data == 0)
|
77
|
+
tar.reset
|
78
|
+
end
|
79
|
+
end
|
80
|
+
end
|
81
|
+
end
|
@@ -0,0 +1,65 @@
|
|
1
|
+
require 'origen_arm_debug/sw_dp_controller'
|
2
|
+
module OrigenARMDebug
|
3
|
+
class SW_DP
|
4
|
+
include Origen::Model
|
5
|
+
|
6
|
+
def initialize(options = {})
|
7
|
+
reg :idcode, 0, access: :ro do |reg|
|
8
|
+
reg.bit 31..28, :version
|
9
|
+
reg.bit 27..12, :partno
|
10
|
+
reg.bit 11..1, :designer
|
11
|
+
reg.bit 0, :bit0, reset: 1
|
12
|
+
end
|
13
|
+
|
14
|
+
reg :abort, 0, access: :wo do |reg|
|
15
|
+
reg.bit 4, :orunerrclr
|
16
|
+
reg.bit 3, :wderrclr
|
17
|
+
reg.bit 2, :stkerrclr
|
18
|
+
reg.bit 1, :stkcmpclr
|
19
|
+
reg.bit 0, :dapabort
|
20
|
+
end
|
21
|
+
|
22
|
+
reg :ctrlstat, 0x4 do |reg|
|
23
|
+
reg.bit 31, :csyspwrupack
|
24
|
+
reg.bit 30, :csyspwrupreq
|
25
|
+
reg.bit 29, :cdbgpwrupack
|
26
|
+
reg.bit 28, :cdbgpwrupreq
|
27
|
+
reg.bit 27, :cdbgrstack
|
28
|
+
reg.bit 26, :cdbgrstreq
|
29
|
+
reg.bit 23..12, :trncnt
|
30
|
+
reg.bit 11..8, :masklane
|
31
|
+
reg.bit 7, :wdataerr
|
32
|
+
reg.bit 6, :readok
|
33
|
+
reg.bit 5, :stickyerr
|
34
|
+
reg.bit 4, :stickycmp
|
35
|
+
reg.bit 3..2, :trnmode
|
36
|
+
reg.bit 1, :stickyorun
|
37
|
+
reg.bit 0, :orundetect
|
38
|
+
end
|
39
|
+
|
40
|
+
reg :wcr, 0x4 do |reg|
|
41
|
+
reg.bit 9..8, :turnround
|
42
|
+
reg.bit 7..6, :wiremode
|
43
|
+
reg.bit 2..0, :prescaler
|
44
|
+
end
|
45
|
+
|
46
|
+
add_reg :resend, 0x8, access: :ro
|
47
|
+
|
48
|
+
reg :select, 0x8, access: :wo do |reg|
|
49
|
+
reg.bit 31..24, :apsel
|
50
|
+
reg.bit 7..4, :apbanksel
|
51
|
+
reg.bit 0, :ctrlsel
|
52
|
+
end
|
53
|
+
|
54
|
+
add_reg :rdbuff, 0xC, access: :ro
|
55
|
+
end
|
56
|
+
|
57
|
+
def select
|
58
|
+
reg(:select)
|
59
|
+
end
|
60
|
+
|
61
|
+
def abort
|
62
|
+
reg(:abort)
|
63
|
+
end
|
64
|
+
end
|
65
|
+
end
|