origen_arm_debug 0.10.1 → 1.0.0.pre1

data/lib/origen_arm_debug/mem_ap.rb

@@ -1,304 +1,54 @@
+require 'origen_arm_debug/mem_ap_controller'
 module OrigenARMDebug
-  # Object that defines the API necessary to perform MEM-AP transactions.  Requires
-  #  a top-level protocol be defined as well as a top-level instantiation of an
-  #  SWJ-DP object.
-  class MemAP
+  # Memory Access Port (MEM-AP)
+  class MemAP < AP
     include Origen::Model
 
-    # Initialize class variables
-    #
-    # @param [Hash] options Options to customize the operation
-    #
-    # @example
-    #   DUT.new.arm_debug.mem_ap
-    #
+    # Latency to write a memory resource
+    attr_reader :latency
+
+    # Wait states for data to be transferred from Memory Resource to DRW on
+    #   read request.  Should be added to apreg_access_wait for complete transaction
+    #   time of memory read (read data path: memory->drw->rdbuff)
+    attr_reader :apmem_access_wait
+
     def initialize(options = {})
-      instantiate_registers
-    end
+      super
+      @latency = options[:latency] || 0
+      @apmem_access_wait = options[:apmem_access_wait] || 0
 
-    def instantiate_registers(options = {})
-      # ARM Debug Interface v5.1
-      reg :csw, 0x00, size: 32, reset: 0x00000000 do |reg|
+      reg :csw, 0x0 do |reg|
         reg.bit 31,     :dbg_sw_enable
         reg.bit 30..24, :prot
         reg.bit 23,     :spiden
         reg.bit 11..8,  :mode
         reg.bit 7,      :tr_in_prog
         reg.bit 6,      :device_en
-        reg.bit 5..4,   :addr_inc, reset: 0b00
-        reg.bit 2..0,   :size, reset: 0b000
-      end
-
-      add_reg :tar, 0x04, 32, data: { pos: 0, bits: 32 }, reset: 0xffffffff
-      add_reg :drw, 0x0C, 32, data: { pos: 0, bits: 32 }, reset: 0x00000000
-    end
-
-    # Shortcut name to SWJ-DP Debug Port
-    def debug_port
-      parent.swj_dp
-    end
-    alias_method :dp, :debug_port
-
-    # -----------------------------------------------------------------------------
-    # User API
-    # -----------------------------------------------------------------------------
-    def write_register(reg_or_val, options = {})
-      if reg_or_val.respond_to?(:data)
-        addr = reg_or_val.addr
-        data = reg_or_val.data
-      else
-        addr = options[:address]
-        data = reg_or_val
-      end
-      size = options[:size] || 32
-
-      msg = "Arm Debug: Shift in data to write: #{data.to_hex}"
-      options = { arm_debug_comment: msg }.merge(options)
-
-      set_size(size)
-      set_addr(addr)
-      reg(:drw).data = get_wdata(size, addr, data)
-      debug_port.write_ap(reg(:drw).address, reg(:drw).data, options)
-      increment_addr
-
-      cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
-        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
-        "data=0x#{reg(:drw).data.to_s(16).rjust(size / 4, '0')}"
-
-      apply_latency
-    end
-
-    def read_register(reg_or_val, options = {})
-      if reg_or_val.respond_to?(:data)
-        addr = reg_or_val.addr
-        data = reg_or_val.data
-        options[:mask] = reg_or_val.enable_mask(:read)
-        options[:store] = reg_or_val.enable_mask(:store)
-      else
-        addr = options[:address]
-        data = reg_or_val
-      end
-      size = options[:size] || 32
-
-      msg = 'Arm Debug: Shift out data for reading'
-      options = { arm_debug_comment: msg }.merge(options)
-      set_size(size)
-      set_addr(addr)
-      reg(:drw).data = get_rdata(size, addr, data)
-      debug_port.read_ap(reg(:drw).address, reg(:drw).data, options)
-      increment_addr
-
-      cc "MEM-AP(#{@name}): R-#{size.to_s(10)}: "\
-        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}"
-
-      apply_latency
-    end
-
-    # -----------------------------------------------------------------------------
-    # Legacy Support (to be phased out)
-    # -----------------------------------------------------------------------------
-
-    # Method to read from a mem_ap register (DEPRECATED)
-    #
-    # @param [Integer] addr Address of register to be read from
-    # @param [Hash] options Options to customize the operation
-    #
-    # @example
-    #   # don't care what data actually is
-    #   mem_ap.read(0x2000000, size: 32)
-    #
-    #   # expect read data to be = 0x5a5a5a5a
-    #   mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a)
-    #
-    #   # expect read data to be = 0xXXXXXX5a (mask out all bits except [7:0])
-    #   mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a, r_mask: 0x000000ff)
-    #
-    # Returns nothing.
-    def read(addr, options = {})
-      # Warn caller that this method is being deprecated
-      msg = 'Use mem_ap.read_register(reg_or_val, options) instead of read(addr, options)'
-      Origen.deprecate msg
-
-      # Convert old style (addr, options) to (data, options) before passing on to new method
-      data = options.delete(:edata) || 0x00000000
-      mask = options.delete(:r_mask) || 0xFFFFFFFF
-      options = { address: addr, mask: mask }.merge(options)
-      if mask == 'store'
-        options = { store: 0xFFFFFFFF }.merge(options)
-        read_register(data, options)
-      else
-        read_register(data, options)
-      end
-    end
-
-    # Method to write to a mem_ap register (DEPRECATED)
-    #
-    # @param [Integer] addr Address of register to be read from
-    # @param [Integer] wdata Data to be written
-    # @param [Hash] options Options to customize the operation
-    #
-    # @example
-    #   mem_ap.write(0x2000000, 0xc3c3a5a5, size: 32)
-    #
-    # Returns nothing.
-    def write(addr, wdata, options = {});
-      # Warn caller that this method is being deprecated
-      msg = 'Use mem_ap.write_register(reg_or_val, options) instead of write(addr, wdata, options)'
-      Origen.deprecate msg
-
-      # Convert old style (addr, wdata, options) to (data, options) before passing on to new method
-      data = wdata
-      options = { address: addr }.merge(options)
-      write_register(data, options)
-    end
-
-    # Method to write and then read from a mem_ap register (DEPRECATED)
-    #
-    # @param [Integer] addr Address of register to be read from
-    # @param [Integer] wdata Data to be written
-    # @param [Hash] options Options to customize the operation
-    #
-    # @example
-    #   # don't care what read-back data actually is
-    #   mem_ap.write_read(0x2000000, 0xc3c3a5a5, size: 32)
-    #
-    #   # expect read-back data to be same as write data = 0xc3c3a5a5
-    #   mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5)
-    #
-    #   # expect read-back data to be = 0xXXXXXXa5 (mask out all bits except [7:0])
-    #   mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5, r_mask: 0x000000ff)
-    #
-    # Returns nothing.
-    def write_read(addr, wdata, options = {})
-      # Warn caller that this method is being deprecated
-      msg = 'Use mem_ap.write_read_register(reg_or_val, options) instead of write_read(addr, options)'
-      Origen.deprecate msg
-
-      # Convert old style (addr, wdata, options) to (data, options) before passing on to new method
-      data = wdata
-      mask = options.delete(:r_mask) || 0xFFFFFFFF
-      options = { address: addr, mask: mask }.merge(options)
-      write_register(data, options)
-      data = options[:edata] || wdata
-      read_register(data, options)
-    end
-
-    # -----------------------------------------------------------------------------
-    # Support Code
-    # -----------------------------------------------------------------------------
-
-    private
-
-    # Sets the size of the data (by writing to the CSW size bits).  It will only
-    #   write to the size if the size from the previous transaction has changed
-    #
-    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
-    def set_size(size)
-      case size
-        when 8 then  new_size = 0b00
-        when 16 then new_size = 0b01
-        when 32 then new_size = 0b10
+        reg.bit 5..4,   :addr_inc
+        reg.bit 2..0,   :size
       end
+      reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
 
-      if (reg(:csw).data == 0x00000000)
-        debug_port.read_ap(reg(:csw).address, reg(:csw).data, mask: 0x00000000)
-        reg(:csw).data = 0x23000040
-      end
+      # Doesn't really reset to all 1's, but just to make sure the address
+      # optimization logic does not kick in on the first transaction
+      add_reg :tar, 0x04, reset: 0xFFFFFFFF
+      add_reg :drw, 0x0C, reset: :undefined
+      add_reg :bd0, 0x10, reset: :undefined
+      add_reg :bd1, 0x14, reset: :undefined
+      add_reg :bd2, 0x18, reset: :undefined
+      add_reg :bd3, 0x1C, reset: :undefined
 
-      if (reg(:csw).bits(:size).data != new_size)
-        reg(:csw).bits(:size).data = new_size
-        debug_port.write_ap(reg(:csw).address, reg(:csw).data)
+      reg :cfg, 0xF4, access: :ro do |reg|
+        reg.bit 0, :big_endian
       end
-    end
-
-    # Sets the addr of the transaction.
-    #
-    # @param [Integer] addr Address of data to be read from or written to
-    def set_addr(addr)
-      arm_debug_comment = "Arm Debug: Shift in read/write address: #{addr.to_hex}"
-      options = { arm_debug_comment: arm_debug_comment }
 
-      if (reg(:tar).data != addr)
-        debug_port.write_ap(reg(:tar).address, addr, options)
+      reg :base, 0xF8, access: :ro do |reg|
+        reg.bit 31..12, :baseaddr
+        reg.bit 1, :format, reset: 1
+        reg.bit 0, :entry_present
       end
-      reg(:tar).data = addr;
-    end
-
-    # Increment the address for the next transaction.
-    def increment_addr
-      if reg(:csw).bits(:addr_inc).data == 1
-        case reg(:csw).bits(:size)
-          when 0 then reg(:tar).data += 1   # Increment single
-          when 1 then reg(:tar).data += 2   # Increment single
-          when 2 then reg(:tar).data += 4   # Increment single
-        end
-      elsif reg(:csw).bits(:addr_inc).data == 2
-        reg(:tar).data += 4                 # Increment packed
-      end
-
-      if reg(:csw).bits(:addr_inc) && ((reg(:tar).data & 0xfffffc00) == 0xffffffff)
-        # reset tar when attempting to increment past 1kB boundary
-        reg(:tar).data = 0xffffffff
-      end
-    end
-
-    # Create a bit-wise read-data based on size, address and rdata parameters.
-    #
-    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
-    # @param [Integer] addr Address of data to be read from or written to
-    # @param [Integer] rdata Full data for read, used to create nibble read data
-    def get_rdata(size, addr, rdata)
-      addr_1_0 = addr & 0x00000003
-      case size
-        when 8
-          case addr_1_0
-            when 0 then rdata = 0x000000ff & rdata
-            when 1 then rdata = 0x000000ff & (rdata >> 8)
-            when 2 then rdata = 0x000000ff & (rdata >> 16)
-            when 3 then rdata = 0x000000ff & (rdata >> 24)
-          end
-        when 16
-          case addr_1_0
-            when 0 then rdata = 0x0000ffff & rdata
-            when 2 then rdata = 0x0000ffff & (rdata >> 16)
-          end
-        when 32
-          rdata = rdata
-      end
-      rdata
-    end
-
-    # Create a bit-wise read-data based on size, address and wdata parameters.
-    #
-    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
-    # @param [Integer] addr Address of data to be read from or written to
-    # @param [Integer] wdata Full data for write, used to create nibble write data
-    def get_wdata(size, addr, wdata);
-      addr_1_0 = addr & 0x00000003
-      case size
-        when 8
-          case addr_1_0
-            when 0 then wdata = 0x000000ff & wdata
-            when 1 then wdata = 0x0000ff00 & (wdata << 8)
-            when 2 then wdata = 0x00ff0000 & (wdata << 16)
-            when 3 then wdata = 0xff000000 & (wdata << 24)
-          end
-        when 16
-          case addr_1_0
-            when 0 then wdata = 0x0000ffff & wdata
-            when 2 then wdata = 0xffff0000 & (wdata << 16)
-          end
-        when 32
-          wdata = wdata
-      end
-      wdata
-    end
 
-    # Apply delay as specified by the top-level attribute 'latency' (defaults to 0).
-    #
-    # @param [Hash] options Options to customize the operation
-    def apply_latency(options = {})
-      Origen.tester.cycle(repeat: parent.latency)
+      add_reg :idr, 0xFC, access: :ro
     end
   end
 end

data/lib/origen_arm_debug/mem_ap_controller.rb

@@ -0,0 +1,81 @@
+module OrigenARMDebug
+  class MemAPController < APController
+    def write_register(reg_or_val, options = {})
+      if reg_or_val.try(:owner) == model
+        log "Write MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{reg_or_val.data.to_hex}" do
+          parent.dp.write_register(reg_or_val, options)
+          apreg_access_wait.cycles
+        end
+      else
+
+        addr = extract_address(reg_or_val, options)
+        data = extract_data(reg_or_val, options)
+        ovl = options.delete(:overlay)
+        unless ovl.nil?
+          Origen.log.warn '[ARM Debug] Overlays only supported through register model'
+        end
+
+        log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
+          csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
+          tar.write!(addr) unless tar.data == addr
+          drw.reset
+          drw.overlay(nil)
+          drw.copy_all(reg_or_val)
+          drw.write!(options)
+          latency.cycles
+        end
+        increment_addr
+      end
+    end
+
+    def read_register(reg_or_val, options = {})
+      if reg_or_val.try(:owner) == model
+        apacc_wait_states = reg_or_val.name == :drw ? (apmem_access_wait + apreg_access_wait) : apreg_access_wait
+        log "Read MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{Origen::Utility.read_hex(reg_or_val)}" do
+          parent.dp.read_register(reg_or_val, options.merge(apacc_wait_states: apacc_wait_states))
+        end
+
+      else
+
+        addr = extract_address(reg_or_val, options)
+
+        log "Read MEM-AP (#{model.name}) address #{addr.to_hex}: #{Origen::Utility.read_hex(reg_or_val)}" do
+          csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
+          unless tar.data == addr
+            tar.write!(addr)
+          end
+          drw.reset
+          drw.overlay(nil)
+          drw.copy_all(reg_or_val)
+          parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
+        end
+        increment_addr
+      end
+    end
+
+    def address_increment_enabled?
+      d = csw.addr_inc.data
+      d == 1 || d == 2
+    end
+
+    private
+
+    # Update the model if the address is auto-incrementing on chip
+    def increment_addr
+      if address_increment_enabled?
+        case csw.bits(:size).data
+          when 0 then tar.data += 1   # Increment single
+          when 1 then tar.data += 2   # Increment single
+          when 2 then tar.data += 4   # Increment single
+        end
+      elsif csw.addr_inc.data == 2
+        tar.data += 4                 # Increment packed
+      end
+
+      # Reset tar if just crossed a 1kB boundary
+      if address_increment_enabled? && (tar[9..0].data == 0)
+        tar.reset
+      end
+    end
+  end
+end

data/lib/origen_arm_debug/sw_dp.rb

@@ -0,0 +1,65 @@
+require 'origen_arm_debug/sw_dp_controller'
+module OrigenARMDebug
+  class SW_DP
+    include Origen::Model
+
+    def initialize(options = {})
+      reg :idcode, 0, access: :ro do |reg|
+        reg.bit 31..28, :version
+        reg.bit 27..12, :partno
+        reg.bit 11..1, :designer
+        reg.bit 0, :bit0, reset: 1
+      end
+
+      reg :abort, 0, access: :wo do |reg|
+        reg.bit 4, :orunerrclr
+        reg.bit 3, :wderrclr
+        reg.bit 2, :stkerrclr
+        reg.bit 1, :stkcmpclr
+        reg.bit 0, :dapabort
+      end
+
+      reg :ctrlstat, 0x4 do |reg|
+        reg.bit 31, :csyspwrupack
+        reg.bit 30, :csyspwrupreq
+        reg.bit 29, :cdbgpwrupack
+        reg.bit 28, :cdbgpwrupreq
+        reg.bit 27, :cdbgrstack
+        reg.bit 26, :cdbgrstreq
+        reg.bit 23..12, :trncnt
+        reg.bit 11..8, :masklane
+        reg.bit 7, :wdataerr
+        reg.bit 6, :readok
+        reg.bit 5, :stickyerr
+        reg.bit 4, :stickycmp
+        reg.bit 3..2, :trnmode
+        reg.bit 1, :stickyorun
+        reg.bit 0, :orundetect
+      end
+
+      reg :wcr, 0x4 do |reg|
+        reg.bit 9..8, :turnround
+        reg.bit 7..6, :wiremode
+        reg.bit 2..0, :prescaler
+      end
+
+      add_reg :resend, 0x8, access: :ro
+
+      reg :select, 0x8, access: :wo do |reg|
+        reg.bit 31..24, :apsel
+        reg.bit 7..4, :apbanksel
+        reg.bit 0, :ctrlsel
+      end
+
+      add_reg :rdbuff, 0xC, access: :ro
+    end
+
+    def select
+      reg(:select)
+    end
+
+    def abort
+      reg(:abort)
+    end
+  end
+end