origen_arm_debug 0.10.1 → 1.0.0.pre1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
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-  data.tar.gz: 5ff8f7838d12c691a28d5b32129762391e0c0413
+  metadata.gz: 06b61282c9205efdb49a4a8cd5532e9dc718b7f6
+  data.tar.gz: 525f141f5fb7002bb9af7809ae71af1e2a71cdc1
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+  data.tar.gz: da718b20deba251a76896c7c10031b9b9c154f1dbb4da68fc5634328c16823f651b906d759093fe61b169f5e16de17aea8db22db2e21236715f73c901cc2726b

data/config/application.rb

@@ -23,14 +23,14 @@ class OrigenARMDebugApplication < Origen::Application
     # Auto correct violations where possible whenever 'origen lint' is run 
     auto_correct: true,  
     # Limit the testing for large legacy applications 
-    level: :easy, 
+    #level: :easy, 
     # Run on these directories/files by default 
     #files: ["lib", "config/application.rb"], 
   } 
   
   # Ensure that all tests pass before allowing a release to continue 
   def validate_release 
-    if !system("origen examples") || !system("origen specs") 
+    if !system("origen examples") # || !system("origen specs") 
       puts "Sorry but you can't release with failing tests, please fix them and try again." 
       exit 1 
     else 
@@ -42,7 +42,7 @@ class OrigenARMDebugApplication < Origen::Application
   def before_deploy_site 
     Dir.chdir Origen.root do 
       system "origen examples -c" 
-      system "origen specs -c" 
+      # system "origen specs -c" 
       dir = "#{Origen.root}/web/output/coverage"        
       FileUtils.remove_dir(dir, true) if File.exists?(dir)  
       system "mv #{Origen.root}/coverage #{dir}" 

data/config/boot.rb

@@ -0,0 +1,5 @@
+require "origen_arm_debug"
+
+require "origen_arm_debug_dev/dut"
+require "origen_arm_debug_dev/dut_jtag"
+require "origen_arm_debug_dev/dut_swd"

data/config/commands.rb

@@ -17,20 +17,18 @@ aliases ={
 # Now branch to the specific task code
 case @command
 
-when "specs"
-  require "rspec"
-  exit RSpec::Core::Runner.run(['spec'])
+# when "specs"
+#   require "rspec"
+#   exit RSpec::Core::Runner.run(['spec'])
 
-when "examples"  
+when "examples"    # , "test"  
   Origen.load_application
   status = 0
   
   # Pattern generator tests
-  ARGV = %w(read_write_reg -t debug -r approved)
+  ARGV = %w(workout -t jtag -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
-  ARGV = %w(read_write_reg_jtag -t jtag -r approved)
-  load "#{Origen.top}/lib/origen/commands/generate.rb"
-  ARGV = %w(read_write_reg_swd -t swd -r approved)
+  ARGV = %w(workout -t swd -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
     
   if Origen.app.stats.changed_files == 0 &&
@@ -44,6 +42,12 @@ when "examples"
      status = 1
   end
   puts
+#  if @command == "test"
+#    Origen.app.unload_target!
+#    require "rspec"
+#    result = RSpec::Core::Runner.run(['spec'])
+#    status = status == 1 ? 1 : result
+#  end
   exit status
 
 # Always leave an else clause to allow control to fall back through to the
@@ -52,8 +56,9 @@ when "examples"
 # origen -h, you can do this be assigning the required text to @application_commands
 # before handing control back to Origen. Un-comment the example below to get started.
 else
+ #specs        Run the specs (unit tests), -c will enable coverage
+ #test         Run both specs and examples, -c will enable coverage
   @application_commands = <<-EOT
- specs        Run the specs (unit tests), -c will enable coverage
  examples     Run the examples (tests), -c will enable coverage
   EOT
 

data/config/version.rb

@@ -1,8 +1,8 @@
 module OrigenARMDebug
-  MAJOR = 0
-  MINOR = 10
-  BUGFIX = 1
-  DEV = nil
+  MAJOR = 1
+  MINOR = 0
+  BUGFIX = 0
+  DEV = 1
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_arm_debug.rb

@@ -3,14 +3,10 @@ require_relative '../config/application.rb'
 require 'origen_jtag'
 require 'origen_swd'
 
-# Include this module to add a ARM Debug driver to your class
-module OrigenARMDebug
-  autoload :Driver, 'origen_arm_debug/driver'
-  autoload :SWJ_DP, 'origen_arm_debug/swj_dp'
-  autoload :MemAP,  'origen_arm_debug/mem_ap'
-
-  # Returns an instance of the OrigenARMDebug::Driver
-  # def arm_debug
-  #  @arm_debug ||= Driver.new(self)
-  # end
-end
+require 'origen_arm_debug/helpers'
+require 'origen_arm_debug/dap'
+require 'origen_arm_debug/jtag_dp'
+require 'origen_arm_debug/sw_dp'
+require 'origen_arm_debug/ap.rb'
+require 'origen_arm_debug/mem_ap'
+require 'origen_arm_debug/jtag_ap'

data/lib/origen_arm_debug/ap.rb

@@ -0,0 +1,14 @@
+require 'origen_arm_debug/ap_controller'
+module OrigenARMDebug
+  # Generic Access Port (AP)
+  class AP
+    include Origen::Model
+
+    # Wait states for data to be transferred from AP-Reg to RDBUFF (on read)
+    attr_reader :apreg_access_wait
+
+    def initialize(options = {})
+      @apreg_access_wait = options[:apreg_access_wait] || 0
+    end
+  end
+end

data/lib/origen_arm_debug/ap_controller.rb

@@ -0,0 +1,27 @@
+module OrigenARMDebug
+  class APController
+    include Origen::Controller
+    include Helpers
+
+    def write_register(reg_or_val, options = {})
+      if reg_or_val.try(:owner) == model
+        log "Write AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{reg_or_val.data.to_hex}" do
+          parent.dp.write_register(reg_or_val)
+          apreg_access_wait.cycles
+        end
+      else
+        fail 'No Resource-specific transport defined for MDM-AP (#model.name})'
+      end
+    end
+
+    def read_register(reg_or_val, options = {})
+      if reg_or_val.try(:owner) == model
+        log "Read AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{Origen::Utility.read_hex(reg_or_val)}" do
+          parent.dp.read_register(reg_or_val, apacc_wait_states: apreg_access_wait)
+        end
+      else
+        fail 'No Resource-specific transport defined for MDM-AP (#model.name})'
+      end
+    end
+  end
+end

data/lib/origen_arm_debug/dap.rb

@@ -0,0 +1,89 @@
+require 'origen_arm_debug/dap_controller'
+module OrigenARMDebug
+  # This is the top-level model that instantiates the DP and APs
+  class DAP
+    include Origen::Model
+
+    attr_reader :dps, :mem_aps, :jtag_aps, :ext_aps
+
+    def initialize(options = {})
+      @dps = []
+      @mem_aps = []         # Array of MEM-APs
+      @jtag_aps = []        # Array of JTAG-APs
+      @ext_aps = []         # Array of 'extension' APs
+      instantiate_subblocks(options)
+    end
+
+    def instantiate_subblocks(options = {})
+      if options[:swd] || parent.respond_to?(:swd)
+        dps << sub_block(:sw_dp, class_name: 'OrigenARMDebug::SW_DP')
+      end
+
+      if options[:jtag] || parent.respond_to?(:jtag)
+        dps << sub_block(:jtag_dp, class_name: 'OrigenARMDebug::JTAG_DP')
+      end
+
+      Array(options[:mem_aps]).each do |name, base_address|
+        if base_address.is_a?(Hash)
+          ap_opts = { class_name: 'OrigenARMDebug::MemAP' }.merge(base_address)
+        else
+          ap_opts = { class_name: 'OrigenARMDebug::MemAP', base_address: base_address }
+        end
+
+        add_ap(name, ap_opts)
+      end
+
+      Array(options[:jtag_aps]).each do |name, base_address|
+        if base_address.is_a?(Hash)
+          ap_opts = { class_name: 'OrigenARMDebug::JTAGAP' }.merge(base_address)
+        else
+          ap_opts = { class_name: 'OrigenARMDebug::JTAGAP', base_address: base_address }
+        end
+
+        add_ap(name, ap_opts)
+      end
+
+      Array(options[:aps]).each do |name, opts|
+        if opts.is_a?(Hash)
+          klass = opts.delete(:class_name)
+          addr = opts.delete(:base_address)
+          if klass.nil? || addr.nil?
+            fail "[ARM DEBUG] Error: Must specify class_name and base_address if using 'aps' hash to define APs"
+          end
+          ap_opts = { class_name: klass, base_address: addr }.merge(opts)
+        else
+          fail "[ARM DEBUG] Error: Must specify class_name and base_address if using 'aps' hash to define APs"
+        end
+
+        add_ap(name, ap_opts)
+      end
+    end
+
+    # Method to add additional Access Ports (MEM-AP)
+    #
+    # @param [Integer] name Short name for mem_ap that is being created
+    # @param [Hash] options Implemenation specific details
+    #
+    # @examples
+    #   arm_debug.add_ap('alt_ahbapi', { class_name: 'OrigenARMDebug::MemAP', base_address: 0x02000000 })
+    #
+    def add_ap(name, options)
+      domain name.to_sym
+      ap = sub_block(name.to_sym, options)
+
+      if options[:class_name] == 'OrigenARMDebug::MemAP'
+        mem_aps << ap
+      elsif options[:class_name] == 'OrigenARMDebug::JTAGAP'
+        jtag_aps << ap
+      else
+        ext_aps << ap
+      end
+    end
+
+    # Returns an array containing all APs
+    def aps
+      mem_aps + jtag_aps + ext_aps
+    end
+  end
+  Driver = DAP # For legacy API compatibility
+end

data/lib/origen_arm_debug/dap_controller.rb

@@ -0,0 +1,14 @@
+module OrigenARMDebug
+  class DAPController
+    include Origen::Controller
+    include Helpers
+
+    # Returns the currently enabled DP (or the only DP if only one
+    # of them).
+    # If no dp is enabled before calling this, it will choose the
+    # SW_DP by default.
+    def dp
+      dps.first
+    end
+  end
+end

data/lib/origen_arm_debug/dp_controller.rb

@@ -0,0 +1,17 @@
+module OrigenARMDebug
+  # Common methods shared between the SW and JTAG DP controllers
+  module DPController
+    # Alias for the ctrlstat register
+    def ctrl_stat
+      ctrlstat
+    end
+
+    # @api private
+    def select_ap_reg(reg)
+      address = reg.address & 0xFFFF_FFF0
+      if model.select.data != address
+        model.select.write!(address)
+      end
+    end
+  end
+end

data/lib/origen_arm_debug/helpers.rb

@@ -0,0 +1,28 @@
+module OrigenARMDebug
+  # Generic helper methods shared by the various controllers
+  module Helpers
+    def extract_data(reg_or_val, options = {})
+      if reg_or_val.respond_to?('data')
+        reg_or_val.data
+      else
+        reg_or_val
+      end
+    end
+
+    def extract_address(reg_or_val, options = {})
+      addr = options[:address] || options[:addr]
+      return addr if addr
+      return reg_or_val.address if reg_or_val.respond_to?('address')
+      return reg_or_val.addr if reg_or_val.respond_to?('addr')
+      fail 'No address given, if supplying a data value instead of a register object, you must supply an :address option'
+    end
+
+    def log(msg)
+      cc "[ARM Debug] #{msg}"
+      if block_given?
+        yield
+        cc "[ARM Debug] /#{msg}"
+      end
+    end
+  end
+end

data/lib/origen_arm_debug/jtag_ap.rb

@@ -0,0 +1,10 @@
+require 'origen_arm_debug/jtag_ap_controller'
+module OrigenARMDebug
+  class JTAGAP < AP
+    include Origen::Model
+
+    def initialize(options = {})
+      super
+    end
+  end
+end

data/lib/origen_arm_debug/jtag_ap_controller.rb

@@ -0,0 +1,6 @@
+module OrigenARMDebug
+  class JTAGAPController
+    include Origen::Controller
+    include Helpers
+  end
+end

data/lib/origen_arm_debug/jtag_dp.rb

@@ -0,0 +1,59 @@
+require 'origen_arm_debug/jtag_dp_controller'
+module OrigenARMDebug
+  class JTAG_DP
+    include Origen::Model
+
+    def initialize(options = {})
+      add_reg :ir, 0, size: 4
+
+      # Virtual reg used to represent all of the various 35-bit scan chains
+      reg :dr, 0, size: 35 do |reg|
+        reg.bit 34..3, :data
+        reg.bit 2..1, :a
+        reg.bit 0, :rnw
+      end
+
+      reg :idcode, 0b1110, access: :ro do |reg|
+        reg.bit 31..28, :version
+        reg.bit 27..12, :partno
+        reg.bit 11..1, :designer
+        reg.bit 0, :bit0, reset: 1
+      end
+
+      reg :ctrlstat, 0x4 do |reg|
+        reg.bit 31, :csyspwrupack
+        reg.bit 30, :csyspwrupreq
+        reg.bit 29, :cdbgpwrupack
+        reg.bit 28, :cdbgpwrupreq
+        reg.bit 27, :cdbgrstack
+        reg.bit 26, :cdbgrstreq
+        reg.bit 23..12, :trncnt
+        reg.bit 11..8, :masklane
+        reg.bit 5, :stickyerr
+        reg.bit 4, :stickycmp
+        reg.bit 3..2, :trnmode
+        reg.bit 1, :stickyorun
+        reg.bit 0, :orundetect
+      end
+
+      reg :select, 0x8 do |reg|
+        reg.bit 31..24, :apsel
+        reg.bit 7..4, :apbanksel
+      end
+
+      add_reg :rdbuff, 0xC, access: :ro, reset: 0
+
+      reg :abort, 0b1000, access: :wo do |reg|
+        reg.bit 0, :dapabort
+      end
+    end
+
+    def select
+      reg(:select)
+    end
+
+    def abort
+      reg(:abort)
+    end
+  end
+end

data/lib/origen_arm_debug/jtag_dp_controller.rb

@@ -0,0 +1,140 @@
+require 'origen_arm_debug/dp_controller'
+module OrigenARMDebug
+  class JTAG_DPController
+    include Origen::Controller
+    include Helpers
+    include DPController
+
+    def write_register(reg, options = {})
+      unless reg.writable?
+        fail "The :#{reg.name} register is not writeable!"
+      end
+
+      # DP register write
+      if reg.owner == model
+        # Don't log this one, not really a DP reg and will be included
+        # in the JTAG driver log anyway
+        if reg.name == :ir
+          dut.jtag.write_ir(reg)
+        else
+
+          log "Write JTAG-DP register #{reg.name.to_s.upcase}: #{reg.data.to_hex}" do
+            if reg.name == :abort
+              ir.write!(reg.offset)
+              dr.reset
+              dr.overlay(nil)
+              dr[2..0].write(0)
+              dr[34..3].copy_all(reg)
+              dut.jtag.write_dr(dr)
+
+            # DPACC
+            elsif reg.name == :ctrlstat || reg.name == :select
+              dr.reset
+              dr.overlay(nil)
+              dr[0].write(0)
+              dr[2..1].write(reg.offset >> 2)
+              dr[34..3].copy_all(reg)
+              ir.write!(0b1010)
+              dut.jtag.write_dr(dr)
+
+            else
+              fail "Can't write #{reg.name}"
+            end
+          end
+        end
+
+      # AP register write
+      else
+
+        unless reg.owner.is_a?(AP)
+          fail 'The JTAG-DP can only write to DP or AP registers!'
+        end
+
+        select_ap_reg(reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(0)
+        dr[2..1].write(reg.offset >> 2)
+        dr[34..3].copy_all(reg)
+        ir.write!(0b1011)
+        dut.jtag.write_dr(dr, options)
+      end
+    end
+
+    def read_register(reg, options = {})
+      unless reg.readable?
+        fail "The :#{reg.name} register is not readable!"
+      end
+
+      if reg.owner == model
+        # Don't log this one, not really a DP reg and will be included
+        # in the JTAG driver log anyway
+        if reg.name == :ir
+          dut.jtag.read_ir(reg)
+        else
+
+          log "Read JTAG-DP register #{reg.name.to_s.upcase}: #{Origen::Utility.read_hex(reg)}" do
+            if reg.name == :idcode
+              ir.write!(reg.offset)
+              dut.jtag.read_dr(reg)
+
+            # DPACC
+            elsif reg.name == :ctrlstat || reg.name == :select || reg.name == :rdbuff
+
+              # Part 1 - Request read from DP-Register by writing to DPACC with RnW=1
+              dr.reset
+              dr.overlay(nil)
+              dr[0].write(1)
+              dr[2..1].write(reg.offset >> 2)
+              dr[34..3].write(0)
+              ir.write!(0b1010)
+              dut.jtag.write_dr(dr)
+
+              # Part 2 - Now read real data from RDBUFF (DP-Reg)
+              dr.reset
+              dr.overlay(nil)
+              dr[0].write(1)
+              dr[2..1].write(rdbuff.offset >> 2)
+              dr[34..3].copy_all(reg)
+              dut.jtag.read_dr(dr, options)
+
+            else
+              fail "Can't read #{reg.name}"
+            end
+          end
+        end
+
+      # AP register read
+      else
+        unless reg.owner.is_a?(AP)
+          fail 'The JTAG-DP can only write to DP or AP registers!'
+        end
+
+        # Part 1 - Request read from AP-Register by writing to APACC with RnW=1
+        select_ap_reg(reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(1)
+        dr[2..1].write(reg.offset >> 2)
+        dr[34..3].write(0)
+        ir.write!(0b1011)
+        dut.jtag.write_dr(dr)
+
+        # Calling AP should provide any delay parameter for wait states between AP read request
+        #   and when the data is available at the RDBUFF DP-Reg
+        if options[:apacc_wait_states]
+          options[:apacc_wait_states].cycles
+        end
+
+        # Part 2 - Now read real data from RDBUFF (DP-Reg)
+        dr.reset
+        dr.overlay(nil)
+        dr[0].write(1)
+        dr[2..1].write(rdbuff.offset >> 2)
+        dr[34..3].copy_all(reg)
+        ir.write!(0b1010)
+        dut.jtag.read_dr(dr, options)
+      end
+    end
+  end
+end