mldsa_gh 0.1.0

data/ext/mldsa_gh_native/vendor/mldsa-native/mldsa/src/native/aarch64/src/mldsa_poly_use_hint_88_aarch64_asm.S

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+/*yaml
+  Name: poly_use_hint_88_aarch64_asm
+  Description: AArch64 hint application (alpha = (Q-1)/88)
+  Signature: void mld_poly_use_hint_88_aarch64_asm(int32_t a[256], const int32_t h[256])
+  ABI:
+    Architecture: aarch64
+    CallingConvention: AAPCS64
+    Features: [NEON]
+    x0:
+      type: buffer
+      size_bytes: 1024
+      permissions: read/write
+      c_parameter: int32_t a[256]
+      description: Input/output polynomial (256 x int32_t)
+    x1:
+      type: buffer
+      size_bytes: 1024
+      permissions: read-only
+      c_parameter: const int32_t h[256]
+      description: Hint polynomial (256 x int32_t)
+*/
+
+#include "../../../common.h"
+
+#if defined(MLD_ARITH_BACKEND_AARCH64) && !defined(MLD_CONFIG_NO_VERIFY_API) && !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED) && \
+           (defined(MLD_CONFIG_MULTILEVEL_WITH_SHARED) || MLD_CONFIG_PARAMETER_SET == 44)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/aarch64_opt/src/mldsa_poly_use_hint_88_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(poly_use_hint_88_aarch64_asm)
+MLD_ASM_FN_SYMBOL(poly_use_hint_88_aarch64_asm)
+
+        .cfi_startproc
+        mov w4, #0xe001             // =57345
+        movk w4, #0x7f, lsl #16
+        dup v20.4s, w4
+        mov w5, #0x6c00             // =27648
+        movk w5, #0x7e, lsl #16
+        dup v21.4s, w5
+        mov w7, #0xe800             // =59392
+        movk w7, #0x2, lsl #16
+        dup v22.4s, w7
+        mov w11, #0x581             // =1409
+        movk w11, #0x5816, lsl #16
+        dup v23.4s, w11
+        movi v24.4s, #0x2b
+        mov x3, #0x10               // =16
+
+Lmld_poly_use_hint_88_loop:
+        ldr q1, [x0, #0x10]
+        ldr q2, [x0, #0x20]
+        ldr q3, [x0, #0x30]
+        ldr q0, [x0]
+        ldr q5, [x1, #0x10]
+        ldr q6, [x1, #0x20]
+        ldr q7, [x1, #0x30]
+        ldr q4, [x1], #0x40
+        sqdmulh v17.4s, v1.4s, v23.4s
+        srshr v17.4s, v17.4s, #0x11
+        cmgt v25.4s, v1.4s, v21.4s
+        mls v1.4s, v17.4s, v22.4s
+        bic v17.16b, v17.16b, v25.16b
+        add v1.4s, v1.4s, v25.4s
+        cmle v1.4s, v1.4s, #0
+        orr v1.4s, #0x1
+        mla v17.4s, v1.4s, v5.4s
+        cmgt v25.4s, v17.4s, v24.4s
+        bic v17.16b, v17.16b, v25.16b
+        umin v17.4s, v17.4s, v24.4s
+        sqdmulh v18.4s, v2.4s, v23.4s
+        srshr v18.4s, v18.4s, #0x11
+        cmgt v25.4s, v2.4s, v21.4s
+        mls v2.4s, v18.4s, v22.4s
+        bic v18.16b, v18.16b, v25.16b
+        add v2.4s, v2.4s, v25.4s
+        cmle v2.4s, v2.4s, #0
+        orr v2.4s, #0x1
+        mla v18.4s, v2.4s, v6.4s
+        cmgt v25.4s, v18.4s, v24.4s
+        bic v18.16b, v18.16b, v25.16b
+        umin v18.4s, v18.4s, v24.4s
+        sqdmulh v19.4s, v3.4s, v23.4s
+        srshr v19.4s, v19.4s, #0x11
+        cmgt v25.4s, v3.4s, v21.4s
+        mls v3.4s, v19.4s, v22.4s
+        bic v19.16b, v19.16b, v25.16b
+        add v3.4s, v3.4s, v25.4s
+        cmle v3.4s, v3.4s, #0
+        orr v3.4s, #0x1
+        mla v19.4s, v3.4s, v7.4s
+        cmgt v25.4s, v19.4s, v24.4s
+        bic v19.16b, v19.16b, v25.16b
+        umin v19.4s, v19.4s, v24.4s
+        sqdmulh v16.4s, v0.4s, v23.4s
+        srshr v16.4s, v16.4s, #0x11
+        cmgt v25.4s, v0.4s, v21.4s
+        mls v0.4s, v16.4s, v22.4s
+        bic v16.16b, v16.16b, v25.16b
+        add v0.4s, v0.4s, v25.4s
+        cmle v0.4s, v0.4s, #0
+        orr v0.4s, #0x1
+        mla v16.4s, v0.4s, v4.4s
+        cmgt v25.4s, v16.4s, v24.4s
+        bic v16.16b, v16.16b, v25.16b
+        umin v16.4s, v16.4s, v24.4s
+        str q17, [x0, #0x10]
+        str q18, [x0, #0x20]
+        str q19, [x0, #0x30]
+        str q16, [x0], #0x40
+        subs x3, x3, #0x1
+        b.ne Lmld_poly_use_hint_88_loop
+        ret
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(poly_use_hint_88_aarch64_asm)
+
+#endif /* MLD_ARITH_BACKEND_AARCH64 && !MLD_CONFIG_NO_VERIFY_API && \
+          !MLD_CONFIG_MULTILEVEL_NO_SHARED && \
+          (MLD_CONFIG_MULTILEVEL_WITH_SHARED || MLD_CONFIG_PARAMETER_SET == 44) \
+        */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif

data/ext/mldsa_gh_native/vendor/mldsa-native/mldsa/src/native/aarch64/src/mldsa_polyvecl_pointwise_acc_montgomery_l4_aarch64_asm.S

@@ -0,0 +1,157 @@
+/* Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/*yaml
+  Name: polyvecl_pointwise_acc_montgomery_l4_aarch64_asm
+  Description: AArch64 pointwise multiply-accumulate of length-4 polynomial vectors
+  Signature: void mld_polyvecl_pointwise_acc_montgomery_l4_aarch64_asm(int32_t r[256], const int32_t a[4][256], const int32_t b[4][256])
+  ABI:
+    Architecture: aarch64
+    CallingConvention: AAPCS64
+    Features: [NEON]
+    x0:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t r[256]
+      description: Output polynomial (256 x int32_t)
+    x1:
+      type: buffer
+      size_bytes: 4096
+      permissions: read-only
+      c_parameter: const int32_t a[4][256]
+      description: Input polynomial vector a (4 x 256 x int32_t)
+    x2:
+      type: buffer
+      size_bytes: 4096
+      permissions: read-only
+      c_parameter: const int32_t b[4][256]
+      description: Input polynomial vector b (4 x 256 x int32_t)
+*/
+
+#include "../../../common.h"
+#if defined(MLD_ARITH_BACKEND_AARCH64) && !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED) && \
+           (defined(MLD_CONFIG_MULTILEVEL_WITH_SHARED) || MLDSA_L == 4)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/aarch64_opt/src/mldsa_polyvecl_pointwise_acc_montgomery_l4_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(polyvecl_pointwise_acc_montgomery_l4_aarch64_asm)
+MLD_ASM_FN_SYMBOL(polyvecl_pointwise_acc_montgomery_l4_aarch64_asm)
+
+        .cfi_startproc
+        mov w3, #0xe001             // =57345
+        movk w3, #0x7f, lsl #16
+        dup v0.4s, w3
+        mov w3, #0x2001             // =8193
+        movk w3, #0x380, lsl #16
+        dup v1.4s, w3
+        mov x3, #0x40               // =64
+
+Lmld_polyvecl_pointwise_acc_montgomery_l4_loop_start:
+        ldr q17, [x1, #0x10]
+        ldr q18, [x1, #0x20]
+        ldr q19, [x1, #0x30]
+        ldr q16, [x1], #0x40
+        ldr q21, [x2, #0x10]
+        ldr q22, [x2, #0x20]
+        ldr q23, [x2, #0x30]
+        ldr q20, [x2], #0x40
+        smull v24.2d, v16.2s, v20.2s
+        smull2 v25.2d, v16.4s, v20.4s
+        smull v26.2d, v17.2s, v21.2s
+        smull2 v27.2d, v17.4s, v21.4s
+        smull v28.2d, v18.2s, v22.2s
+        smull2 v29.2d, v18.4s, v22.4s
+        smull v30.2d, v19.2s, v23.2s
+        smull2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x3c0]
+        ldr q17, [x1, #0x3d0]
+        ldr q18, [x1, #0x3e0]
+        ldr q19, [x1, #0x3f0]
+        ldr q20, [x2, #0x3c0]
+        ldr q21, [x2, #0x3d0]
+        ldr q22, [x2, #0x3e0]
+        ldr q23, [x2, #0x3f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x7c0]
+        ldr q17, [x1, #0x7d0]
+        ldr q18, [x1, #0x7e0]
+        ldr q19, [x1, #0x7f0]
+        ldr q20, [x2, #0x7c0]
+        ldr q21, [x2, #0x7d0]
+        ldr q22, [x2, #0x7e0]
+        ldr q23, [x2, #0x7f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0xbc0]
+        ldr q17, [x1, #0xbd0]
+        ldr q18, [x1, #0xbe0]
+        ldr q19, [x1, #0xbf0]
+        ldr q20, [x2, #0xbc0]
+        ldr q21, [x2, #0xbd0]
+        ldr q22, [x2, #0xbe0]
+        ldr q23, [x2, #0xbf0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        uzp1 v16.4s, v24.4s, v25.4s
+        mul v16.4s, v16.4s, v1.4s
+        smlsl v24.2d, v16.2s, v0.2s
+        smlsl2 v25.2d, v16.4s, v0.4s
+        uzp2 v16.4s, v24.4s, v25.4s
+        uzp1 v17.4s, v26.4s, v27.4s
+        mul v17.4s, v17.4s, v1.4s
+        smlsl v26.2d, v17.2s, v0.2s
+        smlsl2 v27.2d, v17.4s, v0.4s
+        uzp2 v17.4s, v26.4s, v27.4s
+        uzp1 v18.4s, v28.4s, v29.4s
+        mul v18.4s, v18.4s, v1.4s
+        smlsl v28.2d, v18.2s, v0.2s
+        smlsl2 v29.2d, v18.4s, v0.4s
+        uzp2 v18.4s, v28.4s, v29.4s
+        uzp1 v19.4s, v30.4s, v31.4s
+        mul v19.4s, v19.4s, v1.4s
+        smlsl v30.2d, v19.2s, v0.2s
+        smlsl2 v31.2d, v19.4s, v0.4s
+        uzp2 v19.4s, v30.4s, v31.4s
+        str q17, [x0, #0x10]
+        str q18, [x0, #0x20]
+        str q19, [x0, #0x30]
+        str q16, [x0], #0x40
+        subs x3, x3, #0x4
+        cbnz x3, Lmld_polyvecl_pointwise_acc_montgomery_l4_loop_start
+        ret
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(polyvecl_pointwise_acc_montgomery_l4_aarch64_asm)
+
+#endif /* MLD_ARITH_BACKEND_AARCH64 && !MLD_CONFIG_MULTILEVEL_NO_SHARED && \
+          (MLD_CONFIG_MULTILEVEL_WITH_SHARED || MLDSA_L == 4) */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif

data/ext/mldsa_gh_native/vendor/mldsa-native/mldsa/src/native/aarch64/src/mldsa_polyvecl_pointwise_acc_montgomery_l5_aarch64_asm.S

@@ -0,0 +1,173 @@
+/* Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/*yaml
+  Name: polyvecl_pointwise_acc_montgomery_l5_aarch64_asm
+  Description: AArch64 pointwise multiply-accumulate of length-5 polynomial vectors
+  Signature: void mld_polyvecl_pointwise_acc_montgomery_l5_aarch64_asm(int32_t r[256], const int32_t a[5][256], const int32_t b[5][256])
+  ABI:
+    Architecture: aarch64
+    CallingConvention: AAPCS64
+    Features: [NEON]
+    x0:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t r[256]
+      description: Output polynomial (256 x int32_t)
+    x1:
+      type: buffer
+      size_bytes: 5120
+      permissions: read-only
+      c_parameter: const int32_t a[5][256]
+      description: Input polynomial vector a (5 x 256 x int32_t)
+    x2:
+      type: buffer
+      size_bytes: 5120
+      permissions: read-only
+      c_parameter: const int32_t b[5][256]
+      description: Input polynomial vector b (5 x 256 x int32_t)
+*/
+
+#include "../../../common.h"
+#if defined(MLD_ARITH_BACKEND_AARCH64) && !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED) && \
+           (defined(MLD_CONFIG_MULTILEVEL_WITH_SHARED) || MLDSA_L == 5)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/aarch64_opt/src/mldsa_polyvecl_pointwise_acc_montgomery_l5_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(polyvecl_pointwise_acc_montgomery_l5_aarch64_asm)
+MLD_ASM_FN_SYMBOL(polyvecl_pointwise_acc_montgomery_l5_aarch64_asm)
+
+        .cfi_startproc
+        mov w3, #0xe001             // =57345
+        movk w3, #0x7f, lsl #16
+        dup v0.4s, w3
+        mov w3, #0x2001             // =8193
+        movk w3, #0x380, lsl #16
+        dup v1.4s, w3
+        mov x3, #0x40               // =64
+
+Lmld_polyvecl_pointwise_acc_montgomery_l5_loop_start:
+        ldr q17, [x1, #0x10]
+        ldr q18, [x1, #0x20]
+        ldr q19, [x1, #0x30]
+        ldr q16, [x1], #0x40
+        ldr q21, [x2, #0x10]
+        ldr q22, [x2, #0x20]
+        ldr q23, [x2, #0x30]
+        ldr q20, [x2], #0x40
+        smull v24.2d, v16.2s, v20.2s
+        smull2 v25.2d, v16.4s, v20.4s
+        smull v26.2d, v17.2s, v21.2s
+        smull2 v27.2d, v17.4s, v21.4s
+        smull v28.2d, v18.2s, v22.2s
+        smull2 v29.2d, v18.4s, v22.4s
+        smull v30.2d, v19.2s, v23.2s
+        smull2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x3c0]
+        ldr q17, [x1, #0x3d0]
+        ldr q18, [x1, #0x3e0]
+        ldr q19, [x1, #0x3f0]
+        ldr q20, [x2, #0x3c0]
+        ldr q21, [x2, #0x3d0]
+        ldr q22, [x2, #0x3e0]
+        ldr q23, [x2, #0x3f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x7c0]
+        ldr q17, [x1, #0x7d0]
+        ldr q18, [x1, #0x7e0]
+        ldr q19, [x1, #0x7f0]
+        ldr q20, [x2, #0x7c0]
+        ldr q21, [x2, #0x7d0]
+        ldr q22, [x2, #0x7e0]
+        ldr q23, [x2, #0x7f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0xbc0]
+        ldr q17, [x1, #0xbd0]
+        ldr q18, [x1, #0xbe0]
+        ldr q19, [x1, #0xbf0]
+        ldr q20, [x2, #0xbc0]
+        ldr q21, [x2, #0xbd0]
+        ldr q22, [x2, #0xbe0]
+        ldr q23, [x2, #0xbf0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0xfc0]
+        ldr q17, [x1, #0xfd0]
+        ldr q18, [x1, #0xfe0]
+        ldr q19, [x1, #0xff0]
+        ldr q20, [x2, #0xfc0]
+        ldr q21, [x2, #0xfd0]
+        ldr q22, [x2, #0xfe0]
+        ldr q23, [x2, #0xff0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        uzp1 v16.4s, v24.4s, v25.4s
+        mul v16.4s, v16.4s, v1.4s
+        smlsl v24.2d, v16.2s, v0.2s
+        smlsl2 v25.2d, v16.4s, v0.4s
+        uzp2 v16.4s, v24.4s, v25.4s
+        uzp1 v17.4s, v26.4s, v27.4s
+        mul v17.4s, v17.4s, v1.4s
+        smlsl v26.2d, v17.2s, v0.2s
+        smlsl2 v27.2d, v17.4s, v0.4s
+        uzp2 v17.4s, v26.4s, v27.4s
+        uzp1 v18.4s, v28.4s, v29.4s
+        mul v18.4s, v18.4s, v1.4s
+        smlsl v28.2d, v18.2s, v0.2s
+        smlsl2 v29.2d, v18.4s, v0.4s
+        uzp2 v18.4s, v28.4s, v29.4s
+        uzp1 v19.4s, v30.4s, v31.4s
+        mul v19.4s, v19.4s, v1.4s
+        smlsl v30.2d, v19.2s, v0.2s
+        smlsl2 v31.2d, v19.4s, v0.4s
+        uzp2 v19.4s, v30.4s, v31.4s
+        str q17, [x0, #0x10]
+        str q18, [x0, #0x20]
+        str q19, [x0, #0x30]
+        str q16, [x0], #0x40
+        subs x3, x3, #0x4
+        cbnz x3, Lmld_polyvecl_pointwise_acc_montgomery_l5_loop_start
+        ret
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(polyvecl_pointwise_acc_montgomery_l5_aarch64_asm)
+
+#endif /* MLD_ARITH_BACKEND_AARCH64 && !MLD_CONFIG_MULTILEVEL_NO_SHARED && \
+          (MLD_CONFIG_MULTILEVEL_WITH_SHARED || MLDSA_L == 5) */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif

data/ext/mldsa_gh_native/vendor/mldsa-native/mldsa/src/native/aarch64/src/mldsa_polyvecl_pointwise_acc_montgomery_l7_aarch64_asm.S

@@ -0,0 +1,205 @@
+/* Copyright (c) The mldsa-native project authors
+ * SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT
+ */
+
+/*yaml
+  Name: polyvecl_pointwise_acc_montgomery_l7_aarch64_asm
+  Description: AArch64 pointwise multiply-accumulate of length-7 polynomial vectors
+  Signature: void mld_polyvecl_pointwise_acc_montgomery_l7_aarch64_asm(int32_t r[256], const int32_t a[7][256], const int32_t b[7][256])
+  ABI:
+    Architecture: aarch64
+    CallingConvention: AAPCS64
+    Features: [NEON]
+    x0:
+      type: buffer
+      size_bytes: 1024
+      permissions: write-only
+      c_parameter: int32_t r[256]
+      description: Output polynomial (256 x int32_t)
+    x1:
+      type: buffer
+      size_bytes: 7168
+      permissions: read-only
+      c_parameter: const int32_t a[7][256]
+      description: Input polynomial vector a (7 x 256 x int32_t)
+    x2:
+      type: buffer
+      size_bytes: 7168
+      permissions: read-only
+      c_parameter: const int32_t b[7][256]
+      description: Input polynomial vector b (7 x 256 x int32_t)
+*/
+
+#include "../../../common.h"
+#if defined(MLD_ARITH_BACKEND_AARCH64) && !defined(MLD_CONFIG_MULTILEVEL_NO_SHARED) && \
+           (defined(MLD_CONFIG_MULTILEVEL_WITH_SHARED) || MLDSA_L == 7)
+
+/*
+ * WARNING: This file is auto-derived from the mldsa-native source file
+ *   dev/aarch64_opt/src/mldsa_polyvecl_pointwise_acc_montgomery_l7_aarch64_asm.S using scripts/simpasm. Do not modify it directly.
+ */
+
+.text
+.balign 4
+.global MLD_ASM_NAMESPACE(polyvecl_pointwise_acc_montgomery_l7_aarch64_asm)
+MLD_ASM_FN_SYMBOL(polyvecl_pointwise_acc_montgomery_l7_aarch64_asm)
+
+        .cfi_startproc
+        mov w3, #0xe001             // =57345
+        movk w3, #0x7f, lsl #16
+        dup v0.4s, w3
+        mov w3, #0x2001             // =8193
+        movk w3, #0x380, lsl #16
+        dup v1.4s, w3
+        mov x3, #0x40               // =64
+
+Lmld_polyvecl_pointwise_acc_montgomery_l7_loop_start:
+        ldr q17, [x1, #0x10]
+        ldr q18, [x1, #0x20]
+        ldr q19, [x1, #0x30]
+        ldr q16, [x1], #0x40
+        ldr q21, [x2, #0x10]
+        ldr q22, [x2, #0x20]
+        ldr q23, [x2, #0x30]
+        ldr q20, [x2], #0x40
+        smull v24.2d, v16.2s, v20.2s
+        smull2 v25.2d, v16.4s, v20.4s
+        smull v26.2d, v17.2s, v21.2s
+        smull2 v27.2d, v17.4s, v21.4s
+        smull v28.2d, v18.2s, v22.2s
+        smull2 v29.2d, v18.4s, v22.4s
+        smull v30.2d, v19.2s, v23.2s
+        smull2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x3c0]
+        ldr q17, [x1, #0x3d0]
+        ldr q18, [x1, #0x3e0]
+        ldr q19, [x1, #0x3f0]
+        ldr q20, [x2, #0x3c0]
+        ldr q21, [x2, #0x3d0]
+        ldr q22, [x2, #0x3e0]
+        ldr q23, [x2, #0x3f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x7c0]
+        ldr q17, [x1, #0x7d0]
+        ldr q18, [x1, #0x7e0]
+        ldr q19, [x1, #0x7f0]
+        ldr q20, [x2, #0x7c0]
+        ldr q21, [x2, #0x7d0]
+        ldr q22, [x2, #0x7e0]
+        ldr q23, [x2, #0x7f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0xbc0]
+        ldr q17, [x1, #0xbd0]
+        ldr q18, [x1, #0xbe0]
+        ldr q19, [x1, #0xbf0]
+        ldr q20, [x2, #0xbc0]
+        ldr q21, [x2, #0xbd0]
+        ldr q22, [x2, #0xbe0]
+        ldr q23, [x2, #0xbf0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0xfc0]
+        ldr q17, [x1, #0xfd0]
+        ldr q18, [x1, #0xfe0]
+        ldr q19, [x1, #0xff0]
+        ldr q20, [x2, #0xfc0]
+        ldr q21, [x2, #0xfd0]
+        ldr q22, [x2, #0xfe0]
+        ldr q23, [x2, #0xff0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x13c0]
+        ldr q17, [x1, #0x13d0]
+        ldr q18, [x1, #0x13e0]
+        ldr q19, [x1, #0x13f0]
+        ldr q20, [x2, #0x13c0]
+        ldr q21, [x2, #0x13d0]
+        ldr q22, [x2, #0x13e0]
+        ldr q23, [x2, #0x13f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        ldr q16, [x1, #0x17c0]
+        ldr q17, [x1, #0x17d0]
+        ldr q18, [x1, #0x17e0]
+        ldr q19, [x1, #0x17f0]
+        ldr q20, [x2, #0x17c0]
+        ldr q21, [x2, #0x17d0]
+        ldr q22, [x2, #0x17e0]
+        ldr q23, [x2, #0x17f0]
+        smlal v24.2d, v16.2s, v20.2s
+        smlal2 v25.2d, v16.4s, v20.4s
+        smlal v26.2d, v17.2s, v21.2s
+        smlal2 v27.2d, v17.4s, v21.4s
+        smlal v28.2d, v18.2s, v22.2s
+        smlal2 v29.2d, v18.4s, v22.4s
+        smlal v30.2d, v19.2s, v23.2s
+        smlal2 v31.2d, v19.4s, v23.4s
+        uzp1 v16.4s, v24.4s, v25.4s
+        mul v16.4s, v16.4s, v1.4s
+        smlsl v24.2d, v16.2s, v0.2s
+        smlsl2 v25.2d, v16.4s, v0.4s
+        uzp2 v16.4s, v24.4s, v25.4s
+        uzp1 v17.4s, v26.4s, v27.4s
+        mul v17.4s, v17.4s, v1.4s
+        smlsl v26.2d, v17.2s, v0.2s
+        smlsl2 v27.2d, v17.4s, v0.4s
+        uzp2 v17.4s, v26.4s, v27.4s
+        uzp1 v18.4s, v28.4s, v29.4s
+        mul v18.4s, v18.4s, v1.4s
+        smlsl v28.2d, v18.2s, v0.2s
+        smlsl2 v29.2d, v18.4s, v0.4s
+        uzp2 v18.4s, v28.4s, v29.4s
+        uzp1 v19.4s, v30.4s, v31.4s
+        mul v19.4s, v19.4s, v1.4s
+        smlsl v30.2d, v19.2s, v0.2s
+        smlsl2 v31.2d, v19.4s, v0.4s
+        uzp2 v19.4s, v30.4s, v31.4s
+        str q17, [x0, #0x10]
+        str q18, [x0, #0x20]
+        str q19, [x0, #0x30]
+        str q16, [x0], #0x40
+        subs x3, x3, #0x4
+        cbnz x3, Lmld_polyvecl_pointwise_acc_montgomery_l7_loop_start
+        ret
+        .cfi_endproc
+
+MLD_ASM_FN_SIZE(polyvecl_pointwise_acc_montgomery_l7_aarch64_asm)
+
+#endif /* MLD_ARITH_BACKEND_AARCH64 && !MLD_CONFIG_MULTILEVEL_NO_SHARED && \
+          (MLD_CONFIG_MULTILEVEL_WITH_SHARED || MLDSA_L == 7) */
+
+#if defined(__ELF__)
+.section .note.GNU-stack,"",%progbits
+#endif