gccxml_gem 0.9.2-x86-linux → 0.9.3-x86-linux

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Files changed (49) hide show
  1. data/Rakefile +15 -6
  2. data/bin/gccxml +0 -0
  3. data/bin/gccxml_cc1plus +0 -0
  4. data/gccxml.rb +5 -5
  5. data/share/gccxml-0.9/GCC/3.2/bits/gthr-default.h +4 -0
  6. data/share/gccxml-0.9/GCC/3.4/bits/gthr-default.h +5 -0
  7. data/share/gccxml-0.9/GCC/4.0/emmintrin.h +5 -0
  8. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_emmintrin.h +1037 -0
  9. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_mmintrin.h +669 -0
  10. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_xmmintrin.h +870 -0
  11. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_emmintrin.h +977 -0
  12. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_mmintrin.h +636 -0
  13. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_xmmintrin.h +833 -0
  14. data/share/gccxml-0.9/GCC/4.0/mmintrin.h +5 -0
  15. data/share/gccxml-0.9/GCC/4.0/xmmintrin.h +5 -0
  16. data/share/gccxml-0.9/GCC/4.1/bits/gthr-default.h +4 -0
  17. data/share/gccxml-0.9/GCC/4.1/emmintrin.h +5 -0
  18. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_emmintrin.h +1509 -0
  19. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_mmintrin.h +942 -0
  20. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_xmmintrin.h +1192 -0
  21. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_emmintrin.h +1004 -0
  22. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_mmintrin.h +637 -0
  23. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_xmmintrin.h +834 -0
  24. data/share/gccxml-0.9/GCC/4.1/mmintrin.h +5 -0
  25. data/share/gccxml-0.9/GCC/4.1/xmmintrin.h +5 -0
  26. data/share/gccxml-0.9/GCC/4.2/emmintrin.h +5 -0
  27. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_emmintrin.h +1509 -0
  28. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_mmintrin.h +942 -0
  29. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_xmmintrin.h +1192 -0
  30. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_emmintrin.h +1013 -0
  31. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_mmintrin.h +663 -0
  32. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_xmmintrin.h +860 -0
  33. data/share/gccxml-0.9/GCC/4.2/mmintrin.h +5 -0
  34. data/share/gccxml-0.9/GCC/4.2/xmmintrin.h +5 -0
  35. data/share/gccxml-0.9/GCC/4.3/emmintrin.h +1043 -0
  36. data/share/gccxml-0.9/GCC/4.3/gccxml_builtins.h +1 -0
  37. data/share/gccxml-0.9/GCC/4.3/mmintrin.h +663 -0
  38. data/share/gccxml-0.9/GCC/4.3/xmmintrin.h +867 -0
  39. data/share/gccxml-0.9/GCC/4.4/bits/c++config.h +1431 -0
  40. data/share/gccxml-0.9/GCC/4.4/emmintrin.h +1041 -0
  41. data/share/gccxml-0.9/GCC/4.4/gccxml_builtins.h +153 -0
  42. data/share/gccxml-0.9/GCC/4.4/mmintrin.h +662 -0
  43. data/share/gccxml-0.9/GCC/4.4/xmmintrin.h +864 -0
  44. data/share/gccxml-0.9/GCC/4.5/gccxml_builtins.h +154 -0
  45. data/share/gccxml-0.9/GCC/4.5/iomanip +349 -0
  46. data/share/gccxml-0.9/GCC/COPYING.RUNTIME +73 -0
  47. data/share/gccxml-0.9/GCC/COPYING3 +674 -0
  48. data/share/man/man1/gccxml.1 +1 -1
  49. metadata +165 -114
@@ -0,0 +1,833 @@
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+ /* Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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+
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+ This file is part of GCC.
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+
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+ GCC is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2, or (at your option)
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+ any later version.
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+
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+ GCC is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with GCC; see the file COPYING. If not, write to
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+ the Free Software Foundation, 59 Temple Place - Suite 330,
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+ Boston, MA 02111-1307, USA. */
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+
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+ /* As a special exception, if you include this header file into source
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+ files compiled by GCC, this header file does not by itself cause
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+ the resulting executable to be covered by the GNU General Public
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+ License. This exception does not however invalidate any other
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+ reasons why the executable file might be covered by the GNU General
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+ Public License. */
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+
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+ /* Implemented from the specification included in the Intel C++ Compiler
28
+ User Guide and Reference, version 8.0. */
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+
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+ #ifndef _XMMINTRIN_H_INCLUDED
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+ #define _XMMINTRIN_H_INCLUDED
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+
33
+ #ifndef __SSE__
34
+ # error "SSE instruction set not enabled"
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+ #else
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+
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+ /* We need type definitions from the MMX header file. */
38
+ #include <mmintrin.h>
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+
40
+ /* Get _mm_malloc () and _mm_free (). */
41
+ #include <mm_malloc.h>
42
+
43
+ /* The data type intended for user use. */
44
+ typedef float __m128 __attribute__ ((__vector_size__ (16)));
45
+
46
+ /* Internal data types for implementing the intrinsics. */
47
+ typedef float __v4sf __attribute__ ((__vector_size__ (16)));
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+
49
+ /* Create a selector for use with the SHUFPS instruction. */
50
+ #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
51
+ (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
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+
53
+ /* Constants for use with _mm_prefetch. */
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+ enum _mm_hint
55
+ {
56
+ _MM_HINT_T0 = 3,
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+ _MM_HINT_T1 = 2,
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+ _MM_HINT_T2 = 1,
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+ _MM_HINT_NTA = 0
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+ };
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+
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+ /* Bits in the MXCSR. */
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+ #define _MM_EXCEPT_MASK 0x003f
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+ #define _MM_EXCEPT_INVALID 0x0001
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+ #define _MM_EXCEPT_DENORM 0x0002
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+ #define _MM_EXCEPT_DIV_ZERO 0x0004
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+ #define _MM_EXCEPT_OVERFLOW 0x0008
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+ #define _MM_EXCEPT_UNDERFLOW 0x0010
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+ #define _MM_EXCEPT_INEXACT 0x0020
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+
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+ #define _MM_MASK_MASK 0x1f80
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+ #define _MM_MASK_INVALID 0x0080
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+ #define _MM_MASK_DENORM 0x0100
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+ #define _MM_MASK_DIV_ZERO 0x0200
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+ #define _MM_MASK_OVERFLOW 0x0400
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+ #define _MM_MASK_UNDERFLOW 0x0800
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+ #define _MM_MASK_INEXACT 0x1000
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+
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+ #define _MM_ROUND_MASK 0x6000
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+ #define _MM_ROUND_NEAREST 0x0000
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+ #define _MM_ROUND_DOWN 0x2000
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+ #define _MM_ROUND_UP 0x4000
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+ #define _MM_ROUND_TOWARD_ZERO 0x6000
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+
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+ #define _MM_FLUSH_ZERO_MASK 0x8000
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+ #define _MM_FLUSH_ZERO_ON 0x8000
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+ #define _MM_FLUSH_ZERO_OFF 0x0000
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+
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+ /* Create a vector of zeros. */
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+ static __inline __m128
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+ _mm_setzero_ps (void)
92
+ ;
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+
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+ /* Perform the respective operation on the lower SPFP (single-precision
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+ floating-point) values of A and B; the upper three SPFP values are
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+ passed through from A. */
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+
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+ static __inline __m128
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+ _mm_add_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_sub_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_mul_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_div_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_sqrt_ss (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_rcp_ss (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_rsqrt_ss (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_min_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_max_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Perform the respective operation on the four SPFP values in A and B. */
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+
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+ static __inline __m128
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+ _mm_add_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_sub_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_mul_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_div_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_sqrt_ps (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_rcp_ps (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_rsqrt_ps (__m128 __A)
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+ ;
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+
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+ static __inline __m128
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+ _mm_min_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_max_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Perform logical bit-wise operations on 128-bit values. */
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+
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+ static __inline __m128
175
+ _mm_and_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
179
+ _mm_andnot_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_or_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_xor_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Perform a comparison on the lower SPFP values of A and B. If the
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+ comparison is true, place a mask of all ones in the result, otherwise a
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+ mask of zeros. The upper three SPFP values are passed through from A. */
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+
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+ static __inline __m128
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+ _mm_cmpeq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmplt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmple_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpgt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpge_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpneq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnlt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnle_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpngt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnge_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpord_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpunord_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Perform a comparison on the four SPFP values of A and B. For each
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+ element, if the comparison is true, place a mask of all ones in the
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+ result, otherwise a mask of zeros. */
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+
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+ static __inline __m128
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+ _mm_cmpeq_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmplt_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmple_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpgt_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpge_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpneq_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnlt_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnle_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpngt_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpnge_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpord_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128
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+ _mm_cmpunord_ps (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Compare the lower SPFP values of A and B and return 1 if true
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+ and 0 if false. */
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+
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+ static __inline int
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+ _mm_comieq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_comilt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_comile_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_comigt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_comige_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_comineq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomieq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomilt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomile_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomigt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomige_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline int
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+ _mm_ucomineq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ /* Convert the lower SPFP value to a 32-bit integer according to the current
346
+ rounding mode. */
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+ static __inline int
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+ _mm_cvtss_si32 (__m128 __A)
349
+ ;
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+
351
+ static __inline int
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+ _mm_cvt_ss2si (__m128 __A)
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+ ;
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+
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+ #ifdef __x86_64__
356
+ /* Convert the lower SPFP value to a 32-bit integer according to the current
357
+ rounding mode. */
358
+ static __inline long long
359
+ _mm_cvtss_si64x (__m128 __A)
360
+ ;
361
+ #endif
362
+
363
+ /* Convert the two lower SPFP values to 32-bit integers according to the
364
+ current rounding mode. Return the integers in packed form. */
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+ static __inline __m64
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+ _mm_cvtps_pi32 (__m128 __A)
367
+ ;
368
+
369
+ static __inline __m64
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+ _mm_cvt_ps2pi (__m128 __A)
371
+ ;
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+
373
+ /* Truncate the lower SPFP value to a 32-bit integer. */
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+ static __inline int
375
+ _mm_cvttss_si32 (__m128 __A)
376
+ ;
377
+
378
+ static __inline int
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+ _mm_cvtt_ss2si (__m128 __A)
380
+ ;
381
+
382
+ #ifdef __x86_64__
383
+ /* Truncate the lower SPFP value to a 32-bit integer. */
384
+ static __inline long long
385
+ _mm_cvttss_si64x (__m128 __A)
386
+ ;
387
+ #endif
388
+
389
+ /* Truncate the two lower SPFP values to 32-bit integers. Return the
390
+ integers in packed form. */
391
+ static __inline __m64
392
+ _mm_cvttps_pi32 (__m128 __A)
393
+ ;
394
+
395
+ static __inline __m64
396
+ _mm_cvtt_ps2pi (__m128 __A)
397
+ ;
398
+
399
+ /* Convert B to a SPFP value and insert it as element zero in A. */
400
+ static __inline __m128
401
+ _mm_cvtsi32_ss (__m128 __A, int __B)
402
+ ;
403
+
404
+ static __inline __m128
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+ _mm_cvt_si2ss (__m128 __A, int __B)
406
+ ;
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+
408
+ #ifdef __x86_64__
409
+ /* Convert B to a SPFP value and insert it as element zero in A. */
410
+ static __inline __m128
411
+ _mm_cvtsi64x_ss (__m128 __A, long long __B)
412
+ ;
413
+ #endif
414
+
415
+ /* Convert the two 32-bit values in B to SPFP form and insert them
416
+ as the two lower elements in A. */
417
+ static __inline __m128
418
+ _mm_cvtpi32_ps (__m128 __A, __m64 __B)
419
+ ;
420
+
421
+ static __inline __m128
422
+ _mm_cvt_pi2ps (__m128 __A, __m64 __B)
423
+ ;
424
+
425
+ /* Convert the four signed 16-bit values in A to SPFP form. */
426
+ static __inline __m128
427
+ _mm_cvtpi16_ps (__m64 __A)
428
+ ;
429
+
430
+ /* Convert the four unsigned 16-bit values in A to SPFP form. */
431
+ static __inline __m128
432
+ _mm_cvtpu16_ps (__m64 __A)
433
+ ;
434
+
435
+ /* Convert the low four signed 8-bit values in A to SPFP form. */
436
+ static __inline __m128
437
+ _mm_cvtpi8_ps (__m64 __A)
438
+ ;
439
+
440
+ /* Convert the low four unsigned 8-bit values in A to SPFP form. */
441
+ static __inline __m128
442
+ _mm_cvtpu8_ps(__m64 __A)
443
+ ;
444
+
445
+ /* Convert the four signed 32-bit values in A and B to SPFP form. */
446
+ static __inline __m128
447
+ _mm_cvtpi32x2_ps(__m64 __A, __m64 __B)
448
+ ;
449
+
450
+ /* Convert the four SPFP values in A to four signed 16-bit integers. */
451
+ static __inline __m64
452
+ _mm_cvtps_pi16(__m128 __A)
453
+ ;
454
+
455
+ /* Convert the four SPFP values in A to four signed 8-bit integers. */
456
+ static __inline __m64
457
+ _mm_cvtps_pi8(__m128 __A)
458
+ ;
459
+
460
+ /* Selects four specific SPFP values from A and B based on MASK. */
461
+ #if 0
462
+ static __inline __m128
463
+ _mm_shuffle_ps (__m128 __A, __m128 __B, int __mask)
464
+ ;
465
+ #else
466
+ #define _mm_shuffle_ps(A, B, MASK) \
467
+ ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
468
+ #endif
469
+
470
+
471
+ /* Selects and interleaves the upper two SPFP values from A and B. */
472
+ static __inline __m128
473
+ _mm_unpackhi_ps (__m128 __A, __m128 __B)
474
+ ;
475
+
476
+ /* Selects and interleaves the lower two SPFP values from A and B. */
477
+ static __inline __m128
478
+ _mm_unpacklo_ps (__m128 __A, __m128 __B)
479
+ ;
480
+
481
+ /* Sets the upper two SPFP values with 64-bits of data loaded from P;
482
+ the lower two values are passed through from A. */
483
+ static __inline __m128
484
+ _mm_loadh_pi (__m128 __A, __m64 const *__P)
485
+ ;
486
+
487
+ /* Stores the upper two SPFP values of A into P. */
488
+ static __inline void
489
+ _mm_storeh_pi (__m64 *__P, __m128 __A)
490
+ ;
491
+
492
+ /* Moves the upper two values of B into the lower two values of A. */
493
+ static __inline __m128
494
+ _mm_movehl_ps (__m128 __A, __m128 __B)
495
+ ;
496
+
497
+ /* Moves the lower two values of B into the upper two values of A. */
498
+ static __inline __m128
499
+ _mm_movelh_ps (__m128 __A, __m128 __B)
500
+ ;
501
+
502
+ /* Sets the lower two SPFP values with 64-bits of data loaded from P;
503
+ the upper two values are passed through from A. */
504
+ static __inline __m128
505
+ _mm_loadl_pi (__m128 __A, __m64 const *__P)
506
+ ;
507
+
508
+ /* Stores the lower two SPFP values of A into P. */
509
+ static __inline void
510
+ _mm_storel_pi (__m64 *__P, __m128 __A)
511
+ ;
512
+
513
+ /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
514
+ static __inline int
515
+ _mm_movemask_ps (__m128 __A)
516
+ ;
517
+
518
+ /* Return the contents of the control register. */
519
+ static __inline unsigned int
520
+ _mm_getcsr (void)
521
+ ;
522
+
523
+ /* Read exception bits from the control register. */
524
+ static __inline unsigned int
525
+ _MM_GET_EXCEPTION_STATE (void)
526
+ ;
527
+
528
+ static __inline unsigned int
529
+ _MM_GET_EXCEPTION_MASK (void)
530
+ ;
531
+
532
+ static __inline unsigned int
533
+ _MM_GET_ROUNDING_MODE (void)
534
+ ;
535
+
536
+ static __inline unsigned int
537
+ _MM_GET_FLUSH_ZERO_MODE (void)
538
+ ;
539
+
540
+ /* Set the control register to I. */
541
+ static __inline void
542
+ _mm_setcsr (unsigned int __I)
543
+ ;
544
+
545
+ /* Set exception bits in the control register. */
546
+ static __inline void
547
+ _MM_SET_EXCEPTION_STATE(unsigned int __mask)
548
+ ;
549
+
550
+ static __inline void
551
+ _MM_SET_EXCEPTION_MASK (unsigned int __mask)
552
+ ;
553
+
554
+ static __inline void
555
+ _MM_SET_ROUNDING_MODE (unsigned int __mode)
556
+ ;
557
+
558
+ static __inline void
559
+ _MM_SET_FLUSH_ZERO_MODE (unsigned int __mode)
560
+ ;
561
+
562
+ /* Create a vector with element 0 as F and the rest zero. */
563
+ static __inline __m128
564
+ _mm_set_ss (float __F)
565
+ ;
566
+
567
+ /* Create a vector with all four elements equal to F. */
568
+ static __inline __m128
569
+ _mm_set1_ps (float __F)
570
+ ;
571
+
572
+ static __inline __m128
573
+ _mm_set_ps1 (float __F)
574
+ ;
575
+
576
+ /* Create a vector with element 0 as *P and the rest zero. */
577
+ static __inline __m128
578
+ _mm_load_ss (float const *__P)
579
+ ;
580
+
581
+ /* Create a vector with all four elements equal to *P. */
582
+ static __inline __m128
583
+ _mm_load1_ps (float const *__P)
584
+ ;
585
+
586
+ static __inline __m128
587
+ _mm_load_ps1 (float const *__P)
588
+ ;
589
+
590
+ /* Load four SPFP values from P. The address must be 16-byte aligned. */
591
+ static __inline __m128
592
+ _mm_load_ps (float const *__P)
593
+ ;
594
+
595
+ /* Load four SPFP values from P. The address need not be 16-byte aligned. */
596
+ static __inline __m128
597
+ _mm_loadu_ps (float const *__P)
598
+ ;
599
+
600
+ /* Load four SPFP values in reverse order. The address must be aligned. */
601
+ static __inline __m128
602
+ _mm_loadr_ps (float const *__P)
603
+ ;
604
+
605
+ /* Create the vector [Z Y X W]. */
606
+ static __inline __m128
607
+ _mm_set_ps (const float __Z, const float __Y, const float __X, const float __W)
608
+ ;
609
+
610
+ /* Create the vector [W X Y Z]. */
611
+ static __inline __m128
612
+ _mm_setr_ps (float __Z, float __Y, float __X, float __W)
613
+ ;
614
+
615
+ /* Stores the lower SPFP value. */
616
+ static __inline void
617
+ _mm_store_ss (float *__P, __m128 __A)
618
+ ;
619
+
620
+ /* Store four SPFP values. The address must be 16-byte aligned. */
621
+ static __inline void
622
+ _mm_store_ps (float *__P, __m128 __A)
623
+ ;
624
+
625
+ /* Store four SPFP values. The address need not be 16-byte aligned. */
626
+ static __inline void
627
+ _mm_storeu_ps (float *__P, __m128 __A)
628
+ ;
629
+
630
+ /* Store the lower SPFP value across four words. */
631
+ static __inline void
632
+ _mm_store1_ps (float *__P, __m128 __A)
633
+ ;
634
+
635
+ static __inline void
636
+ _mm_store_ps1 (float *__P, __m128 __A)
637
+ ;
638
+
639
+ /* Store four SPFP values in reverse order. The address must be aligned. */
640
+ static __inline void
641
+ _mm_storer_ps (float *__P, __m128 __A)
642
+ ;
643
+
644
+ /* Sets the low SPFP value of A from the low value of B. */
645
+ static __inline __m128
646
+ _mm_move_ss (__m128 __A, __m128 __B)
647
+ ;
648
+
649
+ /* Extracts one of the four words of A. The selector N must be immediate. */
650
+ #if 0
651
+ static __inline int __attribute__((__always_inline__))
652
+ _mm_extract_pi16 (__m64 const __A, int const __N)
653
+ ;
654
+
655
+ static __inline int __attribute__((__always_inline__))
656
+ _m_pextrw (__m64 const __A, int const __N)
657
+ ;
658
+ #else
659
+ #define _mm_extract_pi16(A, N) __builtin_ia32_vec_ext_v4hi ((__v4hi)(A), (N))
660
+ #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
661
+ #endif
662
+
663
+ /* Inserts word D into one of four words of A. The selector N must be
664
+ immediate. */
665
+ #if 0
666
+ static __inline __m64 __attribute__((__always_inline__))
667
+ _mm_insert_pi16 (__m64 const __A, int const __D, int const __N)
668
+ ;
669
+
670
+ static __inline __m64 __attribute__((__always_inline__))
671
+ _m_pinsrw (__m64 const __A, int const __D, int const __N)
672
+ ;
673
+ #else
674
+ #define _mm_insert_pi16(A, D, N) \
675
+ ((__m64) __builtin_ia32_vec_set_v4hi ((__v4hi)(A), (D), (N)))
676
+ #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
677
+ #endif
678
+
679
+ /* Compute the element-wise maximum of signed 16-bit values. */
680
+ static __inline __m64
681
+ _mm_max_pi16 (__m64 __A, __m64 __B)
682
+ ;
683
+
684
+ static __inline __m64
685
+ _m_pmaxsw (__m64 __A, __m64 __B)
686
+ ;
687
+
688
+ /* Compute the element-wise maximum of unsigned 8-bit values. */
689
+ static __inline __m64
690
+ _mm_max_pu8 (__m64 __A, __m64 __B)
691
+ ;
692
+
693
+ static __inline __m64
694
+ _m_pmaxub (__m64 __A, __m64 __B)
695
+ ;
696
+
697
+ /* Compute the element-wise minimum of signed 16-bit values. */
698
+ static __inline __m64
699
+ _mm_min_pi16 (__m64 __A, __m64 __B)
700
+ ;
701
+
702
+ static __inline __m64
703
+ _m_pminsw (__m64 __A, __m64 __B)
704
+ ;
705
+
706
+ /* Compute the element-wise minimum of unsigned 8-bit values. */
707
+ static __inline __m64
708
+ _mm_min_pu8 (__m64 __A, __m64 __B)
709
+ ;
710
+
711
+ static __inline __m64
712
+ _m_pminub (__m64 __A, __m64 __B)
713
+ ;
714
+
715
+ /* Create an 8-bit mask of the signs of 8-bit values. */
716
+ static __inline int
717
+ _mm_movemask_pi8 (__m64 __A)
718
+ ;
719
+
720
+ static __inline int
721
+ _m_pmovmskb (__m64 __A)
722
+ ;
723
+
724
+ /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
725
+ in B and produce the high 16 bits of the 32-bit results. */
726
+ static __inline __m64
727
+ _mm_mulhi_pu16 (__m64 __A, __m64 __B)
728
+ ;
729
+
730
+ static __inline __m64
731
+ _m_pmulhuw (__m64 __A, __m64 __B)
732
+ ;
733
+
734
+ /* Return a combination of the four 16-bit values in A. The selector
735
+ must be an immediate. */
736
+ #if 0
737
+ static __inline __m64
738
+ _mm_shuffle_pi16 (__m64 __A, int __N)
739
+ ;
740
+
741
+ static __inline __m64
742
+ _m_pshufw (__m64 __A, int __N)
743
+ ;
744
+ #else
745
+ #define _mm_shuffle_pi16(A, N) \
746
+ ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
747
+ #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
748
+ #endif
749
+
750
+ /* Conditionally store byte elements of A into P. The high bit of each
751
+ byte in the selector N determines whether the corresponding byte from
752
+ A is stored. */
753
+ static __inline void
754
+ _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
755
+ ;
756
+
757
+ static __inline void
758
+ _m_maskmovq (__m64 __A, __m64 __N, char *__P)
759
+ ;
760
+
761
+ /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
762
+ static __inline __m64
763
+ _mm_avg_pu8 (__m64 __A, __m64 __B)
764
+ ;
765
+
766
+ static __inline __m64
767
+ _m_pavgb (__m64 __A, __m64 __B)
768
+ ;
769
+
770
+ /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
771
+ static __inline __m64
772
+ _mm_avg_pu16 (__m64 __A, __m64 __B)
773
+ ;
774
+
775
+ static __inline __m64
776
+ _m_pavgw (__m64 __A, __m64 __B)
777
+ ;
778
+
779
+ /* Compute the sum of the absolute differences of the unsigned 8-bit
780
+ values in A and B. Return the value in the lower 16-bit word; the
781
+ upper words are cleared. */
782
+ static __inline __m64
783
+ _mm_sad_pu8 (__m64 __A, __m64 __B)
784
+ ;
785
+
786
+ static __inline __m64
787
+ _m_psadbw (__m64 __A, __m64 __B)
788
+ ;
789
+
790
+ /* Loads one cache line from address P to a location "closer" to the
791
+ processor. The selector I specifies the type of prefetch operation. */
792
+ #if 0
793
+ static __inline void
794
+ _mm_prefetch (void *__P, enum _mm_hint __I)
795
+ ;
796
+ #else
797
+ #define _mm_prefetch(P, I) \
798
+ __builtin_prefetch ((P), 0, (I))
799
+ #endif
800
+
801
+ /* Stores the data in A to the address P without polluting the caches. */
802
+ static __inline void
803
+ _mm_stream_pi (__m64 *__P, __m64 __A)
804
+ ;
805
+
806
+ /* Likewise. The address must be 16-byte aligned. */
807
+ static __inline void
808
+ _mm_stream_ps (float *__P, __m128 __A)
809
+ ;
810
+
811
+ /* Guarantees that every preceding store is globally visible before
812
+ any subsequent store. */
813
+ static __inline void
814
+ _mm_sfence (void)
815
+ ;
816
+
817
+ /* The execution of the next instruction is delayed by an implementation
818
+ specific amount of time. The instruction does not modify the
819
+ architectural state. */
820
+ static __inline void
821
+ _mm_pause (void)
822
+ ;
823
+
824
+ /* Transpose the 4x4 matrix composed of row[0-3]. */
825
+ #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
826
+ do { \
827
+ } while (0)
828
+
829
+ /* For backward source compatibility. */
830
+ #include <emmintrin.h>
831
+
832
+ #endif /* __SSE__ */
833
+ #endif /* _XMMINTRIN_H_INCLUDED */