gccxml_gem 0.9.2-x86-linux → 0.9.3-x86-linux

Sign up to get free protection for your applications and to get access to all the features.
Files changed (49) hide show
  1. data/Rakefile +15 -6
  2. data/bin/gccxml +0 -0
  3. data/bin/gccxml_cc1plus +0 -0
  4. data/gccxml.rb +5 -5
  5. data/share/gccxml-0.9/GCC/3.2/bits/gthr-default.h +4 -0
  6. data/share/gccxml-0.9/GCC/3.4/bits/gthr-default.h +5 -0
  7. data/share/gccxml-0.9/GCC/4.0/emmintrin.h +5 -0
  8. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_emmintrin.h +1037 -0
  9. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_mmintrin.h +669 -0
  10. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_xmmintrin.h +870 -0
  11. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_emmintrin.h +977 -0
  12. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_mmintrin.h +636 -0
  13. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_xmmintrin.h +833 -0
  14. data/share/gccxml-0.9/GCC/4.0/mmintrin.h +5 -0
  15. data/share/gccxml-0.9/GCC/4.0/xmmintrin.h +5 -0
  16. data/share/gccxml-0.9/GCC/4.1/bits/gthr-default.h +4 -0
  17. data/share/gccxml-0.9/GCC/4.1/emmintrin.h +5 -0
  18. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_emmintrin.h +1509 -0
  19. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_mmintrin.h +942 -0
  20. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_xmmintrin.h +1192 -0
  21. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_emmintrin.h +1004 -0
  22. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_mmintrin.h +637 -0
  23. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_xmmintrin.h +834 -0
  24. data/share/gccxml-0.9/GCC/4.1/mmintrin.h +5 -0
  25. data/share/gccxml-0.9/GCC/4.1/xmmintrin.h +5 -0
  26. data/share/gccxml-0.9/GCC/4.2/emmintrin.h +5 -0
  27. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_emmintrin.h +1509 -0
  28. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_mmintrin.h +942 -0
  29. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_xmmintrin.h +1192 -0
  30. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_emmintrin.h +1013 -0
  31. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_mmintrin.h +663 -0
  32. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_xmmintrin.h +860 -0
  33. data/share/gccxml-0.9/GCC/4.2/mmintrin.h +5 -0
  34. data/share/gccxml-0.9/GCC/4.2/xmmintrin.h +5 -0
  35. data/share/gccxml-0.9/GCC/4.3/emmintrin.h +1043 -0
  36. data/share/gccxml-0.9/GCC/4.3/gccxml_builtins.h +1 -0
  37. data/share/gccxml-0.9/GCC/4.3/mmintrin.h +663 -0
  38. data/share/gccxml-0.9/GCC/4.3/xmmintrin.h +867 -0
  39. data/share/gccxml-0.9/GCC/4.4/bits/c++config.h +1431 -0
  40. data/share/gccxml-0.9/GCC/4.4/emmintrin.h +1041 -0
  41. data/share/gccxml-0.9/GCC/4.4/gccxml_builtins.h +153 -0
  42. data/share/gccxml-0.9/GCC/4.4/mmintrin.h +662 -0
  43. data/share/gccxml-0.9/GCC/4.4/xmmintrin.h +864 -0
  44. data/share/gccxml-0.9/GCC/4.5/gccxml_builtins.h +154 -0
  45. data/share/gccxml-0.9/GCC/4.5/iomanip +349 -0
  46. data/share/gccxml-0.9/GCC/COPYING.RUNTIME +73 -0
  47. data/share/gccxml-0.9/GCC/COPYING3 +674 -0
  48. data/share/man/man1/gccxml.1 +1 -1
  49. metadata +165 -114
@@ -0,0 +1,834 @@
1
+ /* Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
2
+
3
+ This file is part of GCC.
4
+
5
+ GCC is free software; you can redistribute it and/or modify
6
+ it under the terms of the GNU General Public License as published by
7
+ the Free Software Foundation; either version 2, or (at your option)
8
+ any later version.
9
+
10
+ GCC is distributed in the hope that it will be useful,
11
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+ GNU General Public License for more details.
14
+
15
+ You should have received a copy of the GNU General Public License
16
+ along with GCC; see the file COPYING. If not, write to
17
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
18
+ Boston, MA 02110-1301, USA. */
19
+
20
+ /* As a special exception, if you include this header file into source
21
+ files compiled by GCC, this header file does not by itself cause
22
+ the resulting executable to be covered by the GNU General Public
23
+ License. This exception does not however invalidate any other
24
+ reasons why the executable file might be covered by the GNU General
25
+ Public License. */
26
+
27
+ /* Implemented from the specification included in the Intel C++ Compiler
28
+ User Guide and Reference, version 8.0. */
29
+
30
+ #ifndef _XMMINTRIN_H_INCLUDED
31
+ #define _XMMINTRIN_H_INCLUDED
32
+
33
+ #ifndef __SSE__
34
+ # error "SSE instruction set not enabled"
35
+ #else
36
+
37
+ /* We need type definitions from the MMX header file. */
38
+ #include <mmintrin.h>
39
+
40
+ /* Get _mm_malloc () and _mm_free (). */
41
+ #include <mm_malloc.h>
42
+
43
+ /* The Intel API is flexible enough that we must allow aliasing with other
44
+ vector types, and their scalar components. */
45
+ typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
46
+
47
+ /* Internal data types for implementing the intrinsics. */
48
+ typedef float __v4sf __attribute__ ((__vector_size__ (16)));
49
+
50
+ /* Create a selector for use with the SHUFPS instruction. */
51
+ #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
52
+ (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
53
+
54
+ /* Constants for use with _mm_prefetch. */
55
+ enum _mm_hint
56
+ {
57
+ _MM_HINT_T0 = 3,
58
+ _MM_HINT_T1 = 2,
59
+ _MM_HINT_T2 = 1,
60
+ _MM_HINT_NTA = 0
61
+ };
62
+
63
+ /* Bits in the MXCSR. */
64
+ #define _MM_EXCEPT_MASK 0x003f
65
+ #define _MM_EXCEPT_INVALID 0x0001
66
+ #define _MM_EXCEPT_DENORM 0x0002
67
+ #define _MM_EXCEPT_DIV_ZERO 0x0004
68
+ #define _MM_EXCEPT_OVERFLOW 0x0008
69
+ #define _MM_EXCEPT_UNDERFLOW 0x0010
70
+ #define _MM_EXCEPT_INEXACT 0x0020
71
+
72
+ #define _MM_MASK_MASK 0x1f80
73
+ #define _MM_MASK_INVALID 0x0080
74
+ #define _MM_MASK_DENORM 0x0100
75
+ #define _MM_MASK_DIV_ZERO 0x0200
76
+ #define _MM_MASK_OVERFLOW 0x0400
77
+ #define _MM_MASK_UNDERFLOW 0x0800
78
+ #define _MM_MASK_INEXACT 0x1000
79
+
80
+ #define _MM_ROUND_MASK 0x6000
81
+ #define _MM_ROUND_NEAREST 0x0000
82
+ #define _MM_ROUND_DOWN 0x2000
83
+ #define _MM_ROUND_UP 0x4000
84
+ #define _MM_ROUND_TOWARD_ZERO 0x6000
85
+
86
+ #define _MM_FLUSH_ZERO_MASK 0x8000
87
+ #define _MM_FLUSH_ZERO_ON 0x8000
88
+ #define _MM_FLUSH_ZERO_OFF 0x0000
89
+
90
+ /* Create a vector of zeros. */
91
+ static __inline __m128 __attribute__((__always_inline__))
92
+ _mm_setzero_ps (void)
93
+ ;
94
+
95
+ /* Perform the respective operation on the lower SPFP (single-precision
96
+ floating-point) values of A and B; the upper three SPFP values are
97
+ passed through from A. */
98
+
99
+ static __inline __m128 __attribute__((__always_inline__))
100
+ _mm_add_ss (__m128 __A, __m128 __B)
101
+ ;
102
+
103
+ static __inline __m128 __attribute__((__always_inline__))
104
+ _mm_sub_ss (__m128 __A, __m128 __B)
105
+ ;
106
+
107
+ static __inline __m128 __attribute__((__always_inline__))
108
+ _mm_mul_ss (__m128 __A, __m128 __B)
109
+ ;
110
+
111
+ static __inline __m128 __attribute__((__always_inline__))
112
+ _mm_div_ss (__m128 __A, __m128 __B)
113
+ ;
114
+
115
+ static __inline __m128 __attribute__((__always_inline__))
116
+ _mm_sqrt_ss (__m128 __A)
117
+ ;
118
+
119
+ static __inline __m128 __attribute__((__always_inline__))
120
+ _mm_rcp_ss (__m128 __A)
121
+ ;
122
+
123
+ static __inline __m128 __attribute__((__always_inline__))
124
+ _mm_rsqrt_ss (__m128 __A)
125
+ ;
126
+
127
+ static __inline __m128 __attribute__((__always_inline__))
128
+ _mm_min_ss (__m128 __A, __m128 __B)
129
+ ;
130
+
131
+ static __inline __m128 __attribute__((__always_inline__))
132
+ _mm_max_ss (__m128 __A, __m128 __B)
133
+ ;
134
+
135
+ /* Perform the respective operation on the four SPFP values in A and B. */
136
+
137
+ static __inline __m128 __attribute__((__always_inline__))
138
+ _mm_add_ps (__m128 __A, __m128 __B)
139
+ ;
140
+
141
+ static __inline __m128 __attribute__((__always_inline__))
142
+ _mm_sub_ps (__m128 __A, __m128 __B)
143
+ ;
144
+
145
+ static __inline __m128 __attribute__((__always_inline__))
146
+ _mm_mul_ps (__m128 __A, __m128 __B)
147
+ ;
148
+
149
+ static __inline __m128 __attribute__((__always_inline__))
150
+ _mm_div_ps (__m128 __A, __m128 __B)
151
+ ;
152
+
153
+ static __inline __m128 __attribute__((__always_inline__))
154
+ _mm_sqrt_ps (__m128 __A)
155
+ ;
156
+
157
+ static __inline __m128 __attribute__((__always_inline__))
158
+ _mm_rcp_ps (__m128 __A)
159
+ ;
160
+
161
+ static __inline __m128 __attribute__((__always_inline__))
162
+ _mm_rsqrt_ps (__m128 __A)
163
+ ;
164
+
165
+ static __inline __m128 __attribute__((__always_inline__))
166
+ _mm_min_ps (__m128 __A, __m128 __B)
167
+ ;
168
+
169
+ static __inline __m128 __attribute__((__always_inline__))
170
+ _mm_max_ps (__m128 __A, __m128 __B)
171
+ ;
172
+
173
+ /* Perform logical bit-wise operations on 128-bit values. */
174
+
175
+ static __inline __m128 __attribute__((__always_inline__))
176
+ _mm_and_ps (__m128 __A, __m128 __B)
177
+ ;
178
+
179
+ static __inline __m128 __attribute__((__always_inline__))
180
+ _mm_andnot_ps (__m128 __A, __m128 __B)
181
+ ;
182
+
183
+ static __inline __m128 __attribute__((__always_inline__))
184
+ _mm_or_ps (__m128 __A, __m128 __B)
185
+ ;
186
+
187
+ static __inline __m128 __attribute__((__always_inline__))
188
+ _mm_xor_ps (__m128 __A, __m128 __B)
189
+ ;
190
+
191
+ /* Perform a comparison on the lower SPFP values of A and B. If the
192
+ comparison is true, place a mask of all ones in the result, otherwise a
193
+ mask of zeros. The upper three SPFP values are passed through from A. */
194
+
195
+ static __inline __m128 __attribute__((__always_inline__))
196
+ _mm_cmpeq_ss (__m128 __A, __m128 __B)
197
+ ;
198
+
199
+ static __inline __m128 __attribute__((__always_inline__))
200
+ _mm_cmplt_ss (__m128 __A, __m128 __B)
201
+ ;
202
+
203
+ static __inline __m128 __attribute__((__always_inline__))
204
+ _mm_cmple_ss (__m128 __A, __m128 __B)
205
+ ;
206
+
207
+ static __inline __m128 __attribute__((__always_inline__))
208
+ _mm_cmpgt_ss (__m128 __A, __m128 __B)
209
+ ;
210
+
211
+ static __inline __m128 __attribute__((__always_inline__))
212
+ _mm_cmpge_ss (__m128 __A, __m128 __B)
213
+ ;
214
+
215
+ static __inline __m128 __attribute__((__always_inline__))
216
+ _mm_cmpneq_ss (__m128 __A, __m128 __B)
217
+ ;
218
+
219
+ static __inline __m128 __attribute__((__always_inline__))
220
+ _mm_cmpnlt_ss (__m128 __A, __m128 __B)
221
+ ;
222
+
223
+ static __inline __m128 __attribute__((__always_inline__))
224
+ _mm_cmpnle_ss (__m128 __A, __m128 __B)
225
+ ;
226
+
227
+ static __inline __m128 __attribute__((__always_inline__))
228
+ _mm_cmpngt_ss (__m128 __A, __m128 __B)
229
+ ;
230
+
231
+ static __inline __m128 __attribute__((__always_inline__))
232
+ _mm_cmpnge_ss (__m128 __A, __m128 __B)
233
+ ;
234
+
235
+ static __inline __m128 __attribute__((__always_inline__))
236
+ _mm_cmpord_ss (__m128 __A, __m128 __B)
237
+ ;
238
+
239
+ static __inline __m128 __attribute__((__always_inline__))
240
+ _mm_cmpunord_ss (__m128 __A, __m128 __B)
241
+ ;
242
+
243
+ /* Perform a comparison on the four SPFP values of A and B. For each
244
+ element, if the comparison is true, place a mask of all ones in the
245
+ result, otherwise a mask of zeros. */
246
+
247
+ static __inline __m128 __attribute__((__always_inline__))
248
+ _mm_cmpeq_ps (__m128 __A, __m128 __B)
249
+ ;
250
+
251
+ static __inline __m128 __attribute__((__always_inline__))
252
+ _mm_cmplt_ps (__m128 __A, __m128 __B)
253
+ ;
254
+
255
+ static __inline __m128 __attribute__((__always_inline__))
256
+ _mm_cmple_ps (__m128 __A, __m128 __B)
257
+ ;
258
+
259
+ static __inline __m128 __attribute__((__always_inline__))
260
+ _mm_cmpgt_ps (__m128 __A, __m128 __B)
261
+ ;
262
+
263
+ static __inline __m128 __attribute__((__always_inline__))
264
+ _mm_cmpge_ps (__m128 __A, __m128 __B)
265
+ ;
266
+
267
+ static __inline __m128 __attribute__((__always_inline__))
268
+ _mm_cmpneq_ps (__m128 __A, __m128 __B)
269
+ ;
270
+
271
+ static __inline __m128 __attribute__((__always_inline__))
272
+ _mm_cmpnlt_ps (__m128 __A, __m128 __B)
273
+ ;
274
+
275
+ static __inline __m128 __attribute__((__always_inline__))
276
+ _mm_cmpnle_ps (__m128 __A, __m128 __B)
277
+ ;
278
+
279
+ static __inline __m128 __attribute__((__always_inline__))
280
+ _mm_cmpngt_ps (__m128 __A, __m128 __B)
281
+ ;
282
+
283
+ static __inline __m128 __attribute__((__always_inline__))
284
+ _mm_cmpnge_ps (__m128 __A, __m128 __B)
285
+ ;
286
+
287
+ static __inline __m128 __attribute__((__always_inline__))
288
+ _mm_cmpord_ps (__m128 __A, __m128 __B)
289
+ ;
290
+
291
+ static __inline __m128 __attribute__((__always_inline__))
292
+ _mm_cmpunord_ps (__m128 __A, __m128 __B)
293
+ ;
294
+
295
+ /* Compare the lower SPFP values of A and B and return 1 if true
296
+ and 0 if false. */
297
+
298
+ static __inline int __attribute__((__always_inline__))
299
+ _mm_comieq_ss (__m128 __A, __m128 __B)
300
+ ;
301
+
302
+ static __inline int __attribute__((__always_inline__))
303
+ _mm_comilt_ss (__m128 __A, __m128 __B)
304
+ ;
305
+
306
+ static __inline int __attribute__((__always_inline__))
307
+ _mm_comile_ss (__m128 __A, __m128 __B)
308
+ ;
309
+
310
+ static __inline int __attribute__((__always_inline__))
311
+ _mm_comigt_ss (__m128 __A, __m128 __B)
312
+ ;
313
+
314
+ static __inline int __attribute__((__always_inline__))
315
+ _mm_comige_ss (__m128 __A, __m128 __B)
316
+ ;
317
+
318
+ static __inline int __attribute__((__always_inline__))
319
+ _mm_comineq_ss (__m128 __A, __m128 __B)
320
+ ;
321
+
322
+ static __inline int __attribute__((__always_inline__))
323
+ _mm_ucomieq_ss (__m128 __A, __m128 __B)
324
+ ;
325
+
326
+ static __inline int __attribute__((__always_inline__))
327
+ _mm_ucomilt_ss (__m128 __A, __m128 __B)
328
+ ;
329
+
330
+ static __inline int __attribute__((__always_inline__))
331
+ _mm_ucomile_ss (__m128 __A, __m128 __B)
332
+ ;
333
+
334
+ static __inline int __attribute__((__always_inline__))
335
+ _mm_ucomigt_ss (__m128 __A, __m128 __B)
336
+ ;
337
+
338
+ static __inline int __attribute__((__always_inline__))
339
+ _mm_ucomige_ss (__m128 __A, __m128 __B)
340
+ ;
341
+
342
+ static __inline int __attribute__((__always_inline__))
343
+ _mm_ucomineq_ss (__m128 __A, __m128 __B)
344
+ ;
345
+
346
+ /* Convert the lower SPFP value to a 32-bit integer according to the current
347
+ rounding mode. */
348
+ static __inline int __attribute__((__always_inline__))
349
+ _mm_cvtss_si32 (__m128 __A)
350
+ ;
351
+
352
+ static __inline int __attribute__((__always_inline__))
353
+ _mm_cvt_ss2si (__m128 __A)
354
+ ;
355
+
356
+ #ifdef __x86_64__
357
+ /* Convert the lower SPFP value to a 32-bit integer according to the current
358
+ rounding mode. */
359
+ static __inline long long __attribute__((__always_inline__))
360
+ _mm_cvtss_si64x (__m128 __A)
361
+ ;
362
+ #endif
363
+
364
+ /* Convert the two lower SPFP values to 32-bit integers according to the
365
+ current rounding mode. Return the integers in packed form. */
366
+ static __inline __m64 __attribute__((__always_inline__))
367
+ _mm_cvtps_pi32 (__m128 __A)
368
+ ;
369
+
370
+ static __inline __m64 __attribute__((__always_inline__))
371
+ _mm_cvt_ps2pi (__m128 __A)
372
+ ;
373
+
374
+ /* Truncate the lower SPFP value to a 32-bit integer. */
375
+ static __inline int __attribute__((__always_inline__))
376
+ _mm_cvttss_si32 (__m128 __A)
377
+ ;
378
+
379
+ static __inline int __attribute__((__always_inline__))
380
+ _mm_cvtt_ss2si (__m128 __A)
381
+ ;
382
+
383
+ #ifdef __x86_64__
384
+ /* Truncate the lower SPFP value to a 32-bit integer. */
385
+ static __inline long long __attribute__((__always_inline__))
386
+ _mm_cvttss_si64x (__m128 __A)
387
+ ;
388
+ #endif
389
+
390
+ /* Truncate the two lower SPFP values to 32-bit integers. Return the
391
+ integers in packed form. */
392
+ static __inline __m64 __attribute__((__always_inline__))
393
+ _mm_cvttps_pi32 (__m128 __A)
394
+ ;
395
+
396
+ static __inline __m64 __attribute__((__always_inline__))
397
+ _mm_cvtt_ps2pi (__m128 __A)
398
+ ;
399
+
400
+ /* Convert B to a SPFP value and insert it as element zero in A. */
401
+ static __inline __m128 __attribute__((__always_inline__))
402
+ _mm_cvtsi32_ss (__m128 __A, int __B)
403
+ ;
404
+
405
+ static __inline __m128 __attribute__((__always_inline__))
406
+ _mm_cvt_si2ss (__m128 __A, int __B)
407
+ ;
408
+
409
+ #ifdef __x86_64__
410
+ /* Convert B to a SPFP value and insert it as element zero in A. */
411
+ static __inline __m128 __attribute__((__always_inline__))
412
+ _mm_cvtsi64x_ss (__m128 __A, long long __B)
413
+ ;
414
+ #endif
415
+
416
+ /* Convert the two 32-bit values in B to SPFP form and insert them
417
+ as the two lower elements in A. */
418
+ static __inline __m128 __attribute__((__always_inline__))
419
+ _mm_cvtpi32_ps (__m128 __A, __m64 __B)
420
+ ;
421
+
422
+ static __inline __m128 __attribute__((__always_inline__))
423
+ _mm_cvt_pi2ps (__m128 __A, __m64 __B)
424
+ ;
425
+
426
+ /* Convert the four signed 16-bit values in A to SPFP form. */
427
+ static __inline __m128 __attribute__((__always_inline__))
428
+ _mm_cvtpi16_ps (__m64 __A)
429
+ ;
430
+
431
+ /* Convert the four unsigned 16-bit values in A to SPFP form. */
432
+ static __inline __m128 __attribute__((__always_inline__))
433
+ _mm_cvtpu16_ps (__m64 __A)
434
+ ;
435
+
436
+ /* Convert the low four signed 8-bit values in A to SPFP form. */
437
+ static __inline __m128 __attribute__((__always_inline__))
438
+ _mm_cvtpi8_ps (__m64 __A)
439
+ ;
440
+
441
+ /* Convert the low four unsigned 8-bit values in A to SPFP form. */
442
+ static __inline __m128 __attribute__((__always_inline__))
443
+ _mm_cvtpu8_ps(__m64 __A)
444
+ ;
445
+
446
+ /* Convert the four signed 32-bit values in A and B to SPFP form. */
447
+ static __inline __m128 __attribute__((__always_inline__))
448
+ _mm_cvtpi32x2_ps(__m64 __A, __m64 __B)
449
+ ;
450
+
451
+ /* Convert the four SPFP values in A to four signed 16-bit integers. */
452
+ static __inline __m64 __attribute__((__always_inline__))
453
+ _mm_cvtps_pi16(__m128 __A)
454
+ ;
455
+
456
+ /* Convert the four SPFP values in A to four signed 8-bit integers. */
457
+ static __inline __m64 __attribute__((__always_inline__))
458
+ _mm_cvtps_pi8(__m128 __A)
459
+ ;
460
+
461
+ /* Selects four specific SPFP values from A and B based on MASK. */
462
+ #if 0
463
+ static __inline __m128 __attribute__((__always_inline__))
464
+ _mm_shuffle_ps (__m128 __A, __m128 __B, int __mask)
465
+ ;
466
+ #else
467
+ #define _mm_shuffle_ps(A, B, MASK) \
468
+ ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
469
+ #endif
470
+
471
+
472
+ /* Selects and interleaves the upper two SPFP values from A and B. */
473
+ static __inline __m128 __attribute__((__always_inline__))
474
+ _mm_unpackhi_ps (__m128 __A, __m128 __B)
475
+ ;
476
+
477
+ /* Selects and interleaves the lower two SPFP values from A and B. */
478
+ static __inline __m128 __attribute__((__always_inline__))
479
+ _mm_unpacklo_ps (__m128 __A, __m128 __B)
480
+ ;
481
+
482
+ /* Sets the upper two SPFP values with 64-bits of data loaded from P;
483
+ the lower two values are passed through from A. */
484
+ static __inline __m128 __attribute__((__always_inline__))
485
+ _mm_loadh_pi (__m128 __A, __m64 const *__P)
486
+ ;
487
+
488
+ /* Stores the upper two SPFP values of A into P. */
489
+ static __inline void __attribute__((__always_inline__))
490
+ _mm_storeh_pi (__m64 *__P, __m128 __A)
491
+ ;
492
+
493
+ /* Moves the upper two values of B into the lower two values of A. */
494
+ static __inline __m128 __attribute__((__always_inline__))
495
+ _mm_movehl_ps (__m128 __A, __m128 __B)
496
+ ;
497
+
498
+ /* Moves the lower two values of B into the upper two values of A. */
499
+ static __inline __m128 __attribute__((__always_inline__))
500
+ _mm_movelh_ps (__m128 __A, __m128 __B)
501
+ ;
502
+
503
+ /* Sets the lower two SPFP values with 64-bits of data loaded from P;
504
+ the upper two values are passed through from A. */
505
+ static __inline __m128 __attribute__((__always_inline__))
506
+ _mm_loadl_pi (__m128 __A, __m64 const *__P)
507
+ ;
508
+
509
+ /* Stores the lower two SPFP values of A into P. */
510
+ static __inline void __attribute__((__always_inline__))
511
+ _mm_storel_pi (__m64 *__P, __m128 __A)
512
+ ;
513
+
514
+ /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
515
+ static __inline int __attribute__((__always_inline__))
516
+ _mm_movemask_ps (__m128 __A)
517
+ ;
518
+
519
+ /* Return the contents of the control register. */
520
+ static __inline unsigned int __attribute__((__always_inline__))
521
+ _mm_getcsr (void)
522
+ ;
523
+
524
+ /* Read exception bits from the control register. */
525
+ static __inline unsigned int __attribute__((__always_inline__))
526
+ _MM_GET_EXCEPTION_STATE (void)
527
+ ;
528
+
529
+ static __inline unsigned int __attribute__((__always_inline__))
530
+ _MM_GET_EXCEPTION_MASK (void)
531
+ ;
532
+
533
+ static __inline unsigned int __attribute__((__always_inline__))
534
+ _MM_GET_ROUNDING_MODE (void)
535
+ ;
536
+
537
+ static __inline unsigned int __attribute__((__always_inline__))
538
+ _MM_GET_FLUSH_ZERO_MODE (void)
539
+ ;
540
+
541
+ /* Set the control register to I. */
542
+ static __inline void __attribute__((__always_inline__))
543
+ _mm_setcsr (unsigned int __I)
544
+ ;
545
+
546
+ /* Set exception bits in the control register. */
547
+ static __inline void __attribute__((__always_inline__))
548
+ _MM_SET_EXCEPTION_STATE(unsigned int __mask)
549
+ ;
550
+
551
+ static __inline void __attribute__((__always_inline__))
552
+ _MM_SET_EXCEPTION_MASK (unsigned int __mask)
553
+ ;
554
+
555
+ static __inline void __attribute__((__always_inline__))
556
+ _MM_SET_ROUNDING_MODE (unsigned int __mode)
557
+ ;
558
+
559
+ static __inline void __attribute__((__always_inline__))
560
+ _MM_SET_FLUSH_ZERO_MODE (unsigned int __mode)
561
+ ;
562
+
563
+ /* Create a vector with element 0 as F and the rest zero. */
564
+ static __inline __m128 __attribute__((__always_inline__))
565
+ _mm_set_ss (float __F)
566
+ ;
567
+
568
+ /* Create a vector with all four elements equal to F. */
569
+ static __inline __m128 __attribute__((__always_inline__))
570
+ _mm_set1_ps (float __F)
571
+ ;
572
+
573
+ static __inline __m128 __attribute__((__always_inline__))
574
+ _mm_set_ps1 (float __F)
575
+ ;
576
+
577
+ /* Create a vector with element 0 as *P and the rest zero. */
578
+ static __inline __m128 __attribute__((__always_inline__))
579
+ _mm_load_ss (float const *__P)
580
+ ;
581
+
582
+ /* Create a vector with all four elements equal to *P. */
583
+ static __inline __m128 __attribute__((__always_inline__))
584
+ _mm_load1_ps (float const *__P)
585
+ ;
586
+
587
+ static __inline __m128 __attribute__((__always_inline__))
588
+ _mm_load_ps1 (float const *__P)
589
+ ;
590
+
591
+ /* Load four SPFP values from P. The address must be 16-byte aligned. */
592
+ static __inline __m128 __attribute__((__always_inline__))
593
+ _mm_load_ps (float const *__P)
594
+ ;
595
+
596
+ /* Load four SPFP values from P. The address need not be 16-byte aligned. */
597
+ static __inline __m128 __attribute__((__always_inline__))
598
+ _mm_loadu_ps (float const *__P)
599
+ ;
600
+
601
+ /* Load four SPFP values in reverse order. The address must be aligned. */
602
+ static __inline __m128 __attribute__((__always_inline__))
603
+ _mm_loadr_ps (float const *__P)
604
+ ;
605
+
606
+ /* Create the vector [Z Y X W]. */
607
+ static __inline __m128 __attribute__((__always_inline__))
608
+ _mm_set_ps (const float __Z, const float __Y, const float __X, const float __W)
609
+ ;
610
+
611
+ /* Create the vector [W X Y Z]. */
612
+ static __inline __m128 __attribute__((__always_inline__))
613
+ _mm_setr_ps (float __Z, float __Y, float __X, float __W)
614
+ ;
615
+
616
+ /* Stores the lower SPFP value. */
617
+ static __inline void __attribute__((__always_inline__))
618
+ _mm_store_ss (float *__P, __m128 __A)
619
+ ;
620
+
621
+ /* Store four SPFP values. The address must be 16-byte aligned. */
622
+ static __inline void __attribute__((__always_inline__))
623
+ _mm_store_ps (float *__P, __m128 __A)
624
+ ;
625
+
626
+ /* Store four SPFP values. The address need not be 16-byte aligned. */
627
+ static __inline void __attribute__((__always_inline__))
628
+ _mm_storeu_ps (float *__P, __m128 __A)
629
+ ;
630
+
631
+ /* Store the lower SPFP value across four words. */
632
+ static __inline void __attribute__((__always_inline__))
633
+ _mm_store1_ps (float *__P, __m128 __A)
634
+ ;
635
+
636
+ static __inline void __attribute__((__always_inline__))
637
+ _mm_store_ps1 (float *__P, __m128 __A)
638
+ ;
639
+
640
+ /* Store four SPFP values in reverse order. The address must be aligned. */
641
+ static __inline void __attribute__((__always_inline__))
642
+ _mm_storer_ps (float *__P, __m128 __A)
643
+ ;
644
+
645
+ /* Sets the low SPFP value of A from the low value of B. */
646
+ static __inline __m128 __attribute__((__always_inline__))
647
+ _mm_move_ss (__m128 __A, __m128 __B)
648
+ ;
649
+
650
+ /* Extracts one of the four words of A. The selector N must be immediate. */
651
+ #if 0
652
+ static __inline int __attribute__((__always_inline__))
653
+ _mm_extract_pi16 (__m64 const __A, int const __N)
654
+ ;
655
+
656
+ static __inline int __attribute__((__always_inline__))
657
+ _m_pextrw (__m64 const __A, int const __N)
658
+ ;
659
+ #else
660
+ #define _mm_extract_pi16(A, N) __builtin_ia32_vec_ext_v4hi ((__v4hi)(A), (N))
661
+ #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
662
+ #endif
663
+
664
+ /* Inserts word D into one of four words of A. The selector N must be
665
+ immediate. */
666
+ #if 0
667
+ static __inline __m64 __attribute__((__always_inline__))
668
+ _mm_insert_pi16 (__m64 const __A, int const __D, int const __N)
669
+ ;
670
+
671
+ static __inline __m64 __attribute__((__always_inline__))
672
+ _m_pinsrw (__m64 const __A, int const __D, int const __N)
673
+ ;
674
+ #else
675
+ #define _mm_insert_pi16(A, D, N) \
676
+ ((__m64) __builtin_ia32_vec_set_v4hi ((__v4hi)(A), (D), (N)))
677
+ #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
678
+ #endif
679
+
680
+ /* Compute the element-wise maximum of signed 16-bit values. */
681
+ static __inline __m64 __attribute__((__always_inline__))
682
+ _mm_max_pi16 (__m64 __A, __m64 __B)
683
+ ;
684
+
685
+ static __inline __m64 __attribute__((__always_inline__))
686
+ _m_pmaxsw (__m64 __A, __m64 __B)
687
+ ;
688
+
689
+ /* Compute the element-wise maximum of unsigned 8-bit values. */
690
+ static __inline __m64 __attribute__((__always_inline__))
691
+ _mm_max_pu8 (__m64 __A, __m64 __B)
692
+ ;
693
+
694
+ static __inline __m64 __attribute__((__always_inline__))
695
+ _m_pmaxub (__m64 __A, __m64 __B)
696
+ ;
697
+
698
+ /* Compute the element-wise minimum of signed 16-bit values. */
699
+ static __inline __m64 __attribute__((__always_inline__))
700
+ _mm_min_pi16 (__m64 __A, __m64 __B)
701
+ ;
702
+
703
+ static __inline __m64 __attribute__((__always_inline__))
704
+ _m_pminsw (__m64 __A, __m64 __B)
705
+ ;
706
+
707
+ /* Compute the element-wise minimum of unsigned 8-bit values. */
708
+ static __inline __m64 __attribute__((__always_inline__))
709
+ _mm_min_pu8 (__m64 __A, __m64 __B)
710
+ ;
711
+
712
+ static __inline __m64 __attribute__((__always_inline__))
713
+ _m_pminub (__m64 __A, __m64 __B)
714
+ ;
715
+
716
+ /* Create an 8-bit mask of the signs of 8-bit values. */
717
+ static __inline int __attribute__((__always_inline__))
718
+ _mm_movemask_pi8 (__m64 __A)
719
+ ;
720
+
721
+ static __inline int __attribute__((__always_inline__))
722
+ _m_pmovmskb (__m64 __A)
723
+ ;
724
+
725
+ /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
726
+ in B and produce the high 16 bits of the 32-bit results. */
727
+ static __inline __m64 __attribute__((__always_inline__))
728
+ _mm_mulhi_pu16 (__m64 __A, __m64 __B)
729
+ ;
730
+
731
+ static __inline __m64 __attribute__((__always_inline__))
732
+ _m_pmulhuw (__m64 __A, __m64 __B)
733
+ ;
734
+
735
+ /* Return a combination of the four 16-bit values in A. The selector
736
+ must be an immediate. */
737
+ #if 0
738
+ static __inline __m64 __attribute__((__always_inline__))
739
+ _mm_shuffle_pi16 (__m64 __A, int __N)
740
+ ;
741
+
742
+ static __inline __m64 __attribute__((__always_inline__))
743
+ _m_pshufw (__m64 __A, int __N)
744
+ ;
745
+ #else
746
+ #define _mm_shuffle_pi16(A, N) \
747
+ ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
748
+ #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
749
+ #endif
750
+
751
+ /* Conditionally store byte elements of A into P. The high bit of each
752
+ byte in the selector N determines whether the corresponding byte from
753
+ A is stored. */
754
+ static __inline void __attribute__((__always_inline__))
755
+ _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
756
+ ;
757
+
758
+ static __inline void __attribute__((__always_inline__))
759
+ _m_maskmovq (__m64 __A, __m64 __N, char *__P)
760
+ ;
761
+
762
+ /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
763
+ static __inline __m64 __attribute__((__always_inline__))
764
+ _mm_avg_pu8 (__m64 __A, __m64 __B)
765
+ ;
766
+
767
+ static __inline __m64 __attribute__((__always_inline__))
768
+ _m_pavgb (__m64 __A, __m64 __B)
769
+ ;
770
+
771
+ /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
772
+ static __inline __m64 __attribute__((__always_inline__))
773
+ _mm_avg_pu16 (__m64 __A, __m64 __B)
774
+ ;
775
+
776
+ static __inline __m64 __attribute__((__always_inline__))
777
+ _m_pavgw (__m64 __A, __m64 __B)
778
+ ;
779
+
780
+ /* Compute the sum of the absolute differences of the unsigned 8-bit
781
+ values in A and B. Return the value in the lower 16-bit word; the
782
+ upper words are cleared. */
783
+ static __inline __m64 __attribute__((__always_inline__))
784
+ _mm_sad_pu8 (__m64 __A, __m64 __B)
785
+ ;
786
+
787
+ static __inline __m64 __attribute__((__always_inline__))
788
+ _m_psadbw (__m64 __A, __m64 __B)
789
+ ;
790
+
791
+ /* Loads one cache line from address P to a location "closer" to the
792
+ processor. The selector I specifies the type of prefetch operation. */
793
+ #if 0
794
+ static __inline void __attribute__((__always_inline__))
795
+ _mm_prefetch (void *__P, enum _mm_hint __I)
796
+ ;
797
+ #else
798
+ #define _mm_prefetch(P, I) \
799
+ __builtin_prefetch ((P), 0, (I))
800
+ #endif
801
+
802
+ /* Stores the data in A to the address P without polluting the caches. */
803
+ static __inline void __attribute__((__always_inline__))
804
+ _mm_stream_pi (__m64 *__P, __m64 __A)
805
+ ;
806
+
807
+ /* Likewise. The address must be 16-byte aligned. */
808
+ static __inline void __attribute__((__always_inline__))
809
+ _mm_stream_ps (float *__P, __m128 __A)
810
+ ;
811
+
812
+ /* Guarantees that every preceding store is globally visible before
813
+ any subsequent store. */
814
+ static __inline void __attribute__((__always_inline__))
815
+ _mm_sfence (void)
816
+ ;
817
+
818
+ /* The execution of the next instruction is delayed by an implementation
819
+ specific amount of time. The instruction does not modify the
820
+ architectural state. */
821
+ static __inline void __attribute__((__always_inline__))
822
+ _mm_pause (void)
823
+ ;
824
+
825
+ /* Transpose the 4x4 matrix composed of row[0-3]. */
826
+ #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
827
+ do { \
828
+ } while (0)
829
+
830
+ /* For backward source compatibility. */
831
+ #include <emmintrin.h>
832
+
833
+ #endif /* __SSE__ */
834
+ #endif /* _XMMINTRIN_H_INCLUDED */