gccxml_gem 0.9.2-x86-linux → 0.9.3-x86-linux

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Files changed (49) hide show
  1. data/Rakefile +15 -6
  2. data/bin/gccxml +0 -0
  3. data/bin/gccxml_cc1plus +0 -0
  4. data/gccxml.rb +5 -5
  5. data/share/gccxml-0.9/GCC/3.2/bits/gthr-default.h +4 -0
  6. data/share/gccxml-0.9/GCC/3.4/bits/gthr-default.h +5 -0
  7. data/share/gccxml-0.9/GCC/4.0/emmintrin.h +5 -0
  8. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_emmintrin.h +1037 -0
  9. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_mmintrin.h +669 -0
  10. data/share/gccxml-0.9/GCC/4.0/gccxml_apple_xmmintrin.h +870 -0
  11. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_emmintrin.h +977 -0
  12. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_mmintrin.h +636 -0
  13. data/share/gccxml-0.9/GCC/4.0/gccxml_gnu_xmmintrin.h +833 -0
  14. data/share/gccxml-0.9/GCC/4.0/mmintrin.h +5 -0
  15. data/share/gccxml-0.9/GCC/4.0/xmmintrin.h +5 -0
  16. data/share/gccxml-0.9/GCC/4.1/bits/gthr-default.h +4 -0
  17. data/share/gccxml-0.9/GCC/4.1/emmintrin.h +5 -0
  18. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_emmintrin.h +1509 -0
  19. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_mmintrin.h +942 -0
  20. data/share/gccxml-0.9/GCC/4.1/gccxml_apple_xmmintrin.h +1192 -0
  21. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_emmintrin.h +1004 -0
  22. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_mmintrin.h +637 -0
  23. data/share/gccxml-0.9/GCC/4.1/gccxml_gnu_xmmintrin.h +834 -0
  24. data/share/gccxml-0.9/GCC/4.1/mmintrin.h +5 -0
  25. data/share/gccxml-0.9/GCC/4.1/xmmintrin.h +5 -0
  26. data/share/gccxml-0.9/GCC/4.2/emmintrin.h +5 -0
  27. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_emmintrin.h +1509 -0
  28. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_mmintrin.h +942 -0
  29. data/share/gccxml-0.9/GCC/4.2/gccxml_apple_xmmintrin.h +1192 -0
  30. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_emmintrin.h +1013 -0
  31. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_mmintrin.h +663 -0
  32. data/share/gccxml-0.9/GCC/4.2/gccxml_gnu_xmmintrin.h +860 -0
  33. data/share/gccxml-0.9/GCC/4.2/mmintrin.h +5 -0
  34. data/share/gccxml-0.9/GCC/4.2/xmmintrin.h +5 -0
  35. data/share/gccxml-0.9/GCC/4.3/emmintrin.h +1043 -0
  36. data/share/gccxml-0.9/GCC/4.3/gccxml_builtins.h +1 -0
  37. data/share/gccxml-0.9/GCC/4.3/mmintrin.h +663 -0
  38. data/share/gccxml-0.9/GCC/4.3/xmmintrin.h +867 -0
  39. data/share/gccxml-0.9/GCC/4.4/bits/c++config.h +1431 -0
  40. data/share/gccxml-0.9/GCC/4.4/emmintrin.h +1041 -0
  41. data/share/gccxml-0.9/GCC/4.4/gccxml_builtins.h +153 -0
  42. data/share/gccxml-0.9/GCC/4.4/mmintrin.h +662 -0
  43. data/share/gccxml-0.9/GCC/4.4/xmmintrin.h +864 -0
  44. data/share/gccxml-0.9/GCC/4.5/gccxml_builtins.h +154 -0
  45. data/share/gccxml-0.9/GCC/4.5/iomanip +349 -0
  46. data/share/gccxml-0.9/GCC/COPYING.RUNTIME +73 -0
  47. data/share/gccxml-0.9/GCC/COPYING3 +674 -0
  48. data/share/man/man1/gccxml.1 +1 -1
  49. metadata +165 -114
@@ -0,0 +1,870 @@
1
+ /* APPLE LOCAL file mainline 2005-06-30 Radar 4131077 */
2
+ /* Copyright (C) 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3
+
4
+ This file is part of GCC.
5
+
6
+ GCC is free software; you can redistribute it and/or modify
7
+ it under the terms of the GNU General Public License as published by
8
+ the Free Software Foundation; either version 2, or (at your option)
9
+ any later version.
10
+
11
+ GCC is distributed in the hope that it will be useful,
12
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+ GNU General Public License for more details.
15
+
16
+ You should have received a copy of the GNU General Public License
17
+ along with GCC; see the file COPYING. If not, write to
18
+ the Free Software Foundation, 59 Temple Place - Suite 330,
19
+ Boston, MA 02111-1307, USA. */
20
+
21
+ /* As a special exception, if you include this header file into source
22
+ files compiled by GCC, this header file does not by itself cause
23
+ the resulting executable to be covered by the GNU General Public
24
+ License. This exception does not however invalidate any other
25
+ reasons why the executable file might be covered by the GNU General
26
+ Public License. */
27
+
28
+ /* Implemented from the specification included in the Intel C++ Compiler
29
+ User Guide and Reference, version 9.0. */
30
+
31
+ #ifndef _XMMINTRIN_H_INCLUDED
32
+ #define _XMMINTRIN_H_INCLUDED
33
+
34
+ #ifndef __SSE__
35
+ # error "SSE instruction set not enabled"
36
+ #else
37
+
38
+ /* We need type definitions from the MMX header file. */
39
+ #include <mmintrin.h>
40
+
41
+ /* Get _mm_malloc () and _mm_free (). */
42
+ #include <mm_malloc.h>
43
+
44
+ /* The data type intended for user use. */
45
+ typedef float __m128 __attribute__ ((__vector_size__ (16)));
46
+
47
+ /* Internal data types for implementing the intrinsics. */
48
+ typedef float __v4sf __attribute__ ((__vector_size__ (16)));
49
+
50
+ /* Create a selector for use with the SHUFPS instruction. */
51
+ #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
52
+ (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
53
+
54
+ /* Constants for use with _mm_prefetch. */
55
+ enum _mm_hint
56
+ {
57
+ _MM_HINT_T0 = 3,
58
+ _MM_HINT_T1 = 2,
59
+ _MM_HINT_T2 = 1,
60
+ _MM_HINT_NTA = 0
61
+ };
62
+
63
+ /* Bits in the MXCSR. */
64
+ #define _MM_EXCEPT_MASK 0x003f
65
+ #define _MM_EXCEPT_INVALID 0x0001
66
+ #define _MM_EXCEPT_DENORM 0x0002
67
+ #define _MM_EXCEPT_DIV_ZERO 0x0004
68
+ #define _MM_EXCEPT_OVERFLOW 0x0008
69
+ #define _MM_EXCEPT_UNDERFLOW 0x0010
70
+ #define _MM_EXCEPT_INEXACT 0x0020
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+
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+ #define _MM_MASK_MASK 0x1f80
73
+ #define _MM_MASK_INVALID 0x0080
74
+ #define _MM_MASK_DENORM 0x0100
75
+ #define _MM_MASK_DIV_ZERO 0x0200
76
+ #define _MM_MASK_OVERFLOW 0x0400
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+ #define _MM_MASK_UNDERFLOW 0x0800
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+ #define _MM_MASK_INEXACT 0x1000
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+
80
+ #define _MM_ROUND_MASK 0x6000
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+ #define _MM_ROUND_NEAREST 0x0000
82
+ #define _MM_ROUND_DOWN 0x2000
83
+ #define _MM_ROUND_UP 0x4000
84
+ #define _MM_ROUND_TOWARD_ZERO 0x6000
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+
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+ #define _MM_FLUSH_ZERO_MASK 0x8000
87
+ #define _MM_FLUSH_ZERO_ON 0x8000
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+ #define _MM_FLUSH_ZERO_OFF 0x0000
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+
90
+ /* APPLE LOCAL begin nodebug inline 4152603 */
91
+ #define __always_inline__ __always_inline__, __nodebug__
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+ /* APPLE LOCAL end nodebug inline 4152603 */
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+
94
+ /* Create a vector of zeros. */
95
+ /* APPLE LOCAL begin radar 4152603 */
96
+ static __inline __m128 __attribute__((__always_inline__))
97
+ _mm_setzero_ps (void)
98
+ ;
99
+
100
+ /* Perform the respective operation on the lower SPFP (single-precision
101
+ floating-point) values of A and B; the upper three SPFP values are
102
+ passed through from A. */
103
+
104
+ static __inline __m128 __attribute__((__always_inline__))
105
+ _mm_add_ss (__m128 __A, __m128 __B)
106
+ ;
107
+
108
+ static __inline __m128 __attribute__((__always_inline__))
109
+ _mm_sub_ss (__m128 __A, __m128 __B)
110
+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
113
+ _mm_mul_ss (__m128 __A, __m128 __B)
114
+ ;
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+
116
+ static __inline __m128 __attribute__((__always_inline__))
117
+ _mm_div_ss (__m128 __A, __m128 __B)
118
+ ;
119
+
120
+ static __inline __m128 __attribute__((__always_inline__))
121
+ _mm_sqrt_ss (__m128 __A)
122
+ ;
123
+
124
+ static __inline __m128 __attribute__((__always_inline__))
125
+ _mm_rcp_ss (__m128 __A)
126
+ ;
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+
128
+ static __inline __m128 __attribute__((__always_inline__))
129
+ _mm_rsqrt_ss (__m128 __A)
130
+ ;
131
+
132
+ static __inline __m128 __attribute__((__always_inline__))
133
+ _mm_min_ss (__m128 __A, __m128 __B)
134
+ ;
135
+
136
+ static __inline __m128 __attribute__((__always_inline__))
137
+ _mm_max_ss (__m128 __A, __m128 __B)
138
+ ;
139
+
140
+ /* Perform the respective operation on the four SPFP values in A and B. */
141
+
142
+ static __inline __m128 __attribute__((__always_inline__))
143
+ _mm_add_ps (__m128 __A, __m128 __B)
144
+ ;
145
+
146
+ static __inline __m128 __attribute__((__always_inline__))
147
+ _mm_sub_ps (__m128 __A, __m128 __B)
148
+ ;
149
+
150
+ static __inline __m128 __attribute__((__always_inline__))
151
+ _mm_mul_ps (__m128 __A, __m128 __B)
152
+ ;
153
+
154
+ static __inline __m128 __attribute__((__always_inline__))
155
+ _mm_div_ps (__m128 __A, __m128 __B)
156
+ ;
157
+
158
+ static __inline __m128 __attribute__((__always_inline__))
159
+ _mm_sqrt_ps (__m128 __A)
160
+ ;
161
+
162
+ static __inline __m128 __attribute__((__always_inline__))
163
+ _mm_rcp_ps (__m128 __A)
164
+ ;
165
+
166
+ static __inline __m128 __attribute__((__always_inline__))
167
+ _mm_rsqrt_ps (__m128 __A)
168
+ ;
169
+
170
+ static __inline __m128 __attribute__((__always_inline__))
171
+ _mm_min_ps (__m128 __A, __m128 __B)
172
+ ;
173
+
174
+ static __inline __m128 __attribute__((__always_inline__))
175
+ _mm_max_ps (__m128 __A, __m128 __B)
176
+ ;
177
+
178
+ /* Perform logical bit-wise operations on 128-bit values. */
179
+
180
+ static __inline __m128 __attribute__((__always_inline__))
181
+ _mm_and_ps (__m128 __A, __m128 __B)
182
+ ;
183
+
184
+ static __inline __m128 __attribute__((__always_inline__))
185
+ _mm_andnot_ps (__m128 __A, __m128 __B)
186
+ ;
187
+
188
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_or_ps (__m128 __A, __m128 __B)
190
+ ;
191
+
192
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_xor_ps (__m128 __A, __m128 __B)
194
+ ;
195
+
196
+ /* Perform a comparison on the lower SPFP values of A and B. If the
197
+ comparison is true, place a mask of all ones in the result, otherwise a
198
+ mask of zeros. The upper three SPFP values are passed through from A. */
199
+
200
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpeq_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmplt_ss (__m128 __A, __m128 __B)
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+ ;
207
+
208
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmple_ss (__m128 __A, __m128 __B)
210
+ ;
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+
212
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpgt_ss (__m128 __A, __m128 __B)
214
+ ;
215
+
216
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpge_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpneq_ss (__m128 __A, __m128 __B)
222
+ ;
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+
224
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnlt_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnle_ss (__m128 __A, __m128 __B)
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+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpngt_ss (__m128 __A, __m128 __B)
234
+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnge_ss (__m128 __A, __m128 __B)
238
+ ;
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+
240
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpord_ss (__m128 __A, __m128 __B)
242
+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpunord_ss (__m128 __A, __m128 __B)
246
+ ;
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+
248
+ /* Perform a comparison on the four SPFP values of A and B. For each
249
+ element, if the comparison is true, place a mask of all ones in the
250
+ result, otherwise a mask of zeros. */
251
+
252
+ static __inline __m128 __attribute__((__always_inline__))
253
+ _mm_cmpeq_ps (__m128 __A, __m128 __B)
254
+ ;
255
+
256
+ static __inline __m128 __attribute__((__always_inline__))
257
+ _mm_cmplt_ps (__m128 __A, __m128 __B)
258
+ ;
259
+
260
+ static __inline __m128 __attribute__((__always_inline__))
261
+ _mm_cmple_ps (__m128 __A, __m128 __B)
262
+ ;
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+
264
+ static __inline __m128 __attribute__((__always_inline__))
265
+ _mm_cmpgt_ps (__m128 __A, __m128 __B)
266
+ ;
267
+
268
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpge_ps (__m128 __A, __m128 __B)
270
+ ;
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+
272
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpneq_ps (__m128 __A, __m128 __B)
274
+ ;
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+
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+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnlt_ps (__m128 __A, __m128 __B)
278
+ ;
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+
280
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnle_ps (__m128 __A, __m128 __B)
282
+ ;
283
+
284
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpngt_ps (__m128 __A, __m128 __B)
286
+ ;
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+
288
+ static __inline __m128 __attribute__((__always_inline__))
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+ _mm_cmpnge_ps (__m128 __A, __m128 __B)
290
+ ;
291
+
292
+ static __inline __m128 __attribute__((__always_inline__))
293
+ _mm_cmpord_ps (__m128 __A, __m128 __B)
294
+ ;
295
+
296
+ static __inline __m128 __attribute__((__always_inline__))
297
+ _mm_cmpunord_ps (__m128 __A, __m128 __B)
298
+ ;
299
+
300
+ /* Compare the lower SPFP values of A and B and return 1 if true
301
+ and 0 if false. */
302
+
303
+ static __inline int __attribute__((__always_inline__))
304
+ _mm_comieq_ss (__m128 __A, __m128 __B)
305
+ ;
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+
307
+ static __inline int __attribute__((__always_inline__))
308
+ _mm_comilt_ss (__m128 __A, __m128 __B)
309
+ ;
310
+
311
+ static __inline int __attribute__((__always_inline__))
312
+ _mm_comile_ss (__m128 __A, __m128 __B)
313
+ ;
314
+
315
+ static __inline int __attribute__((__always_inline__))
316
+ _mm_comigt_ss (__m128 __A, __m128 __B)
317
+ ;
318
+
319
+ static __inline int __attribute__((__always_inline__))
320
+ _mm_comige_ss (__m128 __A, __m128 __B)
321
+ ;
322
+
323
+ static __inline int __attribute__((__always_inline__))
324
+ _mm_comineq_ss (__m128 __A, __m128 __B)
325
+ ;
326
+
327
+ static __inline int __attribute__((__always_inline__))
328
+ _mm_ucomieq_ss (__m128 __A, __m128 __B)
329
+ ;
330
+
331
+ static __inline int __attribute__((__always_inline__))
332
+ _mm_ucomilt_ss (__m128 __A, __m128 __B)
333
+ ;
334
+
335
+ static __inline int __attribute__((__always_inline__))
336
+ _mm_ucomile_ss (__m128 __A, __m128 __B)
337
+ ;
338
+
339
+ static __inline int __attribute__((__always_inline__))
340
+ _mm_ucomigt_ss (__m128 __A, __m128 __B)
341
+ ;
342
+
343
+ static __inline int __attribute__((__always_inline__))
344
+ _mm_ucomige_ss (__m128 __A, __m128 __B)
345
+ ;
346
+
347
+ static __inline int __attribute__((__always_inline__))
348
+ _mm_ucomineq_ss (__m128 __A, __m128 __B)
349
+ ;
350
+
351
+ /* Convert the lower SPFP value to a 32-bit integer according to the current
352
+ rounding mode. */
353
+ static __inline int __attribute__((__always_inline__))
354
+ _mm_cvtss_si32 (__m128 __A)
355
+ ;
356
+
357
+ static __inline int __attribute__((__always_inline__))
358
+ _mm_cvt_ss2si (__m128 __A)
359
+ ;
360
+
361
+ #ifdef __x86_64__
362
+ /* Convert the lower SPFP value to a 32-bit integer according to the
363
+ current rounding mode. */
364
+ /* Intel intrinsic. */
365
+ static __inline long long __attribute__((__always_inline__))
366
+ _mm_cvtss_si64 (__m128 __A)
367
+ ;
368
+
369
+ /* Microsoft intrinsic. */
370
+ static __inline long long __attribute__((__always_inline__))
371
+ _mm_cvtss_si64x (__m128 __A)
372
+ ;
373
+ #endif
374
+
375
+ /* Convert the two lower SPFP values to 32-bit integers according to the
376
+ current rounding mode. Return the integers in packed form. */
377
+ static __inline __m64 __attribute__((__always_inline__))
378
+ _mm_cvtps_pi32 (__m128 __A)
379
+ ;
380
+
381
+ static __inline __m64 __attribute__((__always_inline__))
382
+ _mm_cvt_ps2pi (__m128 __A)
383
+ ;
384
+
385
+ /* Truncate the lower SPFP value to a 32-bit integer. */
386
+ static __inline int __attribute__((__always_inline__))
387
+ _mm_cvttss_si32 (__m128 __A)
388
+ ;
389
+
390
+ static __inline int __attribute__((__always_inline__))
391
+ _mm_cvtt_ss2si (__m128 __A)
392
+ ;
393
+
394
+ #ifdef __x86_64__
395
+ /* Truncate the lower SPFP value to a 32-bit integer. */
396
+
397
+ /* Intel intrinsic. */
398
+ static __inline long long __attribute__((__always_inline__))
399
+ _mm_cvttss_si64 (__m128 __A)
400
+ ;
401
+
402
+ /* Microsoft intrinsic. */
403
+ static __inline long long __attribute__((__always_inline__))
404
+ _mm_cvttss_si64x (__m128 __A)
405
+ ;
406
+ #endif
407
+
408
+ /* Truncate the two lower SPFP values to 32-bit integers. Return the
409
+ integers in packed form. */
410
+ static __inline __m64 __attribute__((__always_inline__))
411
+ _mm_cvttps_pi32 (__m128 __A)
412
+ ;
413
+
414
+ static __inline __m64 __attribute__((__always_inline__))
415
+ _mm_cvtt_ps2pi (__m128 __A)
416
+ ;
417
+
418
+ /* Convert B to a SPFP value and insert it as element zero in A. */
419
+ static __inline __m128 __attribute__((__always_inline__))
420
+ _mm_cvtsi32_ss (__m128 __A, int __B)
421
+ ;
422
+
423
+ static __inline __m128 __attribute__((__always_inline__))
424
+ _mm_cvt_si2ss (__m128 __A, int __B)
425
+ ;
426
+
427
+ #ifdef __x86_64__
428
+ /* Convert B to a SPFP value and insert it as element zero in A. */
429
+
430
+ /* Intel intrinsic. */
431
+ static __inline __m128 __attribute__((__always_inline__))
432
+ _mm_cvtsi64_ss (__m128 __A, long long __B)
433
+ ;
434
+
435
+ /* Microsoft intrinsic. */
436
+ static __inline __m128 __attribute__((__always_inline__))
437
+ _mm_cvtsi64x_ss (__m128 __A, long long __B)
438
+ ;
439
+ #endif
440
+
441
+ /* Convert the two 32-bit values in B to SPFP form and insert them
442
+ as the two lower elements in A. */
443
+ static __inline __m128 __attribute__((__always_inline__))
444
+ _mm_cvtpi32_ps (__m128 __A, __m64 __B)
445
+ ;
446
+
447
+ static __inline __m128 __attribute__((__always_inline__))
448
+ _mm_cvt_pi2ps (__m128 __A, __m64 __B)
449
+ ;
450
+
451
+ /* Convert the four signed 16-bit values in A to SPFP form. */
452
+ static __inline __m128 __attribute__((__always_inline__))
453
+ _mm_cvtpi16_ps (__m64 __A)
454
+ ;
455
+
456
+ /* Convert the four unsigned 16-bit values in A to SPFP form. */
457
+ static __inline __m128 __attribute__((__always_inline__))
458
+ _mm_cvtpu16_ps (__m64 __A)
459
+ ;
460
+
461
+ /* Convert the low four signed 8-bit values in A to SPFP form. */
462
+ static __inline __m128 __attribute__((__always_inline__))
463
+ _mm_cvtpi8_ps (__m64 __A)
464
+ ;
465
+
466
+ /* Convert the low four unsigned 8-bit values in A to SPFP form. */
467
+ static __inline __m128 __attribute__((__always_inline__))
468
+ _mm_cvtpu8_ps(__m64 __A)
469
+ ;
470
+
471
+ /* Convert the four signed 32-bit values in A and B to SPFP form. */
472
+ static __inline __m128 __attribute__((__always_inline__))
473
+ _mm_cvtpi32x2_ps(__m64 __A, __m64 __B)
474
+ ;
475
+
476
+ /* Convert the four SPFP values in A to four signed 16-bit integers. */
477
+ static __inline __m64 __attribute__((__always_inline__))
478
+ _mm_cvtps_pi16(__m128 __A)
479
+ ;
480
+
481
+ /* Convert the four SPFP values in A to four signed 8-bit integers. */
482
+ static __inline __m64 __attribute__((__always_inline__))
483
+ _mm_cvtps_pi8(__m128 __A)
484
+ ;
485
+
486
+ /* Selects four specific SPFP values from A and B based on MASK. */
487
+ #if 0
488
+ static __inline __m128 __attribute__((__always_inline__))
489
+ _mm_shuffle_ps (__m128 __A, __m128 __B, int __mask)
490
+ ;
491
+ #else
492
+ #define _mm_shuffle_ps(A, B, MASK) \
493
+ ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
494
+ #endif
495
+
496
+
497
+ /* Selects and interleaves the upper two SPFP values from A and B. */
498
+ static __inline __m128 __attribute__((__always_inline__))
499
+ _mm_unpackhi_ps (__m128 __A, __m128 __B)
500
+ ;
501
+
502
+ /* Selects and interleaves the lower two SPFP values from A and B. */
503
+ static __inline __m128 __attribute__((__always_inline__))
504
+ _mm_unpacklo_ps (__m128 __A, __m128 __B)
505
+ ;
506
+
507
+ /* Sets the upper two SPFP values with 64-bits of data loaded from P;
508
+ the lower two values are passed through from A. */
509
+ static __inline __m128 __attribute__((__always_inline__))
510
+ _mm_loadh_pi (__m128 __A, __m64 const *__P)
511
+ ;
512
+
513
+ /* Stores the upper two SPFP values of A into P. */
514
+ static __inline void __attribute__((__always_inline__))
515
+ _mm_storeh_pi (__m64 *__P, __m128 __A)
516
+ ;
517
+
518
+ /* Moves the upper two values of B into the lower two values of A. */
519
+ static __inline __m128 __attribute__((__always_inline__))
520
+ _mm_movehl_ps (__m128 __A, __m128 __B)
521
+ ;
522
+
523
+ /* Moves the lower two values of B into the upper two values of A. */
524
+ static __inline __m128 __attribute__((__always_inline__))
525
+ _mm_movelh_ps (__m128 __A, __m128 __B)
526
+ ;
527
+
528
+ /* Sets the lower two SPFP values with 64-bits of data loaded from P;
529
+ the upper two values are passed through from A. */
530
+ static __inline __m128 __attribute__((__always_inline__))
531
+ _mm_loadl_pi (__m128 __A, __m64 const *__P)
532
+ ;
533
+
534
+ /* Stores the lower two SPFP values of A into P. */
535
+ static __inline void __attribute__((__always_inline__))
536
+ _mm_storel_pi (__m64 *__P, __m128 __A)
537
+ ;
538
+
539
+ /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
540
+ static __inline int __attribute__((__always_inline__))
541
+ _mm_movemask_ps (__m128 __A)
542
+ ;
543
+
544
+ /* Return the contents of the control register. */
545
+ static __inline unsigned int __attribute__((__always_inline__))
546
+ _mm_getcsr (void)
547
+ ;
548
+
549
+ /* Read exception bits from the control register. */
550
+ static __inline unsigned int __attribute__((__always_inline__))
551
+ _MM_GET_EXCEPTION_STATE (void)
552
+ ;
553
+
554
+ static __inline unsigned int __attribute__((__always_inline__))
555
+ _MM_GET_EXCEPTION_MASK (void)
556
+ ;
557
+
558
+ static __inline unsigned int __attribute__((__always_inline__))
559
+ _MM_GET_ROUNDING_MODE (void)
560
+ ;
561
+
562
+ static __inline unsigned int __attribute__((__always_inline__))
563
+ _MM_GET_FLUSH_ZERO_MODE (void)
564
+ ;
565
+
566
+ /* Set the control register to I. */
567
+ static __inline void __attribute__((__always_inline__))
568
+ _mm_setcsr (unsigned int __I)
569
+ ;
570
+
571
+ /* Set exception bits in the control register. */
572
+ static __inline void __attribute__((__always_inline__))
573
+ _MM_SET_EXCEPTION_STATE(unsigned int __mask)
574
+ ;
575
+
576
+ static __inline void __attribute__((__always_inline__))
577
+ _MM_SET_EXCEPTION_MASK (unsigned int __mask)
578
+ ;
579
+
580
+ static __inline void __attribute__((__always_inline__))
581
+ _MM_SET_ROUNDING_MODE (unsigned int __mode)
582
+ ;
583
+
584
+ static __inline void __attribute__((__always_inline__))
585
+ _MM_SET_FLUSH_ZERO_MODE (unsigned int __mode)
586
+ ;
587
+
588
+ /* Create a vector with element 0 as F and the rest zero. */
589
+ static __inline __m128 __attribute__((__always_inline__))
590
+ _mm_set_ss (float __F)
591
+ ;
592
+
593
+ /* Create a vector with all four elements equal to F. */
594
+ static __inline __m128 __attribute__((__always_inline__))
595
+ _mm_set1_ps (float __F)
596
+ ;
597
+
598
+ static __inline __m128 __attribute__((__always_inline__))
599
+ _mm_set_ps1 (float __F)
600
+ ;
601
+
602
+ /* Create a vector with element 0 as *P and the rest zero. */
603
+ static __inline __m128 __attribute__((__always_inline__))
604
+ _mm_load_ss (float const *__P)
605
+ ;
606
+
607
+ /* Create a vector with all four elements equal to *P. */
608
+ static __inline __m128 __attribute__((__always_inline__))
609
+ _mm_load1_ps (float const *__P)
610
+ ;
611
+
612
+ static __inline __m128 __attribute__((__always_inline__))
613
+ _mm_load_ps1 (float const *__P)
614
+ ;
615
+
616
+ /* Load four SPFP values from P. The address must be 16-byte aligned. */
617
+ static __inline __m128 __attribute__((__always_inline__))
618
+ _mm_load_ps (float const *__P)
619
+ ;
620
+
621
+ /* Load four SPFP values from P. The address need not be 16-byte aligned. */
622
+ static __inline __m128 __attribute__((__always_inline__))
623
+ _mm_loadu_ps (float const *__P)
624
+ ;
625
+
626
+ /* Load four SPFP values in reverse order. The address must be aligned. */
627
+ static __inline __m128 __attribute__((__always_inline__))
628
+ _mm_loadr_ps (float const *__P)
629
+ ;
630
+
631
+ /* Create the vector [Z Y X W]. */
632
+ static __inline __m128 __attribute__((__always_inline__))
633
+ _mm_set_ps (const float __Z, const float __Y, const float __X, const float __W)
634
+ ;
635
+
636
+ /* Create the vector [W X Y Z]. */
637
+ static __inline __m128 __attribute__((__always_inline__))
638
+ _mm_setr_ps (float __Z, float __Y, float __X, float __W)
639
+ ;
640
+
641
+ /* Stores the lower SPFP value. */
642
+ static __inline void __attribute__((__always_inline__))
643
+ _mm_store_ss (float *__P, __m128 __A)
644
+ ;
645
+
646
+ static __inline float __attribute__((__always_inline__))
647
+ _mm_cvtss_f32 (__m128 __A)
648
+ ;
649
+
650
+ /* Store four SPFP values. The address must be 16-byte aligned. */
651
+ static __inline void __attribute__((__always_inline__))
652
+ _mm_store_ps (float *__P, __m128 __A)
653
+ ;
654
+
655
+ /* Store four SPFP values. The address need not be 16-byte aligned. */
656
+ static __inline void __attribute__((__always_inline__))
657
+ _mm_storeu_ps (float *__P, __m128 __A)
658
+ ;
659
+
660
+ /* Store the lower SPFP value across four words. */
661
+ static __inline void __attribute__((__always_inline__))
662
+ _mm_store1_ps (float *__P, __m128 __A)
663
+ ;
664
+
665
+ static __inline void __attribute__((__always_inline__))
666
+ _mm_store_ps1 (float *__P, __m128 __A)
667
+ ;
668
+
669
+ /* Store four SPFP values in reverse order. The address must be aligned. */
670
+ static __inline void __attribute__((__always_inline__))
671
+ _mm_storer_ps (float *__P, __m128 __A)
672
+ ;
673
+
674
+ /* Sets the low SPFP value of A from the low value of B. */
675
+ static __inline __m128 __attribute__((__always_inline__))
676
+ _mm_move_ss (__m128 __A, __m128 __B)
677
+ ;
678
+
679
+ /* Extracts one of the four words of A. The selector N must be immediate. */
680
+ #if 0
681
+ static __inline int __attribute__((__always_inline__))
682
+ _mm_extract_pi16 (__m64 const __A, int const __N)
683
+ ;
684
+
685
+ static __inline int __attribute__((__always_inline__))
686
+ _m_pextrw (__m64 const __A, int const __N)
687
+ ;
688
+ #else
689
+ #define _mm_extract_pi16(A, N) __builtin_ia32_vec_ext_v4hi ((__v4hi)(A), (N))
690
+ #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
691
+ #endif
692
+
693
+ /* Inserts word D into one of four words of A. The selector N must be
694
+ immediate. */
695
+ #if 0
696
+ static __inline __m64 __attribute__((__always_inline__))
697
+ _mm_insert_pi16 (__m64 const __A, int const __D, int const __N)
698
+ ;
699
+
700
+ static __inline __m64 __attribute__((__always_inline__))
701
+ _m_pinsrw (__m64 const __A, int const __D, int const __N)
702
+ ;
703
+ #else
704
+ #define _mm_insert_pi16(A, D, N) \
705
+ ((__m64) __builtin_ia32_vec_set_v4hi ((__v4hi)(A), (D), (N)))
706
+ #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
707
+ #endif
708
+
709
+ /* Compute the element-wise maximum of signed 16-bit values. */
710
+ static __inline __m64 __attribute__((__always_inline__))
711
+ _mm_max_pi16 (__m64 __A, __m64 __B)
712
+ ;
713
+
714
+ static __inline __m64 __attribute__((__always_inline__))
715
+ _m_pmaxsw (__m64 __A, __m64 __B)
716
+ ;
717
+
718
+ /* Compute the element-wise maximum of unsigned 8-bit values. */
719
+ static __inline __m64 __attribute__((__always_inline__))
720
+ _mm_max_pu8 (__m64 __A, __m64 __B)
721
+ ;
722
+
723
+ static __inline __m64 __attribute__((__always_inline__))
724
+ _m_pmaxub (__m64 __A, __m64 __B)
725
+ ;
726
+
727
+ /* Compute the element-wise minimum of signed 16-bit values. */
728
+ static __inline __m64 __attribute__((__always_inline__))
729
+ _mm_min_pi16 (__m64 __A, __m64 __B)
730
+ ;
731
+
732
+ static __inline __m64 __attribute__((__always_inline__))
733
+ _m_pminsw (__m64 __A, __m64 __B)
734
+ ;
735
+
736
+ /* Compute the element-wise minimum of unsigned 8-bit values. */
737
+ static __inline __m64 __attribute__((__always_inline__))
738
+ _mm_min_pu8 (__m64 __A, __m64 __B)
739
+ ;
740
+
741
+ static __inline __m64 __attribute__((__always_inline__))
742
+ _m_pminub (__m64 __A, __m64 __B)
743
+ ;
744
+
745
+ /* Create an 8-bit mask of the signs of 8-bit values. */
746
+ static __inline int __attribute__((__always_inline__))
747
+ _mm_movemask_pi8 (__m64 __A)
748
+ ;
749
+
750
+ static __inline int __attribute__((__always_inline__))
751
+ _m_pmovmskb (__m64 __A)
752
+ ;
753
+
754
+ /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
755
+ in B and produce the high 16 bits of the 32-bit results. */
756
+ static __inline __m64 __attribute__((__always_inline__))
757
+ _mm_mulhi_pu16 (__m64 __A, __m64 __B)
758
+ ;
759
+
760
+ static __inline __m64 __attribute__((__always_inline__))
761
+ _m_pmulhuw (__m64 __A, __m64 __B)
762
+ ;
763
+
764
+ /* Return a combination of the four 16-bit values in A. The selector
765
+ must be an immediate. */
766
+ #if 0
767
+ static __inline __m64 __attribute__((__always_inline__))
768
+ _mm_shuffle_pi16 (__m64 __A, int __N)
769
+ ;
770
+
771
+ static __inline __m64 __attribute__((__always_inline__))
772
+ _m_pshufw (__m64 __A, int __N)
773
+ ;
774
+ #else
775
+ #define _mm_shuffle_pi16(A, N) \
776
+ ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
777
+ #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
778
+ #endif
779
+
780
+ /* Conditionally store byte elements of A into P. The high bit of each
781
+ byte in the selector N determines whether the corresponding byte from
782
+ A is stored. */
783
+ static __inline void __attribute__((__always_inline__))
784
+ _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
785
+ ;
786
+
787
+ static __inline void __attribute__((__always_inline__))
788
+ _m_maskmovq (__m64 __A, __m64 __N, char *__P)
789
+ ;
790
+
791
+ /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
792
+ static __inline __m64 __attribute__((__always_inline__))
793
+ _mm_avg_pu8 (__m64 __A, __m64 __B)
794
+ ;
795
+
796
+ static __inline __m64 __attribute__((__always_inline__))
797
+ _m_pavgb (__m64 __A, __m64 __B)
798
+ ;
799
+
800
+ /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
801
+ static __inline __m64 __attribute__((__always_inline__))
802
+ _mm_avg_pu16 (__m64 __A, __m64 __B)
803
+ ;
804
+
805
+ static __inline __m64 __attribute__((__always_inline__))
806
+ _m_pavgw (__m64 __A, __m64 __B)
807
+ ;
808
+
809
+ /* Compute the sum of the absolute differences of the unsigned 8-bit
810
+ values in A and B. Return the value in the lower 16-bit word; the
811
+ upper words are cleared. */
812
+ static __inline __m64 __attribute__((__always_inline__))
813
+ _mm_sad_pu8 (__m64 __A, __m64 __B)
814
+ ;
815
+
816
+ static __inline __m64 __attribute__((__always_inline__))
817
+ _m_psadbw (__m64 __A, __m64 __B)
818
+ ;
819
+
820
+ /* Loads one cache line from address P to a location "closer" to the
821
+ processor. The selector I specifies the type of prefetch operation. */
822
+ #if 0
823
+ static __inline void __attribute__((__always_inline__))
824
+ _mm_prefetch (void *__P, enum _mm_hint __I)
825
+ ;
826
+ #else
827
+ #define _mm_prefetch(P, I) \
828
+ __builtin_prefetch ((P), 0, (I))
829
+ #endif
830
+
831
+ /* Stores the data in A to the address P without polluting the caches. */
832
+ static __inline void __attribute__((__always_inline__))
833
+ _mm_stream_pi (__m64 *__P, __m64 __A)
834
+ ;
835
+
836
+ /* Likewise. The address must be 16-byte aligned. */
837
+ static __inline void __attribute__((__always_inline__))
838
+ _mm_stream_ps (float *__P, __m128 __A)
839
+ ;
840
+
841
+ /* Guarantees that every preceding store is globally visible before
842
+ any subsequent store. */
843
+ static __inline void __attribute__((__always_inline__))
844
+ _mm_sfence (void)
845
+ ;
846
+
847
+ /* The execution of the next instruction is delayed by an implementation
848
+ specific amount of time. The instruction does not modify the
849
+ architectural state. */
850
+ static __inline void __attribute__((__always_inline__))
851
+ _mm_pause (void)
852
+ ;
853
+ /* APPLE LOCAL end radar 4152603 */
854
+
855
+ /* APPPLE LOCAL begin radar 4109832 */
856
+ /* Transpose the 4x4 matrix composed of row[0-3]. */
857
+ #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
858
+ do { \
859
+ } while (0)
860
+ /* APPPLE LOCAL end radar 4109832 */
861
+
862
+ /* APPLE LOCAL begin nodebug inline 4152603 */
863
+ #undef __always_inline__
864
+ /* APPLE LOCAL end nodebug inline 4152603 */
865
+
866
+ /* For backward source compatibility. */
867
+ #include <emmintrin.h>
868
+
869
+ #endif /* __SSE__ */
870
+ #endif /* _XMMINTRIN_H_INCLUDED */