faiss 0.6.4 → 0.6.5

data/vendor/faiss/faiss/utils/simd_levels.cpp

@@ -30,6 +30,8 @@ uint64_t SIMDConfig::supported_simd_levels = 0;
 // Microarchitecture flags (x86). Default false; set by
 // detect_x86_uarch_flags() at load time.
 bool SIMDConfig::avx512_split = false;
+bool SIMDConfig::scalar_gather = false;
+bool SIMDConfig::sq_avx512_4_accumulators = false;
 
 // Resolved here rather than in the header so that dependents, which never see
 // FAISS_ENABLE_DD, still get the answer for the faiss they link against.
@@ -137,6 +139,13 @@ void detect_x86_uarch_flags() {
     // AMD Zen 4 / Zen 4c (Bergamo) is family 0x19 and splits AVX-512.
     // (Zen 5, family 0x1A, has a native 512-bit datapath and is excluded.)
     SIMDConfig::avx512_split = is_amd && display_family == 0x19u;
+    // Measured on Milan, Bergamo (0x19) and Turin (0x1A); other AMD families
+    // keep the gather kernels.
+    SIMDConfig::scalar_gather =
+            is_amd && (display_family == 0x19u || display_family == 0x1Au);
+    // Measured on Bergamo (0x19) and Turin (0x1A). Intel Skylake and Sapphire
+    // Rapids are faster with one accumulator.
+    SIMDConfig::sq_avx512_4_accumulators = SIMDConfig::scalar_gather;
 }
 
 #else // Not x86-64
@@ -191,6 +200,8 @@ SIMDConfig::SIMDConfig(const char** faiss_simd_level_env) {
     if (!env_var) {
         level = auto_detect_simd_level();
     } else {
+        // The microarchitecture flags describe the CPU, not the forced level.
+        detect_x86_uarch_flags();
         // Forcing a level the CPU lacks is allowed. Forcing one the binary
         // does not hold is not: dispatch would fall to NONE and skip every
         // level between. Walk down to the nearest compiled level instead.
@@ -274,7 +285,9 @@ SIMDLevel SIMDConfig::auto_detect_simd_level() {
 
 #if defined(COMPILE_SIMD_AVX2) || defined(COMPILE_SIMD_AVX512)
         bool has_avx2 = (ebx7 & (1 << 5)) != 0;
-        if (has_avx2) {
+        // The AVX2 and higher SIMD files compile with -mbmi2.
+        bool has_bmi2 = (ebx7 & (1 << 8)) != 0;
+        if (has_avx2 && has_bmi2) {
             supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::AVX2));
             detected_level = SIMDLevel::AVX2;
         }
@@ -282,7 +295,7 @@ SIMDLevel SIMDConfig::auto_detect_simd_level() {
 #if defined(COMPILE_SIMD_AVX512)
         bool cpu_has_avx512f = (ebx7 & (1 << 16)) != 0;
         bool os_supports_avx512 = (xcr0 & 0xE0) == 0xE0;
-        bool has_avx512f = cpu_has_avx512f && os_supports_avx512;
+        bool has_avx512f = cpu_has_avx512f && os_supports_avx512 && has_bmi2;
         if (has_avx512f) {
             bool has_avx512cd = (ebx7 & (1 << 28)) != 0;
             bool has_avx512vl = (ebx7 & (1 << 31)) != 0;
@@ -342,7 +355,10 @@ SIMDLevel SIMDConfig::auto_detect_simd_level() {
 #endif
 
 #if defined(__riscv) && defined(COMPILE_SIMD_RISCV_RVV)
-    // RVV is always available on RISC-V builds compiled with rv64gcv.
+    // RVV is always available on RISC-V builds compiled with
+    // rv64gcv_zvfhmin: that ISA (including Zvfhmin, used by the QT_fp16
+    // kernels) is the minimum requirement to run such binaries at all,
+    // so no runtime feature check is needed beyond the build contract.
     supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::RISCV_RVV));
     detected_level = SIMDLevel::RISCV_RVV;
 #endif

data/vendor/faiss/faiss/utils/simd_levels.h

@@ -26,7 +26,11 @@ enum class SIMDLevel {
     ARM_NEON,
     ARM_SVE, // Scalable Vector Extension (ARMv8.2+)
     // riscv
-    RISCV_RVV, // RISC-V Vector Extension (rv64gcv)
+    // RISC-V Vector Extension. The minimum ISA for this level is rv64gcv
+    // plus Zvfhmin (FP16 vector conversion), which the QT_fp16 kernels
+    // require; RVV translation units are compiled with
+    // -march=rv64gcv_zvfhmin.
+    RISCV_RVV,
 
     // Appended to preserve the numeric values of the existing public enum.
     // AVX-512 core features plus AVX512_VPOPCNTDQ and AVX512_BITALG
@@ -36,6 +40,65 @@ enum class SIMDLevel {
     COUNT
 };
 
+/***************************************************************
+ * FAISS_SIMD_TU(L): 1 if the library contains SIMD level L
+ * (COMPILE_SIMD_L) and the current translation unit can use the
+ * instructions of L (compiler macro), else 0. Use it to guard level
+ * code in headers that common files also include, for example
+ * `#if FAISS_SIMD_TU(AVX512)`. It is function-like, so a header that
+ * uses it without including this file fails to compile.
+ ***************************************************************/
+#ifdef SWIG
+#define FAISS_SIMD_TU(level) 0
+#else
+
+#if defined(COMPILE_SIMD_AVX2) && defined(__AVX2__)
+#define FAISS_SIMD_TU_AVX2 1
+#else
+#define FAISS_SIMD_TU_AVX2 0
+#endif
+
+#if defined(COMPILE_SIMD_AVX512) && defined(__AVX512F__)
+#define FAISS_SIMD_TU_AVX512 1
+#else
+#define FAISS_SIMD_TU_AVX512 0
+#endif
+
+#if defined(COMPILE_SIMD_AVX512_VPOPCNT) && defined(__AVX512VPOPCNTDQ__)
+#define FAISS_SIMD_TU_AVX512_VPOPCNT 1
+#else
+#define FAISS_SIMD_TU_AVX512_VPOPCNT 0
+#endif
+
+#if defined(COMPILE_SIMD_AVX512_SPR) && defined(__AVX512FP16__)
+#define FAISS_SIMD_TU_AVX512_SPR 1
+#else
+#define FAISS_SIMD_TU_AVX512_SPR 0
+#endif
+
+// __aarch64__ is not defined by MSVC, which cannot compile the NEON code.
+#if defined(COMPILE_SIMD_ARM_NEON) && defined(__aarch64__)
+#define FAISS_SIMD_TU_ARM_NEON 1
+#else
+#define FAISS_SIMD_TU_ARM_NEON 0
+#endif
+
+#if defined(COMPILE_SIMD_ARM_SVE) && defined(__ARM_FEATURE_SVE)
+#define FAISS_SIMD_TU_ARM_SVE 1
+#else
+#define FAISS_SIMD_TU_ARM_SVE 0
+#endif
+
+#if defined(COMPILE_SIMD_RISCV_RVV) && defined(__riscv_vector)
+#define FAISS_SIMD_TU_RISCV_RVV 1
+#else
+#define FAISS_SIMD_TU_RISCV_RVV 0
+#endif
+
+#define FAISS_SIMD_TU(level) FAISS_SIMD_TU_##level
+
+#endif // SWIG
+
 /***************************************************************
  * SINGLE_SIMD_LEVEL: the SIMD level for code without explicit SL context.
  *
@@ -183,6 +246,16 @@ struct FAISS_API SIMDConfig {
     /// 256-bit kernel.
     static bool avx512_split;
 
+    /// Scalar table lookups beat gathers (AMD Zen 3, Zen 4 and Zen 5,
+    /// families 0x19 and 0x1A), so the 8-bit PQ code-distance kernels use
+    /// the scalar path instead of gathers.
+    static bool scalar_gather;
+
+    /// Same CPUs as scalar_gather. The AVX-512 QT_fp16, QT_bf16 and QT_8bit
+    /// inner-product distance loops use four accumulators per code at a
+    /// large d.
+    static bool sq_avx512_4_accumulators;
+
     static SIMDLevel auto_detect_simd_level();
 
     /// Whether this faiss build dispatches SIMD at runtime.

data/vendor/faiss/faiss/utils/transpose/transpose-avx2-inl.h

@@ -10,8 +10,6 @@
 // This file contains transposing kernels for AVX2 for
 // tiny float/int32 matrices, such as 8x2.
 
-#ifdef __AVX2__
-
 #include <immintrin.h>
 
 namespace faiss {
@@ -161,5 +159,3 @@ inline void transpose_8x8(
 }
 
 } // namespace faiss
-
-#endif

data/vendor/faiss/faiss/utils/transpose/transpose-avx512-inl.h

@@ -10,8 +10,6 @@
 // This file contains transposing kernels for AVX512 for // tiny float/int32
 // matrices, such as 16x2.
 
-#ifdef __AVX512F__
-
 #include <immintrin.h>
 
 namespace faiss {
@@ -172,5 +170,3 @@ inline void transpose_16x8(
 }
 
 } // namespace faiss
-
-#endif

data/vendor/faiss/faiss/utils/utils.cpp

@@ -28,14 +28,19 @@
 #include <omp.h>
 
 #include <algorithm>
+#include <atomic>
 #include <set>
 #include <type_traits>
 #include <unordered_set>
+#include <utility>
 #include <vector>
 
 #include <faiss/impl/AuxIndexStructures.h>
 #include <faiss/impl/FaissAssert.h>
+#include <faiss/impl/simd_dispatch.h>
 #include <faiss/utils/random.h>
+#include <faiss/utils/simd_impl/fp16_kernels.h>
+#include <faiss/utils/sorting.h>
 
 #ifndef FINTEGER
 #define FINTEGER long
@@ -175,6 +180,18 @@ uint64_t get_cycles() {
 #endif
 }
 
+namespace {
+std::atomic<bool> search_stats_enabled{true};
+} // namespace
+
+void set_search_stats_enabled(bool enabled) {
+    search_stats_enabled.store(enabled, std::memory_order_relaxed);
+}
+
+bool get_search_stats_enabled() {
+    return search_stats_enabled.load(std::memory_order_relaxed);
+}
+
 #ifdef __linux__
 
 size_t get_mem_usage_kb() {
@@ -461,6 +478,51 @@ void bvecs_checksum(size_t n, size_t d, const uint8_t* a, uint64_t* cs) {
     }
 }
 
+size_t find_duplicate_codes(
+        size_t n,
+        size_t code_size,
+        const uint8_t* codes,
+        int64_t* rep) {
+    constexpr int64_t nbucket = 1 << 16;
+    std::vector<uint64_t> hash(n), bucket(n);
+    // the low bits of a checksum only depend on the low bits of its inputs
+#pragma omp parallel for
+    for (int64_t i = 0; i < int64_t(n); i++) {
+        hash[i] = SplitMix64RandomGenerator(
+                          bvec_checksum(code_size, codes + i * code_size))
+                          .next();
+        bucket[i] = hash[i] % nbucket;
+    }
+    std::vector<int64_t> lims(nbucket + 1), order(n);
+    bucket_sort(n, bucket.data(), nbucket, lims.data(), order.data());
+
+    size_t n_distinct = 0;
+#pragma omp parallel for schedule(dynamic) reduction(+ : n_distinct)
+    for (int64_t b = 0; b < nbucket; b++) {
+        int64_t* begin = order.data() + lims[b];
+        int64_t* end = order.data() + lims[b + 1];
+        std::sort(begin, end, [&](int64_t x, int64_t y) {
+            return std::pair(hash[x], x) < std::pair(hash[y], y);
+        });
+        const int64_t* group = begin;
+        for (const int64_t* r = begin; r < end; r++) {
+            if (hash[*r] != hash[*group]) {
+                group = r;
+            }
+            const int64_t* q = group;
+            while (q < r &&
+                   memcmp(codes + *q * code_size,
+                          codes + *r * code_size,
+                          code_size) != 0) {
+                q++;
+            }
+            rep[*r] = *q;
+            n_distinct += q == r;
+        }
+    }
+    return n_distinct;
+}
+
 const float* fvecs_maybe_subsample(
         size_t d,
         size_t* n,
@@ -626,6 +688,24 @@ void CombinerRangeKNN<T>::write_result(T* D_res, int64_t* I_res) {
 template struct CombinerRangeKNN<float>;
 template struct CombinerRangeKNN<int16_t>;
 
+void fp16_to_fp32(size_t n, const uint16_t* x, float* out) {
+    // below this many values, stay on the calling thread
+    constexpr size_t block = size_t(1) << 16;
+    with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_BASE>([&]<SIMDLevel SL>() {
+        if (n <= block) {
+            detail::fp16_to_fp32_kernel<SL>(n, x, out);
+            return;
+        }
+        const int64_t nblock = static_cast<int64_t>((n + block - 1) / block);
+#pragma omp parallel for
+        for (int64_t b = 0; b < nblock; b++) {
+            const size_t j0 = static_cast<size_t>(b) * block;
+            detail::fp16_to_fp32_kernel<SL>(
+                    std::min(block, n - j0), x + j0, out + j0);
+        }
+    });
+}
+
 void CodeSet::insert(size_t n, const uint8_t* codes, bool* inserted) {
     for (size_t i = 0; i < n; i++) {
         auto res = s.insert(

data/vendor/faiss/faiss/utils/utils.h

@@ -48,6 +48,14 @@ size_t get_mem_usage_kb();
 
 uint64_t get_cycles();
 
+/** Enable or disable the collection of global search statistics (enabled by
+ * default). The flag is process-wide. When it is disabled, searches may skip
+ * updates to global stats objects, so their values are unspecified. At the
+ * moment, the flag controls hnsw_stats and rabitq_stats.
+ */
+void set_search_stats_enabled(bool enabled);
+bool get_search_stats_enabled();
+
 /***************************************************************************
  * Misc  matrix and vector manipulation functions
  ***************************************************************************/
@@ -122,6 +130,14 @@ uint64_t bvec_checksum(size_t n, const uint8_t* a);
  */
 void bvecs_checksum(size_t n, size_t d, const uint8_t* a, uint64_t* cs);
 
+/// rep[i]: lowest row whose code equals code i (codes: n x code_size).
+/// Returns the number of distinct codes.
+size_t find_duplicate_codes(
+        size_t n,
+        size_t code_size,
+        const uint8_t* codes,
+        int64_t* rep);
+
 /** random subsamples a set of vectors if there are too many of them
  *
  * @param d      dimension of the vectors
@@ -156,6 +172,14 @@ void binary_to_real(size_t d, const uint8_t* x_in, float* x_out);
  */
 void real_to_binary(size_t d, const float* x_in, uint8_t* x_out);
 
+/** Convert packed IEEE binary16 values to fp32 (exact).
+ *
+ * @param n    number of values
+ * @param x    input fp16 values, size n
+ * @param out  output fp32 values, size n
+ */
+void fp16_to_fp32(size_t n, const uint16_t* x, float* out);
+
 /** A reasonable hashing function */
 uint64_t hash_bytes(const uint8_t* bytes, int64_t n);
 

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: faiss
 version: !ruby/object:Gem::Version
-  version: 0.6.4
+  version: 0.6.5
 platform: ruby
 authors:
 - Andrew Kane
@@ -123,6 +123,8 @@ files:
 - vendor/faiss/faiss/IndexIVFRaBitQ.h
 - vendor/faiss/faiss/IndexIVFRaBitQFastScan.cpp
 - vendor/faiss/faiss/IndexIVFRaBitQFastScan.h
+- vendor/faiss/faiss/IndexIVFSQFastScan.cpp
+- vendor/faiss/faiss/IndexIVFSQFastScan.h
 - vendor/faiss/faiss/IndexIVFSpectralHash.cpp
 - vendor/faiss/faiss/IndexIVFSpectralHash.h
 - vendor/faiss/faiss/IndexLSH.cpp
@@ -139,6 +141,8 @@ files:
 - vendor/faiss/faiss/IndexPQ.h
 - vendor/faiss/faiss/IndexPQFastScan.cpp
 - vendor/faiss/faiss/IndexPQFastScan.h
+- vendor/faiss/faiss/IndexPiPNN.cpp
+- vendor/faiss/faiss/IndexPiPNN.h
 - vendor/faiss/faiss/IndexPreTransform.cpp
 - vendor/faiss/faiss/IndexPreTransform.h
 - vendor/faiss/faiss/IndexRaBitQ.cpp
@@ -151,6 +155,8 @@ files:
 - vendor/faiss/faiss/IndexReplicas.h
 - vendor/faiss/faiss/IndexRowwiseMinMax.cpp
 - vendor/faiss/faiss/IndexRowwiseMinMax.h
+- vendor/faiss/faiss/IndexSQFastScan.cpp
+- vendor/faiss/faiss/IndexSQFastScan.h
 - vendor/faiss/faiss/IndexScalarQuantizer.cpp
 - vendor/faiss/faiss/IndexScalarQuantizer.h
 - vendor/faiss/faiss/IndexShards.cpp
@@ -183,6 +189,7 @@ files:
 - vendor/faiss/faiss/cppcontrib/sa_decode/PQ-neon-inl.h
 - vendor/faiss/faiss/factory_tools.cpp
 - vendor/faiss/faiss/factory_tools.h
+- vendor/faiss/faiss/gpu/Dataset.h
 - vendor/faiss/faiss/gpu/GpuAutoTune.cpp
 - vendor/faiss/faiss/gpu/GpuAutoTune.h
 - vendor/faiss/faiss/gpu/GpuCloner.cpp
@@ -216,6 +223,7 @@ files:
 - vendor/faiss/faiss/gpu/perf/PerfIVFPQAdd.cpp
 - vendor/faiss/faiss/gpu/perf/WriteIndex.cpp
 - vendor/faiss/faiss/gpu/test/TestCodePacking.cpp
+- vendor/faiss/faiss/gpu/test/TestGpuDatasetHeader.cpp
 - vendor/faiss/faiss/gpu/test/TestGpuIcmEncoder.cpp
 - vendor/faiss/faiss/gpu/test/TestGpuIndexBinaryFlat.cpp
 - vendor/faiss/faiss/gpu/test/TestGpuIndexFlat.cpp
@@ -240,6 +248,7 @@ files:
 - vendor/faiss/faiss/gpu_metal/MetalDistance.h
 - vendor/faiss/faiss/gpu_metal/MetalFlatKernels.h
 - vendor/faiss/faiss/gpu_metal/MetalIndex.h
+- vendor/faiss/faiss/gpu_metal/MetalIndexBinaryFlat.h
 - vendor/faiss/faiss/gpu_metal/MetalIndexFlat.h
 - vendor/faiss/faiss/gpu_metal/MetalIndexIVFFlat.h
 - vendor/faiss/faiss/gpu_metal/MetalIndexIVFPQ.h
@@ -263,6 +272,7 @@ files:
 - vendor/faiss/faiss/impl/CodePacker.h
 - vendor/faiss/faiss/impl/CodePackerRaBitQ.cpp
 - vendor/faiss/faiss/impl/CodePackerRaBitQ.h
+- vendor/faiss/faiss/impl/DistanceComputer.cpp
 - vendor/faiss/faiss/impl/DistanceComputer.h
 - vendor/faiss/faiss/impl/EDENQuantizer.h
 - vendor/faiss/faiss/impl/FaissAssert.h
@@ -285,6 +295,8 @@ files:
 - vendor/faiss/faiss/impl/PanoramaStats.h
 - vendor/faiss/faiss/impl/PdxLayout.cpp
 - vendor/faiss/faiss/impl/PdxLayout.h
+- vendor/faiss/faiss/impl/PiPNN.cpp
+- vendor/faiss/faiss/impl/PiPNN.h
 - vendor/faiss/faiss/impl/PolysemousTraining.cpp
 - vendor/faiss/faiss/impl/PolysemousTraining.h
 - vendor/faiss/faiss/impl/ProductAdditiveQuantizer.cpp
@@ -338,6 +350,7 @@ files:
 - vendor/faiss/faiss/impl/fast_scan/impl-avx512.cpp
 - vendor/faiss/faiss/impl/fast_scan/impl-neon.cpp
 - vendor/faiss/faiss/impl/fast_scan/impl-riscv.cpp
+- vendor/faiss/faiss/impl/fast_scan/kernels_neon.h
 - vendor/faiss/faiss/impl/fast_scan/kernels_simd256.h
 - vendor/faiss/faiss/impl/fast_scan/kernels_simd512.h
 - vendor/faiss/faiss/impl/fast_scan/rabitq_dispatching.h
@@ -362,6 +375,12 @@ files:
 - vendor/faiss/faiss/impl/mapped_io.cpp
 - vendor/faiss/faiss/impl/mapped_io.h
 - vendor/faiss/faiss/impl/maybe_owned_vector.h
+- vendor/faiss/faiss/impl/pipnn/HashPrune.cpp
+- vendor/faiss/faiss/impl/pipnn/HashPrune.h
+- vendor/faiss/faiss/impl/pipnn/Partition.cpp
+- vendor/faiss/faiss/impl/pipnn/Partition.h
+- vendor/faiss/faiss/impl/pipnn/kernels.cpp
+- vendor/faiss/faiss/impl/pipnn/kernels.h
 - vendor/faiss/faiss/impl/platform_macros.h
 - vendor/faiss/faiss/impl/polysemous_training/avx512.cpp
 - vendor/faiss/faiss/impl/polysemous_training/dispatch.h
@@ -378,6 +397,7 @@ files:
 - vendor/faiss/faiss/impl/pq_code_distance/pq_code_distance-generic.h
 - vendor/faiss/faiss/impl/pq_code_distance/pq_code_distance-inl.h
 - vendor/faiss/faiss/impl/pq_code_distance/pq_code_distance-sve.cpp
+- vendor/faiss/faiss/impl/pq_code_distance/pq_rvv_kernel.h
 - vendor/faiss/faiss/impl/pq_code_distance/pq_scan_impl.h
 - vendor/faiss/faiss/impl/pq_code_distance/rvv.cpp
 - vendor/faiss/faiss/impl/residual_quantizer_encode_steps.cpp
@@ -400,6 +420,8 @@ files:
 - vendor/faiss/faiss/impl/scalar_quantizer/sq-dispatch.h
 - vendor/faiss/faiss/impl/scalar_quantizer/sq-neon.cpp
 - vendor/faiss/faiss/impl/scalar_quantizer/sq-rvv.cpp
+- vendor/faiss/faiss/impl/scalar_quantizer/sq8_coefficients.h
+- vendor/faiss/faiss/impl/scalar_quantizer/sq8_rvv_kernel.h
 - vendor/faiss/faiss/impl/scalar_quantizer/training.cpp
 - vendor/faiss/faiss/impl/scalar_quantizer/training.h
 - vendor/faiss/faiss/impl/simd_dispatch.h
@@ -410,6 +432,7 @@ files:
 - vendor/faiss/faiss/impl/simdlib/simdlib_emulated.h
 - vendor/faiss/faiss/impl/simdlib/simdlib_neon.h
 - vendor/faiss/faiss/impl/simdlib/simdlib_ppc64.h
+- vendor/faiss/faiss/impl/sq_fastscan_utils.h
 - vendor/faiss/faiss/impl/svs_io.cpp
 - vendor/faiss/faiss/impl/svs_io.h
 - vendor/faiss/faiss/impl/zerocopy_io.cpp
@@ -459,6 +482,7 @@ files:
 - vendor/faiss/faiss/utils/distances_fused/avx512.cpp
 - vendor/faiss/faiss/utils/distances_fused/distances_fused.cpp
 - vendor/faiss/faiss/utils/distances_fused/distances_fused.h
+- vendor/faiss/faiss/utils/distances_fused/rvv.cpp
 - vendor/faiss/faiss/utils/distances_fused/simdlib_based.cpp
 - vendor/faiss/faiss/utils/distances_fused/simdlib_based_neon.cpp
 - vendor/faiss/faiss/utils/distances_fused/simdlib_kernel-inl.h
@@ -504,10 +528,18 @@ files:
 - vendor/faiss/faiss/utils/simd_impl/distances_avx2.cpp
 - vendor/faiss/faiss/utils/simd_impl/distances_avx512.cpp
 - vendor/faiss/faiss/utils/simd_impl/distances_rvv.cpp
+- vendor/faiss/faiss/utils/simd_impl/distances_rvv_kernel.h
 - vendor/faiss/faiss/utils/simd_impl/distances_simdlib256.h
 - vendor/faiss/faiss/utils/simd_impl/distances_sse-inl.h
 - vendor/faiss/faiss/utils/simd_impl/exhaustive_L2sqr_blas_cmax.h
+- vendor/faiss/faiss/utils/simd_impl/fp16_kernels.h
+- vendor/faiss/faiss/utils/simd_impl/fp16_kernels_avx2.cpp
+- vendor/faiss/faiss/utils/simd_impl/fp16_kernels_avx512.cpp
+- vendor/faiss/faiss/utils/simd_impl/fp16_kernels_neon.cpp
 - vendor/faiss/faiss/utils/simd_impl/hamming_impl.h
+- vendor/faiss/faiss/utils/simd_impl/masked_sum-avx2.h
+- vendor/faiss/faiss/utils/simd_impl/masked_sum-avx512.h
+- vendor/faiss/faiss/utils/simd_impl/masked_sum.h
 - vendor/faiss/faiss/utils/simd_impl/partitioning_avx2.cpp
 - vendor/faiss/faiss/utils/simd_impl/partitioning_neon.cpp
 - vendor/faiss/faiss/utils/simd_impl/partitioning_simdlib256.h