faiss 0.6.4 → 0.6.5

data/vendor/faiss/faiss/impl/binary_hamming/rvv.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_RISCV_RVV
-
 #define THE_SIMD_LEVEL SIMDLevel::RISCV_RVV
 
 // NOLINTNEXTLINE(facebook-hte-InlineHeader)
@@ -22,5 +20,3 @@
 #include <faiss/impl/binary_hamming/IndexIVFSpectralHash_impl.h>
 // NOLINTNEXTLINE(facebook-hte-InlineHeader)
 #include <faiss/impl/binary_hamming/IndexPQ_impl.h>
-
-#endif // COMPILE_SIMD_RISCV_RVV

data/vendor/faiss/faiss/impl/expanded_scanners.h

@@ -67,6 +67,66 @@ size_t run_scan_codes1(
     return nup;
 }
 
+// Batched variant of run_scan_codes1 for the SQ scanners: distances four codes
+// per step via distance_to_codes_batch_4, then applies the threshold and heap
+// updates in id order so results match run_scan_codes1. No-selector path only.
+template <class ScannerType, typename C, bool store_pairs>
+size_t run_scan_codes4(
+        const ScannerType& scanner,
+        size_t list_size,
+        const uint8_t* codes,
+        const idx_t* ids,
+        ResultHandler& handler) {
+    size_t nup = 0;
+    size_t list_no = scanner.list_no;
+    size_t code_size = scanner.code_size;
+    float threshold = handler.threshold;
+
+    size_t j = 0;
+    for (; j + 4 <= list_size; j += 4) {
+        float dis[4];
+        scanner.distance_to_codes_batch_4(
+                codes,
+                codes + code_size,
+                codes + 2 * code_size,
+                codes + 3 * code_size,
+                dis[0],
+                dis[1],
+                dis[2],
+                dis[3]);
+        handler.stats.scan_cnt += 4;
+        for (size_t b = 0; b < 4; b++) {
+            if (C::cmp(threshold, dis[b])) {
+                int64_t id =
+                        store_pairs ? lo_build(list_no, j + b) : ids[j + b];
+                if (handler.add_result(dis[b], id)) {
+                    handler.stats.nheap_updates++;
+                    nup++;
+                    threshold = handler.threshold;
+                }
+            }
+        }
+        codes += 4 * code_size;
+    }
+
+    // tail: the final < 4 codes, one at a time
+    for (; j < list_size; j++) {
+        handler.stats.scan_cnt++;
+        float dis = scanner.distance_to_code(codes);
+        if (C::cmp(threshold, dis)) {
+            int64_t id = store_pairs ? lo_build(list_no, j) : ids[j];
+            if (handler.add_result(dis, id)) {
+                handler.stats.nheap_updates++;
+                nup++;
+                threshold = handler.threshold;
+            }
+        }
+        codes += code_size;
+    }
+
+    return nup;
+}
+
 /*****************************************************************************
  * The following functions dispatch runtime parameters to templates, with
  * possibly some already-fixed templates.
@@ -136,6 +196,34 @@ size_t run_scan_codes_fix_C(
     }
 }
 
+// Routing wrapper for the SQ scanners: the no-selector path takes the batched
+// run_scan_codes4, the selector path stays on run_scan_codes1.
+template <class C, class ScannerType>
+size_t run_scan_codes4_fix_C(
+        const ScannerType& scanner,
+        size_t list_size,
+        const uint8_t* codes,
+        const idx_t* ids,
+        ResultHandler& handler) {
+    if (scanner.sel) {
+        if (scanner.store_pairs) {
+            return run_scan_codes1<ScannerType, C, true, true>(
+                    scanner, list_size, codes, ids, handler);
+        } else {
+            return run_scan_codes1<ScannerType, C, false, true>(
+                    scanner, list_size, codes, ids, handler);
+        }
+    } else {
+        if (scanner.store_pairs) {
+            return run_scan_codes4<ScannerType, C, true>(
+                    scanner, list_size, codes, ids, handler);
+        } else {
+            return run_scan_codes4<ScannerType, C, false>(
+                    scanner, list_size, codes, ids, handler);
+        }
+    }
+}
+
 template <class ScannerType>
 size_t run_scan_codes(
         const ScannerType& scanner,

data/vendor/faiss/faiss/impl/fast_scan/FastScanDistancePostProcessing.h

@@ -29,6 +29,10 @@ struct FastScanDistancePostProcessing {
     /// QueryFactorsData subset for this context.
     rabitq_utils::QueryFactorsData* query_factors = nullptr;
 
+    /// Multi-bit IVF RaBitQ: rotated query per (query, probe), d floats each,
+    /// indexed like query_factors (nullptr if unused).
+    float* rotated_q = nullptr;
+
     /// The nprobe value used when allocating query_factors storage.
     /// This is needed because the allocation size (n * nprobe) may use a
     /// different nprobe than index->nprobe if search params override it.

data/vendor/faiss/faiss/impl/fast_scan/accumulate_loops.h

@@ -1,5 +1,13 @@
 /*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * This source code is licensed under the MIT license found in the
  * LICENSE file in the root directory of this source tree.
@@ -14,22 +22,14 @@
  * Contains:
  *   - accumulate_fixed_blocks / pq4_accumulate_loop_fixed_scaler
  *     (search_1 multi-BB path, bbs > 32)
- *   - accumulate_q_4step_256 / pq4_accumulate_loop_qbs_fixed_scaler_256
- *     (QBS path, bbs == 32, 256-bit kernel only)
+ *   - SIMD-level-selected QBS traversal (bbs == 32)
  *
- * The QBS helpers here use pq4_kernel_qbs_256 exclusively (not
- * decompose_qbs.h) because decompose_qbs.h includes kernels_simd512.h
- * whose 512-bit types need explicit SIMD levels.  The 512-bit QBS path
- * lives in accumulate_loops_512.h, used by the AVX512 per-ISA TU.
+ * The default PQ4QBSKernel<SL> uses the 256-bit kernel. Architecture-specific
+ * headers may specialize it while reusing the traversal and QBS dispatch.
  *
  * All functions live in `namespace faiss` (not anonymous) so they can be
  * shared by both the per-SIMD TU dispatcher (dispatching.h) and the old
  * free-function search paths (pq4_fast_scan_search_1.cpp).
- *
- * The QBS helpers here always use pq4_kernel_qbs_256 (never 512-bit).
- * This is required for the per-SIMD DD TUs where SINGLE_SIMD_LEVEL=NONE
- * leaves 512-bit types empty.  The old pq4_fast_scan_search_qbs.cpp
- * continues to use decompose_qbs.h which includes both 256 and 512 paths.
  */
 
 #include <cassert>
@@ -37,7 +37,11 @@
 #include <faiss/impl/FaissAssert.h>
 #include <faiss/impl/fast_scan/LookupTableScaler.h>
 #include <faiss/impl/fast_scan/kernels_simd256.h>
+#if FAISS_SIMD_TU(ARM_NEON)
+#include <faiss/impl/fast_scan/kernels_neon.h>
+#endif
 #include <faiss/impl/fast_scan/simd_result_handlers.h>
+#include <faiss/utils/simd_levels.h>
 
 namespace faiss {
 
@@ -112,15 +116,11 @@ void pq4_accumulate_loop_fixed_scaler(
 }
 
 /***************************************************************
- * QBS path helpers (bbs == 32, 256-bit kernel only)
+ * QBS path helpers (bbs == 32)
  ***************************************************************/
 
-template <
-        int QBS,
-        SIMDLevel KernelSL = SINGLE_SIMD_LEVEL,
-        class ResultHandler,
-        class Scaler>
-void accumulate_q_4step_256(
+template <int QBS, SIMDLevel SL, class ResultHandler, class Scaler>
+void accumulate_q_4step_for_simd(
         size_t ntotal2,
         int nsq,
         const uint8_t* codes,
@@ -135,33 +135,31 @@ void accumulate_q_4step_256(
     constexpr int SQ = Q1 + Q2 + Q3 + Q4;
 
     for_each_block<32>(ntotal2, codes, block_stride, res, [&](size_t) {
-        FixedStorageHandler<SQ, 2, KernelSL> res2;
+        // Scaler as LinkageTag: see FixedStorageHandler.
+        FixedStorageHandler<SQ, 2, SL, Scaler> res2;
         const uint8_t* LUT = LUT0;
-        pq4_kernel_qbs_256<Q1, KernelSL>(nsq, codes, LUT, res2, scaler);
+        PQ4QBSKernel<SL>::template run<Q1>(nsq, codes, LUT, res2, scaler);
         LUT += Q1 * nsq * 16;
         if (Q2 > 0) {
             res2.set_block_origin(Q1, 0);
-            pq4_kernel_qbs_256<Q2, KernelSL>(nsq, codes, LUT, res2, scaler);
+            PQ4QBSKernel<SL>::template run<Q2>(nsq, codes, LUT, res2, scaler);
             LUT += Q2 * nsq * 16;
         }
         if (Q3 > 0) {
             res2.set_block_origin(Q1 + Q2, 0);
-            pq4_kernel_qbs_256<Q3, KernelSL>(nsq, codes, LUT, res2, scaler);
+            PQ4QBSKernel<SL>::template run<Q3>(nsq, codes, LUT, res2, scaler);
             LUT += Q3 * nsq * 16;
         }
         if (Q4 > 0) {
             res2.set_block_origin(Q1 + Q2 + Q3, 0);
-            pq4_kernel_qbs_256<Q4, KernelSL>(nsq, codes, LUT, res2, scaler);
+            PQ4QBSKernel<SL>::template run<Q4>(nsq, codes, LUT, res2, scaler);
         }
         res2.to_other_handler(res);
     });
 }
 
-template <
-        SIMDLevel KernelSL = SINGLE_SIMD_LEVEL,
-        class ResultHandler,
-        class Scaler>
-void pq4_accumulate_loop_qbs_fixed_scaler_256(
+template <SIMDLevel SL = SINGLE_SIMD_LEVEL, class ResultHandler, class Scaler>
+void pq4_accumulate_loop_qbs_fixed_scaler_simd(
         int qbs,
         size_t ntotal2,
         int nsq,
@@ -175,38 +173,37 @@ void pq4_accumulate_loop_qbs_fixed_scaler_256(
     assert(is_aligned_pointer(LUT0));
 
     switch (qbs) {
-#define FAISS_QBS256_DISPATCH(QBS)                                     \
+#define FAISS_QBS_DISPATCH(QBS)                                        \
     case QBS:                                                          \
-        accumulate_q_4step_256<QBS, KernelSL>(                         \
+        accumulate_q_4step_for_simd<QBS, SL>(                          \
                 ntotal2, nsq, codes, LUT0, res, scaler, block_stride); \
         return;
-        FAISS_QBS256_DISPATCH(0x3333); // 12
-        FAISS_QBS256_DISPATCH(0x2333); // 11
-        FAISS_QBS256_DISPATCH(0x2233); // 10
-        FAISS_QBS256_DISPATCH(0x333);  // 9
-        FAISS_QBS256_DISPATCH(0x2223); // 9
-        FAISS_QBS256_DISPATCH(0x233);  // 8
-        FAISS_QBS256_DISPATCH(0x1223); // 8
-        FAISS_QBS256_DISPATCH(0x223);  // 7
-        FAISS_QBS256_DISPATCH(0x34);   // 7
-        FAISS_QBS256_DISPATCH(0x133);  // 7
-        FAISS_QBS256_DISPATCH(0x6);    // 6
-        FAISS_QBS256_DISPATCH(0x33);   // 6
-        FAISS_QBS256_DISPATCH(0x123);  // 6
-        FAISS_QBS256_DISPATCH(0x222);  // 6
-        FAISS_QBS256_DISPATCH(0x23);   // 5
-        FAISS_QBS256_DISPATCH(0x5);    // 5
-        FAISS_QBS256_DISPATCH(0x13);   // 4
-        FAISS_QBS256_DISPATCH(0x22);   // 4
-        FAISS_QBS256_DISPATCH(0x4);    // 4
-        FAISS_QBS256_DISPATCH(0x3);    // 3
-        FAISS_QBS256_DISPATCH(0x21);   // 3
-        FAISS_QBS256_DISPATCH(0x2);    // 2
-        FAISS_QBS256_DISPATCH(0x1);    // 1
-#undef FAISS_QBS256_DISPATCH
+        FAISS_QBS_DISPATCH(0x3333); // 12
+        FAISS_QBS_DISPATCH(0x2333); // 11
+        FAISS_QBS_DISPATCH(0x2233); // 10
+        FAISS_QBS_DISPATCH(0x333);  // 9
+        FAISS_QBS_DISPATCH(0x2223); // 9
+        FAISS_QBS_DISPATCH(0x233);  // 8
+        FAISS_QBS_DISPATCH(0x1223); // 8
+        FAISS_QBS_DISPATCH(0x223);  // 7
+        FAISS_QBS_DISPATCH(0x34);   // 7
+        FAISS_QBS_DISPATCH(0x133);  // 7
+        FAISS_QBS_DISPATCH(0x6);    // 6
+        FAISS_QBS_DISPATCH(0x33);   // 6
+        FAISS_QBS_DISPATCH(0x123);  // 6
+        FAISS_QBS_DISPATCH(0x222);  // 6
+        FAISS_QBS_DISPATCH(0x23);   // 5
+        FAISS_QBS_DISPATCH(0x5);    // 5
+        FAISS_QBS_DISPATCH(0x13);   // 4
+        FAISS_QBS_DISPATCH(0x22);   // 4
+        FAISS_QBS_DISPATCH(0x4);    // 4
+        FAISS_QBS_DISPATCH(0x3);    // 3
+        FAISS_QBS_DISPATCH(0x21);   // 3
+        FAISS_QBS_DISPATCH(0x2);    // 2
+        FAISS_QBS_DISPATCH(0x1);    // 1
+#undef FAISS_QBS_DISPATCH
     }
 
-    // Default: qbs not known at compile time
     for_each_block<32>(ntotal2, codes, block_stride, res, [&](size_t j0) {
         const uint8_t* LUT = LUT0;
         int qi = qbs;
@@ -215,16 +212,16 @@ void pq4_accumulate_loop_qbs_fixed_scaler_256(
             int nq = qi & 15;
             qi >>= 4;
             res.set_block_origin(i0, j0);
-#define FAISS_NQ256_DISPATCH(NQ)                                        \
-    case NQ:                                                            \
-        pq4_kernel_qbs_256<NQ, KernelSL>(nsq, codes, LUT, res, scaler); \
+#define FAISS_NQ_DISPATCH(NQ)                                             \
+    case NQ:                                                              \
+        PQ4QBSKernel<SL>::template run<NQ>(nsq, codes, LUT, res, scaler); \
         break
             switch (nq) {
-                FAISS_NQ256_DISPATCH(1);
-                FAISS_NQ256_DISPATCH(2);
-                FAISS_NQ256_DISPATCH(3);
-                FAISS_NQ256_DISPATCH(4);
-#undef FAISS_NQ256_DISPATCH
+                FAISS_NQ_DISPATCH(1);
+                FAISS_NQ_DISPATCH(2);
+                FAISS_NQ_DISPATCH(3);
+                FAISS_NQ_DISPATCH(4);
+#undef FAISS_NQ_DISPATCH
                 default:
                     FAISS_THROW_FMT("accumulate nq=%d not instantiated", nq);
             }

data/vendor/faiss/faiss/impl/fast_scan/accumulate_loops_512.h

@@ -1,5 +1,13 @@
 /*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * This source code is licensed under the MIT license found in the
  * LICENSE file in the root directory of this source tree.
@@ -23,8 +31,6 @@
  * dispatching.h's conditional include.
  */
 
-#if defined(COMPILE_SIMD_AVX512) && defined(__AVX512F__)
-
 #include <cassert>
 
 #include <faiss/impl/FaissAssert.h>
@@ -169,17 +175,10 @@ void pq4_accumulate_loop_qbs_fixed_scaler_512(
 
     // Fallback for unknown QBS values: use 256-bit path.
     // This is rare — pq4_preferred_qbs() covers all values above.
-    if constexpr (Scaler::nscale == 0) {
-        DummyScaler<SIMDLevel::AVX2> scaler_avx2;
-        pq4_accumulate_loop_qbs_fixed_scaler_256<SIMDLevel::AVX2>(
-                qbs, ntotal2, nsq, codes, LUT0, res, scaler_avx2, block_stride);
-    } else {
-        NormTableScaler<SIMDLevel::AVX2> scaler_avx2(scaler.scale_int);
-        pq4_accumulate_loop_qbs_fixed_scaler_256<SIMDLevel::AVX2>(
-                qbs, ntotal2, nsq, codes, LUT0, res, scaler_avx2, block_stride);
-    }
+    // The caller's AVX512-level scaler gives these instantiations symbol names
+    // that the AVX2 TU does not emit.
+    pq4_accumulate_loop_qbs_fixed_scaler_simd<SIMDLevel::AVX2>(
+            qbs, ntotal2, nsq, codes, LUT0, res, scaler, block_stride);
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_AVX512 && __AVX512F__

data/vendor/faiss/faiss/impl/fast_scan/decompose_qbs.h

@@ -1,5 +1,13 @@
 /*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * This source code is licensed under the MIT license found in the
  * LICENSE file in the root directory of this source tree.
@@ -12,7 +20,11 @@
 #include <faiss/impl/FaissAssert.h>
 #include <faiss/impl/fast_scan/kernels_simd256.h>
 #include <faiss/impl/fast_scan/kernels_simd512.h>
+#if FAISS_SIMD_TU(ARM_NEON)
+#include <faiss/impl/fast_scan/kernels_neon.h>
+#endif
 #include <faiss/impl/fast_scan/simd_result_handlers.h>
+#include <faiss/utils/simd_levels.h>
 
 namespace faiss {
 
@@ -20,7 +32,7 @@ using namespace simd_result_handlers;
 
 /*
  * Unified kernel: selects 256-bit vs 512-bit path based on
- * compile-time __AVX512F__ guard.
+ * compile-time COMPILE_SIMD_AVX512 && __AVX512F__ guard.
  *
  * KernelSL selects the SIMD type width used for the inner accumulation
  * loop.  In DD mode the caller passes the dispatch level so the kernel
@@ -37,66 +49,20 @@ void kernel_accumulate_block(
         const uint8_t* LUT,
         ResultHandler& res,
         const Scaler& scaler) {
-#ifdef __AVX512F__
+#if FAISS_SIMD_TU(AVX512)
     if constexpr (
             KernelSL == SIMDLevel::AVX512 ||
             KernelSL == SIMDLevel::AVX512_VPOPCNT ||
             KernelSL == SIMDLevel::AVX512_SPR) {
         pq4_kernel_qbs_512<NQ>(nsq, codes, LUT, res, scaler);
     } else {
-        pq4_kernel_qbs_256<NQ, KernelSL>(nsq, codes, LUT, res, scaler);
+        PQ4QBSKernel<KernelSL>::template run<NQ>(nsq, codes, LUT, res, scaler);
     }
 #else
-    pq4_kernel_qbs_256<NQ, KernelSL>(nsq, codes, LUT, res, scaler);
+    PQ4QBSKernel<KernelSL>::template run<NQ>(nsq, codes, LUT, res, scaler);
 #endif
 }
 
-// handle at most 4 blocks of queries
-template <
-        int QBS,
-        SIMDLevel KernelSL = SINGLE_SIMD_LEVEL,
-        class ResultHandler,
-        class Scaler>
-void accumulate_q_4step(
-        size_t ntotal2,
-        int nsq,
-        const uint8_t* codes,
-        const uint8_t* LUT0,
-        ResultHandler& res,
-        const Scaler& scaler,
-        size_t block_stride) {
-    constexpr int Q1 = QBS & 15;
-    constexpr int Q2 = (QBS >> 4) & 15;
-    constexpr int Q3 = (QBS >> 8) & 15;
-    constexpr int Q4 = (QBS >> 12) & 15;
-    constexpr int SQ = Q1 + Q2 + Q3 + Q4;
-
-    for_each_block<32>(ntotal2, codes, block_stride, res, [&](size_t) {
-        FixedStorageHandler<SQ, 2, KernelSL> res2;
-        const uint8_t* LUT = LUT0;
-        kernel_accumulate_block<Q1, KernelSL>(nsq, codes, LUT, res2, scaler);
-        LUT += Q1 * nsq * 16;
-        if (Q2 > 0) {
-            res2.set_block_origin(Q1, 0);
-            kernel_accumulate_block<Q2, KernelSL>(
-                    nsq, codes, LUT, res2, scaler);
-            LUT += Q2 * nsq * 16;
-        }
-        if (Q3 > 0) {
-            res2.set_block_origin(Q1 + Q2, 0);
-            kernel_accumulate_block<Q3, KernelSL>(
-                    nsq, codes, LUT, res2, scaler);
-            LUT += Q3 * nsq * 16;
-        }
-        if (Q4 > 0) {
-            res2.set_block_origin(Q1 + Q2 + Q3, 0);
-            kernel_accumulate_block<Q4, KernelSL>(
-                    nsq, codes, LUT, res2, scaler);
-        }
-        res2.to_other_handler(res);
-    });
-}
-
 template <
         int NQ,
         SIMDLevel KernelSL = SINGLE_SIMD_LEVEL,
@@ -149,82 +115,4 @@ void accumulate(
 #undef DISPATCH
 }
 
-template <
-        SIMDLevel KernelSL = SINGLE_SIMD_LEVEL,
-        class ResultHandler,
-        class Scaler>
-void pq4_accumulate_loop_qbs_fixed_scaler(
-        int qbs,
-        size_t ntotal2,
-        int nsq,
-        const uint8_t* codes,
-        const uint8_t* LUT0,
-        ResultHandler& res,
-        const Scaler& scaler,
-        size_t block_stride = 0) {
-    assert(nsq % 2 == 0);
-    assert(is_aligned_pointer(codes));
-    assert(is_aligned_pointer(LUT0));
-
-    // try out optimized versions
-    switch (qbs) {
-#define DISPATCH(QBS)                                                  \
-    case QBS:                                                          \
-        accumulate_q_4step<QBS, KernelSL>(                             \
-                ntotal2, nsq, codes, LUT0, res, scaler, block_stride); \
-        return;
-        DISPATCH(0x3333); // 12
-        DISPATCH(0x2333); // 11
-        DISPATCH(0x2233); // 10
-        DISPATCH(0x333);  // 9
-        DISPATCH(0x2223); // 9
-        DISPATCH(0x233);  // 8
-        DISPATCH(0x1223); // 8
-        DISPATCH(0x223);  // 7
-        DISPATCH(0x34);   // 7
-        DISPATCH(0x133);  // 7
-        DISPATCH(0x6);    // 6
-        DISPATCH(0x33);   // 6
-        DISPATCH(0x123);  // 6
-        DISPATCH(0x222);  // 6
-        DISPATCH(0x23);   // 5
-        DISPATCH(0x5);    // 5
-        DISPATCH(0x13);   // 4
-        DISPATCH(0x22);   // 4
-        DISPATCH(0x4);    // 4
-        DISPATCH(0x3);    // 3
-        DISPATCH(0x21);   // 3
-        DISPATCH(0x2);    // 2
-        DISPATCH(0x1);    // 1
-#undef DISPATCH
-    }
-
-    // default implementation where qbs is not known at compile time
-    for_each_block<32>(ntotal2, codes, block_stride, res, [&](size_t j0) {
-        const uint8_t* LUT = LUT0;
-        int qi = qbs;
-        int i0 = 0;
-        while (qi) {
-            int nq = qi & 15;
-            qi >>= 4;
-            res.set_block_origin(i0, j0);
-#define DISPATCH(NQ)                                                         \
-    case NQ:                                                                 \
-        kernel_accumulate_block<NQ, KernelSL>(nsq, codes, LUT, res, scaler); \
-        break
-            switch (nq) {
-                DISPATCH(1);
-                DISPATCH(2);
-                DISPATCH(3);
-                DISPATCH(4);
-#undef DISPATCH
-                default:
-                    FAISS_THROW_FMT("accumulate nq=%d not instantiated", nq);
-            }
-            i0 += nq;
-            LUT += nq * nsq * 16;
-        }
-    });
-}
-
 } // namespace faiss

data/vendor/faiss/faiss/impl/fast_scan/dispatching.h

@@ -1,5 +1,13 @@
 /*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * This source code is licensed under the MIT license found in the
  * LICENSE file in the root directory of this source tree.
@@ -20,8 +28,8 @@
  *   #define THE_LEVEL_TO_DISPATCH SIMDLevel::AVX2
  *   #include <faiss/impl/fast_scan/dispatching.h>
  *
- * Kernel helpers come from accumulate_loops.h (search_1 multi-BB path
- * and QBS 256-bit path) and accumulate_loops_512.h (QBS 512-bit path,
+ * Kernel helpers come from accumulate_loops.h (search_1 multi-BB path and
+ * SIMD-level-selected QBS path) and accumulate_loops_512.h (QBS 512-bit path,
  * AVX512 TU only).
  */
 
@@ -35,7 +43,7 @@
 #include <faiss/impl/fast_scan/fast_scan.h>
 #include <faiss/utils/simd_levels.h>
 
-#if defined(COMPILE_SIMD_AVX512) && defined(__AVX512F__)
+#if FAISS_SIMD_TU(AVX512)
 #include <faiss/impl/fast_scan/accumulate_loops_512.h>
 #endif
 
@@ -107,7 +115,7 @@ struct ScannerMixIn : FastScanCodeScanner {
             const uint8_t* LUT,
             int pq2x4_scale,
             size_t block_stride) override {
-#if defined(COMPILE_SIMD_AVX512) && defined(__AVX512F__)
+#if FAISS_SIMD_TU(AVX512)
         constexpr bool use_avx512_qbs =
                 (THE_LEVEL_TO_DISPATCH == SIMDLevel::AVX512 ||
                  THE_LEVEL_TO_DISPATCH == SIMDLevel::AVX512_SPR);
@@ -115,18 +123,14 @@ struct ScannerMixIn : FastScanCodeScanner {
         constexpr bool use_avx512_qbs = false;
 #endif
         if constexpr (use_avx512_qbs) {
-            // AMD Zen 4 / Zen 4c ("Bergamo", family 0x19) split 512-bit
-            // ops over a 256-bit datapath, so the 512-bit QBS kernel yields no
-            // throughput gain but pays extra per-block LUT-assembly and
-            // cross-lane reduction overhead (measured ~14% search regression
-            // for PQ8x4fs / PQ16x4fs). Route those CPUs to the 256-bit (AVX2)
-            // QBS kernel instead -- same output, no downside on Zen 4. This is
-            // a process-constant runtime branch, hoisted out of the inner
-            // accumulate loop. Intel AVX-512 keeps the 512-bit kernel.
+            // Zen 4 runs 512-bit ops on a 256-bit datapath, so the 512-bit QBS
+            // kernel is slower there; use the AVX2 kernel.
             if (SIMDConfig::avx512_split) {
+                // THE_LEVEL_TO_DISPATCH scalers give these AVX2-loop
+                // instantiations symbol names that the AVX2 TU does not emit.
                 if (pq2x4_scale) {
-                    NormTableScaler<SIMDLevel::AVX2> scaler(pq2x4_scale);
-                    pq4_accumulate_loop_qbs_fixed_scaler_256<SIMDLevel::AVX2>(
+                    NormTableScaler<THE_LEVEL_TO_DISPATCH> scaler(pq2x4_scale);
+                    pq4_accumulate_loop_qbs_fixed_scaler_simd<SIMDLevel::AVX2>(
                             qbs,
                             nb,
                             nsq,
@@ -136,8 +140,8 @@ struct ScannerMixIn : FastScanCodeScanner {
                             scaler,
                             block_stride);
                 } else {
-                    DummyScaler<SIMDLevel::AVX2> dummy;
-                    pq4_accumulate_loop_qbs_fixed_scaler_256<SIMDLevel::AVX2>(
+                    DummyScaler<THE_LEVEL_TO_DISPATCH> dummy;
+                    pq4_accumulate_loop_qbs_fixed_scaler_simd<SIMDLevel::AVX2>(
                             qbs,
                             nb,
                             nsq,
@@ -174,7 +178,8 @@ struct ScannerMixIn : FastScanCodeScanner {
         } else {
             if (pq2x4_scale) {
                 NormTableScaler<THE_LEVEL_TO_DISPATCH> scaler(pq2x4_scale);
-                pq4_accumulate_loop_qbs_fixed_scaler_256<THE_LEVEL_TO_DISPATCH>(
+                pq4_accumulate_loop_qbs_fixed_scaler_simd<
+                        THE_LEVEL_TO_DISPATCH>(
                         qbs,
                         nb,
                         nsq,
@@ -185,7 +190,8 @@ struct ScannerMixIn : FastScanCodeScanner {
                         block_stride);
             } else {
                 DummyScaler<THE_LEVEL_TO_DISPATCH> dummy;
-                pq4_accumulate_loop_qbs_fixed_scaler_256<THE_LEVEL_TO_DISPATCH>(
+                pq4_accumulate_loop_qbs_fixed_scaler_simd<
+                        THE_LEVEL_TO_DISPATCH>(
                         qbs,
                         nb,
                         nsq,

data/vendor/faiss/faiss/impl/fast_scan/fast_scan.cpp

@@ -16,6 +16,11 @@
 
 namespace faiss {
 
+void SIMDResultHandlerToFloat::end() {
+    normalizers = nullptr;
+    scan_cnt = 0;
+}
+
 using namespace simd_result_handlers;
 
 /***************************************************************