faiss 0.6.4 → 0.6.5

data/vendor/faiss/faiss/impl/fast_scan/impl-avx2.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_AVX2
-
 #define THE_LEVEL_TO_DISPATCH SIMDLevel::AVX2
 #include <faiss/impl/fast_scan/dispatching.h>        // IWYU pragma: keep
 #include <faiss/impl/fast_scan/rabitq_dispatching.h> // IWYU pragma: keep
@@ -32,5 +30,3 @@ void accumulate_to_mem_impl<SIMDLevel::AVX2>(
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_AVX2

data/vendor/faiss/faiss/impl/fast_scan/impl-avx512.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_AVX512
-
 #define THE_LEVEL_TO_DISPATCH SIMDLevel::AVX512
 #include <faiss/impl/fast_scan/dispatching.h>        // IWYU pragma: keep
 #include <faiss/impl/fast_scan/rabitq_dispatching.h> // IWYU pragma: keep
@@ -36,5 +34,3 @@ void accumulate_to_mem_impl<SIMDLevel::AVX512>(
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_AVX512

data/vendor/faiss/faiss/impl/fast_scan/impl-neon.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_ARM_NEON
-
 #define THE_LEVEL_TO_DISPATCH SIMDLevel::ARM_NEON
 #include <faiss/impl/fast_scan/dispatching.h>        // IWYU pragma: keep
 #include <faiss/impl/fast_scan/rabitq_dispatching.h> // IWYU pragma: keep
@@ -32,89 +30,3 @@ void accumulate_to_mem_impl<SIMDLevel::ARM_NEON>(
 }
 
 } // namespace faiss
-
-// ARM_SVE: forward to ARM_NEON implementation until a dedicated SVE
-// specialization is written (same pattern as scalar_quantizer/sq-neon.cpp).
-#ifdef COMPILE_SIMD_ARM_SVE
-
-namespace faiss {
-
-template <>
-std::unique_ptr<FastScanCodeScanner> make_fast_scan_scanner_impl<
-        SIMDLevel::ARM_SVE>(
-        bool is_max,
-        int impl,
-        size_t nq,
-        size_t ntotal,
-        int64_t k,
-        float* distances,
-        int64_t* ids,
-        const IDSelector* sel,
-        bool with_id_map) {
-    return make_fast_scan_scanner_impl<SIMDLevel::ARM_NEON>(
-            is_max, impl, nq, ntotal, k, distances, ids, sel, with_id_map);
-}
-
-template <>
-std::unique_ptr<FastScanCodeScanner> make_range_scanner_impl<
-        SIMDLevel::ARM_SVE>(
-        bool is_max,
-        RangeSearchResult& rres,
-        float radius,
-        size_t ntotal,
-        const IDSelector* sel) {
-    return make_range_scanner_impl<SIMDLevel::ARM_NEON>(
-            is_max, rres, radius, ntotal, sel);
-}
-
-template <>
-std::unique_ptr<FastScanCodeScanner> make_partial_range_scanner_impl<
-        SIMDLevel::ARM_SVE>(
-        bool is_max,
-        RangeSearchPartialResult& pres,
-        float radius,
-        size_t ntotal,
-        size_t q0,
-        size_t q1,
-        const IDSelector* sel) {
-    return make_partial_range_scanner_impl<SIMDLevel::ARM_NEON>(
-            is_max, pres, radius, ntotal, q0, q1, sel);
-}
-
-template <>
-std::unique_ptr<FastScanCodeScanner> rabitq_make_knn_scanner_impl<
-        SIMDLevel::ARM_SVE>(
-        const IndexRaBitQFastScan* index,
-        bool is_max,
-        size_t nq,
-        int64_t k,
-        float* distances,
-        int64_t* ids,
-        const IDSelector* sel,
-        const FastScanDistancePostProcessing& context,
-        bool is_multi_bit) {
-    return rabitq_make_knn_scanner_impl<SIMDLevel::ARM_NEON>(
-            index, is_max, nq, k, distances, ids, sel, context, is_multi_bit);
-}
-
-template <>
-std::unique_ptr<FastScanCodeScanner> rabitq_ivf_make_knn_scanner_impl<
-        SIMDLevel::ARM_SVE>(
-        bool is_max,
-        const IndexIVFRaBitQFastScan* index,
-        size_t nq,
-        size_t k,
-        float* distances,
-        int64_t* ids,
-        const IDSelector* sel,
-        const FastScanDistancePostProcessing* context,
-        bool multi_bit) {
-    return rabitq_ivf_make_knn_scanner_impl<SIMDLevel::ARM_NEON>(
-            is_max, index, nq, k, distances, ids, sel, context, multi_bit);
-}
-
-} // namespace faiss
-
-#endif // COMPILE_SIMD_ARM_SVE
-
-#endif // COMPILE_SIMD_ARM_NEON

data/vendor/faiss/faiss/impl/fast_scan/impl-riscv.cpp

@@ -8,8 +8,6 @@
 // RISC-V RVV: forward all fast_scan specializations to NONE until
 // dedicated RVV implementations are written.
 
-#ifdef COMPILE_SIMD_RISCV_RVV
-
 #include <faiss/impl/fast_scan/fast_scan.h>
 
 namespace faiss {
@@ -100,5 +98,3 @@ std::unique_ptr<FastScanCodeScanner> rabitq_ivf_make_knn_scanner_impl<
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_RISCV_RVV

data/vendor/faiss/faiss/impl/fast_scan/kernels_neon.h

@@ -0,0 +1,155 @@
+/*
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#pragma once
+
+#include <arm_neon.h>
+
+#include <faiss/impl/fast_scan/kernels_simd256.h>
+#include <faiss/impl/platform_macros.h>
+#include <faiss/impl/simdlib/simdlib_dispatch.h>
+
+namespace faiss {
+
+/*
+ * Single-BB QBS variant: accumulates NQ queries x 32 db elements (BB=1).
+ * Uses native 128-bit AdvSIMD registers instead of logical 256-bit values.
+ */
+template <int NQ, class ResultHandler, class Scaler>
+FAISS_ALWAYS_INLINE void pq4_kernel_qbs_neon(
+        int nsq,
+        const uint8_t* codes,
+        const uint8_t* LUT,
+        ResultHandler& res,
+        const Scaler& scaler) {
+    // Avoid a zero-length array for NQ=0 instantiations.
+    constexpr int NQA = NQ > 0 ? NQ : 1;
+    const uint16x8_t zero = vdupq_n_u16(0);
+    // accu[q][b] holds distances for vectors 8*b..8*b+7.
+    uint16x8_t accu[NQA][4];
+
+    for (int q = 0; q < NQ; q++) {
+        for (int b = 0; b < 4; b++) {
+            accu[q][b] = zero;
+        }
+    }
+
+    // Process two subquantizers per iteration.
+    for (int sq = 0; sq < nsq - scaler.nscale; sq += 2) {
+        const uint8x16_t code0 = vld1q_u8(codes);
+        const uint8x16_t code1 = vld1q_u8(codes + 16);
+        codes += 32;
+
+        const uint8x16_t mask = vdupq_n_u8(0x0f);
+        const uint8x16_t code0_lo = vandq_u8(code0, mask);
+        const uint8x16_t code1_lo = vandq_u8(code1, mask);
+        const uint8x16_t code0_hi = vshrq_n_u8(code0, 4);
+        const uint8x16_t code1_hi = vshrq_n_u8(code1, 4);
+
+        for (int q = 0; q < NQ; q++) {
+            // Load LUTs for two subquantizers.
+            const uint8x16_t lut0 = vld1q_u8(LUT);
+            const uint8x16_t lut1 = vld1q_u8(LUT + 16);
+            LUT += 32;
+
+            const uint8x16_t d0_lo = vqtbl1q_u8(lut0, code0_lo);
+            const uint8x16_t d0_hi = vqtbl1q_u8(lut0, code0_hi);
+            const uint8x16_t d1_lo = vqtbl1q_u8(lut1, code1_lo);
+            const uint8x16_t d1_hi = vqtbl1q_u8(lut1, code1_hi);
+
+            accu[q][0] = vaddq_u16(
+                    accu[q][0],
+                    vaddl_u8(vget_low_u8(d0_lo), vget_low_u8(d1_lo)));
+            accu[q][1] = vaddq_u16(accu[q][1], vaddl_high_u8(d0_lo, d1_lo));
+            accu[q][2] = vaddq_u16(
+                    accu[q][2],
+                    vaddl_u8(vget_low_u8(d0_hi), vget_low_u8(d1_hi)));
+            accu[q][3] = vaddq_u16(accu[q][3], vaddl_high_u8(d0_hi, d1_hi));
+        }
+    }
+
+    // Scaled tail used by additive-quantizer FastScan indexes.
+    // (this is compiled out for DummyScaler)
+    for (int sq = 0; sq < scaler.nscale; sq += 2) {
+        const uint16_t scale = scaler.scale_one(uint16_t{1});
+        const uint8x16_t code0 = vld1q_u8(codes);
+        const uint8x16_t code1 = vld1q_u8(codes + 16);
+        codes += 32;
+
+        const uint8x16_t mask = vdupq_n_u8(0x0f);
+        const uint8x16_t code0_lo = vandq_u8(code0, mask);
+        const uint8x16_t code1_lo = vandq_u8(code1, mask);
+        const uint8x16_t code0_hi = vshrq_n_u8(code0, 4);
+        const uint8x16_t code1_hi = vshrq_n_u8(code1, 4);
+
+        for (int q = 0; q < NQ; q++) {
+            // Load LUTs for two subquantizers.
+            const uint8x16_t lut0 = vld1q_u8(LUT);
+            const uint8x16_t lut1 = vld1q_u8(LUT + 16);
+            LUT += 32;
+
+            const uint8x16_t d0_lo = vqtbl1q_u8(lut0, code0_lo);
+            const uint8x16_t d0_hi = vqtbl1q_u8(lut0, code0_hi);
+            const uint8x16_t d1_lo = vqtbl1q_u8(lut1, code1_lo);
+            const uint8x16_t d1_hi = vqtbl1q_u8(lut1, code1_hi);
+
+            accu[q][0] = vaddq_u16(
+                    accu[q][0],
+                    vmulq_n_u16(
+                            vaddl_u8(vget_low_u8(d0_lo), vget_low_u8(d1_lo)),
+                            scale));
+            accu[q][1] = vaddq_u16(
+                    accu[q][1],
+                    vmulq_n_u16(vaddl_high_u8(d0_lo, d1_lo), scale));
+            accu[q][2] = vaddq_u16(
+                    accu[q][2],
+                    vmulq_n_u16(
+                            vaddl_u8(vget_low_u8(d0_hi), vget_low_u8(d1_hi)),
+                            scale));
+            accu[q][3] = vaddq_u16(
+                    accu[q][3],
+                    vmulq_n_u16(vaddl_high_u8(d0_hi, d1_hi), scale));
+        }
+    }
+
+    // Reorder the four 8-lane accumulators for the result handler.
+    using simd16uint16 = simd16uint16_tpl<SIMDLevel::ARM_NEON>;
+    for (int q = 0; q < NQ; q++) {
+        const uint16x8_t d0 = vuzp1q_u16(accu[q][0], accu[q][1]);
+        const uint16x8_t d1 = vuzp2q_u16(accu[q][0], accu[q][1]);
+        const uint16x8_t d2 = vuzp1q_u16(accu[q][2], accu[q][3]);
+        const uint16x8_t d3 = vuzp2q_u16(accu[q][2], accu[q][3]);
+        res.handle(
+                q,
+                0,
+                simd16uint16(uint16x8x2_t{d0, d1}),
+                simd16uint16(uint16x8x2_t{d2, d3}));
+    }
+}
+
+template <>
+struct PQ4QBSKernel<SIMDLevel::ARM_NEON> {
+    template <int NQ, class ResultHandler, class Scaler>
+    FAISS_ALWAYS_INLINE static void run(
+            int nsq,
+            const uint8_t* codes,
+            const uint8_t* LUT,
+            ResultHandler& res,
+            const Scaler& scaler) {
+        pq4_kernel_qbs_neon<NQ>(nsq, codes, LUT, res, scaler);
+    }
+};
+
+} // namespace faiss

data/vendor/faiss/faiss/impl/fast_scan/kernels_simd256.h

@@ -1,5 +1,13 @@
 /*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * Portions Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+/*
+ * Portions Copyright 2026 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * This source code is licensed under the MIT license found in the
  * LICENSE file in the root directory of this source tree.
@@ -210,4 +218,17 @@ void pq4_kernel_qbs_256(
     }
 }
 
+template <SIMDLevel SL>
+struct PQ4QBSKernel {
+    template <int NQ, class ResultHandler, class Scaler>
+    FAISS_ALWAYS_INLINE static void run(
+            int nsq,
+            const uint8_t* codes,
+            const uint8_t* LUT,
+            ResultHandler& res,
+            const Scaler& scaler) {
+        pq4_kernel_qbs_256<NQ, SL>(nsq, codes, LUT, res, scaler);
+    }
+};
+
 } // namespace faiss

data/vendor/faiss/faiss/impl/fast_scan/kernels_simd512.h

@@ -9,8 +9,9 @@
 
 #include <faiss/impl/platform_macros.h>
 #include <faiss/impl/simdlib/simdlib_dispatch.h>
+#include <faiss/utils/simd_levels.h>
 
-#ifdef __AVX512F__
+#if FAISS_SIMD_TU(AVX512)
 
 namespace faiss {
 
@@ -476,4 +477,4 @@ void pq4_kernel_qbs_512(
 
 } // namespace faiss
 
-#endif // __AVX512F__
+#endif // FAISS_SIMD_TU(AVX512)

data/vendor/faiss/faiss/impl/fast_scan/simd_result_handlers.h

@@ -8,6 +8,7 @@
 #pragma once
 
 #include <algorithm>
+#include <bit>
 #include <type_traits>
 #include <utility>
 #include <vector>
@@ -122,10 +123,7 @@ struct SIMDResultHandlerToFloat {
 
     // called at end of search to convert int16 distances to float, before
     // normalizers are deallocated
-    virtual void end() {
-        normalizers = nullptr;
-        scan_cnt = 0;
-    }
+    virtual void end();
 
     // Get the number of scanned vectors
     size_t count_scanned_rows() {
@@ -217,8 +215,17 @@ struct StoreResultHandler : SIMDResultHandler<SL> {
     }
 };
 
-/** stores results in fixed-size matrix. */
-template <int NQ, int BB, SIMDLevel SL = SINGLE_SIMD_LEVEL_256>
+/** stores results in fixed-size matrix.
+ *
+ * LinkageTag is unused by the handler. A tag type that only one TU uses gives
+ * the instantiation (and its out-of-line virtual handle()) a symbol name of
+ * its own, so a copy compiled with other SIMD flags cannot replace the copy
+ * of another TU. */
+template <
+        int NQ,
+        int BB,
+        SIMDLevel SL = SINGLE_SIMD_LEVEL_256,
+        class LinkageTag = void>
 struct FixedStorageHandler : SIMDResultHandler<SL> {
     using typename SIMDResultHandler<SL>::simd16uint16;
 
@@ -374,7 +381,7 @@ struct SingleResultHandler : ResultHandlerCompare<C, with_id_map, SL> {
         if (this->sel != nullptr) {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 auto real_idx = this->adjust_id(b, j);
                 lt_mask -= 1 << j;
                 if (this->sel->is_member(real_idx)) {
@@ -391,7 +398,7 @@ struct SingleResultHandler : ResultHandlerCompare<C, with_id_map, SL> {
         } else {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
                 this->scan_cnt++;
                 T d = d32tab[j];
@@ -410,7 +417,8 @@ struct SingleResultHandler : ResultHandlerCompare<C, with_id_map, SL> {
             if (!normalizers) {
                 dis[q] = idis[q];
             } else {
-                float one_a = 1 / normalizers[2 * q];
+                float a = normalizers[2 * q];
+                float one_a = a != 0 ? 1 / a : 0;
                 float b = normalizers[2 * q + 1];
                 dis[q] = b + idis[q] * one_a;
             }
@@ -497,7 +505,7 @@ struct HeapHandler : ResultHandlerCompare<C, with_id_map, SL> {
         if (this->sel != nullptr) {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 auto real_idx = this->adjust_id(b, j);
                 lt_mask -= 1 << j;
                 if (this->sel->is_member(real_idx)) {
@@ -519,7 +527,7 @@ struct HeapHandler : ResultHandlerCompare<C, with_id_map, SL> {
         } else {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
                 this->scan_cnt++;
                 T dis_for_j = d32tab[j];
@@ -549,7 +557,8 @@ struct HeapHandler : ResultHandlerCompare<C, with_id_map, SL> {
 
             float one_a = 1.0, b = 0.0;
             if (normalizers) {
-                one_a = 1 / normalizers[2 * q];
+                float a = normalizers[2 * q];
+                one_a = a != 0 ? 1 / a : 0;
                 b = normalizers[2 * q + 1];
             }
             for (int j = 0; j < k; j++) {
@@ -590,7 +599,12 @@ struct ReservoirHandler : ResultHandlerCompare<C, with_id_map, SL> {
 
     std::vector<TI> all_ids;
     AlignedTable<T> all_vals;
-    std::vector<ReservoirTopN<C>> reservoirs;
+    // Declared in this class, which takes the SIMD level, so that
+    // std::vector<Reservoir> is a different type at each level.
+    struct Reservoir : ReservoirTopN<C> {
+        using ReservoirTopN<C>::ReservoirTopN;
+    };
+    std::vector<Reservoir> reservoirs;
 
     ReservoirHandler(
             size_t nq,
@@ -635,7 +649,7 @@ struct ReservoirHandler : ResultHandlerCompare<C, with_id_map, SL> {
         if (this->sel != nullptr) {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 auto real_idx = this->adjust_id(b, j);
                 lt_mask -= 1 << j;
                 if (this->sel->is_member(real_idx)) {
@@ -649,7 +663,7 @@ struct ReservoirHandler : ResultHandlerCompare<C, with_id_map, SL> {
         } else {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
                 T dis_for_j = d32tab[j];
                 this->scan_cnt++;
@@ -679,7 +693,8 @@ struct ReservoirHandler : ResultHandlerCompare<C, with_id_map, SL> {
 
             float one_a = 1.0, b = 0.0;
             if (normalizers) {
-                one_a = 1 / normalizers[2 * q];
+                float a = normalizers[2 * q];
+                one_a = a != 0 ? 1 / a : 0;
                 b = normalizers[2 * q + 1];
             }
             for (size_t i = 0; i < res.i; i++) {
@@ -768,7 +783,7 @@ struct RangeHandler : ResultHandlerCompare<C, with_id_map, SL> {
         if (this->sel != nullptr) {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
 
                 auto real_idx = this->adjust_id(b, j);
@@ -783,7 +798,7 @@ struct RangeHandler : ResultHandlerCompare<C, with_id_map, SL> {
         } else {
             while (lt_mask) {
                 // find first non-zero
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
                 T dis = d32tab[j];
                 n_per_query[q]++;
@@ -807,7 +822,8 @@ struct RangeHandler : ResultHandlerCompare<C, with_id_map, SL> {
         rres.lims[0] = 0;
 
         for (int q = 0; q < nq; q++) {
-            float one_a = 1 / normalizers[2 * q];
+            float a = normalizers[2 * q];
+            float one_a = a != 0 ? 1 / a : 0;
             float b = normalizers[2 * q + 1];
             for (size_t i = rres.lims[q]; i < rres.lims[q + 1]; i++) {
                 rres.distances[i] = rres.distances[i] * one_a + b;
@@ -873,7 +889,8 @@ struct PartialRangeHandler : RangeHandler<C, with_id_map, SL> {
         size_t* lims = n_per_query.data();
 
         for (int q = 0; q < nq; q++) {
-            float one_a = 1 / normalizers[2 * q];
+            float a = normalizers[2 * q];
+            float one_a = a != 0 ? 1 / a : 0;
             float b = normalizers[2 * q + 1];
             RangeQueryResult& qres = pres.new_result(q + q0);
             for (size_t i = lims[q]; i < lims[q + 1]; i++) {
@@ -939,7 +956,7 @@ struct SingleQueryResultCollectHandler
 
         if (this->sel != nullptr) {
             while (lt_mask) {
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 auto real_idx = this->adjust_id(b, j);
                 lt_mask -= 1 << j;
                 if (this->sel->is_member(real_idx)) {
@@ -950,7 +967,7 @@ struct SingleQueryResultCollectHandler
             }
         } else {
             while (lt_mask) {
-                int j = __builtin_ctz(lt_mask);
+                int j = std::countr_zero(lt_mask);
                 lt_mask -= 1 << j;
                 T dis = d32tab[j];
                 int64_t idx = this->adjust_id(b, j);
@@ -962,7 +979,8 @@ struct SingleQueryResultCollectHandler
 
     void end() override {
         if (normalizers) {
-            float one_a = 1 / normalizers[0];
+            float a = normalizers[0];
+            float one_a = a != 0 ? 1 / a : 0;
             float b = normalizers[1];
             for (size_t i = 0; i < collect.size(); i++) {
                 collect[i].second = collect[i].second * one_a + b;

data/vendor/faiss/faiss/impl/hnsw/avx2.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_AVX2
-
 #include <faiss/impl/hnsw/MinimaxHeap.h>
 
 #include <immintrin.h>
@@ -146,5 +144,3 @@ int pop_min_tpl<CMin<float, int32_t>, SIMDLevel::AVX2>(
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_AVX2

data/vendor/faiss/faiss/impl/hnsw/avx512.cpp

@@ -5,8 +5,6 @@
  * LICENSE file in the root directory of this source tree.
  */
 
-#ifdef COMPILE_SIMD_AVX512
-
 #include <faiss/impl/hnsw/MinimaxHeap.h>
 
 #include <immintrin.h>
@@ -138,5 +136,3 @@ int pop_min_tpl<CMin<float, int32_t>, SIMDLevel::AVX512>(
 }
 
 } // namespace faiss
-
-#endif // COMPILE_SIMD_AVX512