carray 3.0.0 → 3.0.2

data/ext/carray_kernels_reduce_extreme.c

@@ -34,6 +34,7 @@ static inline VALUE BOOL2VAL (boolean8_t x) { return x ? Qtrue : Qfalse; }
 #endif
 
 #include "ca_op_powi.h"
+#include "ca_op_cmplx64.h"
 
 /* ===== min_ki ============================================ */
 
@@ -136,6 +137,7 @@ min_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -215,6 +217,7 @@ min_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -340,6 +343,7 @@ min_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -370,8 +374,8 @@ min_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -500,6 +504,7 @@ min_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -655,6 +660,7 @@ min_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -734,6 +740,7 @@ min_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -859,6 +866,7 @@ min_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -889,8 +897,8 @@ min_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1019,6 +1027,7 @@ min_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -1174,6 +1183,7 @@ min_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -1253,6 +1263,7 @@ min_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -1378,6 +1389,7 @@ min_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -1408,8 +1420,8 @@ min_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1538,6 +1550,7 @@ min_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -1693,6 +1706,7 @@ min_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -1772,6 +1786,7 @@ min_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -1897,6 +1912,7 @@ min_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -1927,8 +1943,8 @@ min_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2057,6 +2073,7 @@ min_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -2212,6 +2229,7 @@ min_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -2291,6 +2309,7 @@ min_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -2416,6 +2435,7 @@ min_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -2446,8 +2466,8 @@ min_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2576,6 +2596,7 @@ min_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -2731,6 +2752,7 @@ min_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -2810,6 +2832,7 @@ min_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -2935,6 +2958,7 @@ min_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -2965,8 +2989,8 @@ min_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3095,6 +3119,7 @@ min_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -3250,6 +3275,7 @@ min_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3329,6 +3355,7 @@ min_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3454,6 +3481,7 @@ min_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3484,8 +3512,8 @@ min_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3614,6 +3642,7 @@ min_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3769,6 +3798,7 @@ min_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -3848,6 +3878,7 @@ min_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -3973,6 +4004,7 @@ min_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -4003,8 +4035,8 @@ min_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4133,6 +4165,7 @@ min_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -4216,6 +4249,7 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
       ca_size_t __outer_off = 0;
       float acc;
       acc = (INFINITY);
+      int64_t __anf_seen = 0;
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
@@ -4230,11 +4264,13 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
         for ( __i = 0; __i < __n; __i++ ) {
           float v = __chunk[__i];
           acc = (v < acc) ? v : acc;
+          __anf_seen |= (v == v);
         }
         __outer_off += __r;
       }
       ca_lazy_arena_release(__chunk);
       ca_lazy_arena_exit();
+      if ( ! __anf_seen && ca->elements > 0 ) acc = (float) NAN;
       return rb_float_new((float) (acc));
     }
     /* L.1 / L.7: loop-interchange fast path with inner-tiling
@@ -4288,6 +4324,25 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -4367,6 +4422,25 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -4492,6 +4566,25 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -4522,8 +4615,8 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4652,6 +4745,25 @@ min_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_M_stride + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -4689,6 +4801,16 @@ ca_size_t   out_i = 0;
 #define __min_f32_EXPR(__x) ((float)(__x))
       CA_SLAB_REDUCE_MIN8_EX(float, float, st, p, m, acc, INFINITY, __min_f32_EXPR, masked_cnt);
 #undef __min_f32_EXPR
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (acc == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          acc = (float) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
@@ -4735,6 +4857,7 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
       ca_size_t __outer_off = 0;
       double acc;
       acc = (INFINITY);
+      int64_t __anf_seen = 0;
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
@@ -4749,11 +4872,13 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
         for ( __i = 0; __i < __n; __i++ ) {
           double v = __chunk[__i];
           acc = (v < acc) ? v : acc;
+          __anf_seen |= (v == v);
         }
         __outer_off += __r;
       }
       ca_lazy_arena_release(__chunk);
       ca_lazy_arena_exit();
+      if ( ! __anf_seen && ca->elements > 0 ) acc = (double) NAN;
       return rb_float_new((double) (acc));
     }
     /* L.1 / L.7: loop-interchange fast path with inner-tiling
@@ -4807,6 +4932,25 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -4886,6 +5030,25 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -5011,6 +5174,25 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -5041,8 +5223,8 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5171,6 +5353,25 @@ min_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_M_stride + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -5208,6 +5409,16 @@ ca_size_t   out_i = 0;
 #define __min_f64_EXPR(__x) ((double)(__x))
       CA_SLAB_REDUCE_MIN8_EX(double, double, st, p, m, acc, INFINITY, __min_f64_EXPR, masked_cnt);
 #undef __min_f64_EXPR
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (acc == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          acc = (double) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
@@ -5326,6 +5537,7 @@ min_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -5405,6 +5617,7 @@ min_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -5530,6 +5743,7 @@ min_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -5560,8 +5774,8 @@ min_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5690,6 +5904,7 @@ min_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -5776,7 +5991,7 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -5845,6 +6060,7 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -5924,6 +6140,7 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -6049,6 +6266,7 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -6079,8 +6297,8 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6209,6 +6427,7 @@ min_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -6572,6 +6791,7 @@ max_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -6651,6 +6871,7 @@ max_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -6776,6 +6997,7 @@ max_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -6806,8 +7028,8 @@ max_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6936,6 +7158,7 @@ max_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -7091,6 +7314,7 @@ max_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -7170,6 +7394,7 @@ max_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -7295,6 +7520,7 @@ max_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -7325,8 +7551,8 @@ max_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7455,6 +7681,7 @@ max_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -7610,6 +7837,7 @@ max_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -7689,6 +7917,7 @@ max_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -7814,6 +8043,7 @@ max_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -7844,8 +8074,8 @@ max_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7974,6 +8204,7 @@ max_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -8129,6 +8360,7 @@ max_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -8208,6 +8440,7 @@ max_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -8333,6 +8566,7 @@ max_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -8363,8 +8597,8 @@ max_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -8493,6 +8727,7 @@ max_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -8648,6 +8883,7 @@ max_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -8727,6 +8963,7 @@ max_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -8852,6 +9089,7 @@ max_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -8882,8 +9120,8 @@ max_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9012,6 +9250,7 @@ max_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -9167,6 +9406,7 @@ max_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -9246,6 +9486,7 @@ max_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -9371,6 +9612,7 @@ max_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -9401,8 +9643,8 @@ max_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9531,6 +9773,7 @@ max_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -9686,6 +9929,7 @@ max_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -9765,6 +10009,7 @@ max_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -9890,6 +10135,7 @@ max_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -9920,8 +10166,8 @@ max_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10050,6 +10296,7 @@ max_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -10205,6 +10452,7 @@ max_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -10284,6 +10532,7 @@ max_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -10409,6 +10658,7 @@ max_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -10439,8 +10689,8 @@ max_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10569,6 +10819,7 @@ max_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -10652,6 +10903,7 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
       ca_size_t __outer_off = 0;
       float acc;
       acc = (-INFINITY);
+      int64_t __anf_seen = 0;
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
@@ -10666,11 +10918,13 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
         for ( __i = 0; __i < __n; __i++ ) {
           float v = __chunk[__i];
           acc = (v > acc) ? v : acc;
+          __anf_seen |= (v == v);
         }
         __outer_off += __r;
       }
       ca_lazy_arena_release(__chunk);
       ca_lazy_arena_exit();
+      if ( ! __anf_seen && ca->elements > 0 ) acc = (float) NAN;
       return rb_float_new((float) (acc));
     }
     /* L.1 / L.7: loop-interchange fast path with inner-tiling
@@ -10724,6 +10978,25 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -10803,6 +11076,25 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -10928,6 +11220,25 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -10958,8 +11269,8 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -11088,6 +11399,25 @@ max_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (float) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const float *__li_row = __li_plane + __li_i * __li_M_stride + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (float) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -11125,6 +11455,16 @@ ca_size_t   out_i = 0;
 #define __max_f32_EXPR(__x) ((float)(__x))
       CA_SLAB_REDUCE_MAX8_EX(float, float, st, p, m, acc, -INFINITY, __max_f32_EXPR, masked_cnt);
 #undef __max_f32_EXPR
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (acc == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          acc = (float) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
@@ -11171,6 +11511,7 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
       ca_size_t __outer_off = 0;
       double acc;
       acc = (-INFINITY);
+      int64_t __anf_seen = 0;
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
@@ -11185,11 +11526,13 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
         for ( __i = 0; __i < __n; __i++ ) {
           double v = __chunk[__i];
           acc = (v > acc) ? v : acc;
+          __anf_seen |= (v == v);
         }
         __outer_off += __r;
       }
       ca_lazy_arena_release(__chunk);
       ca_lazy_arena_exit();
+      if ( ! __anf_seen && ca->elements > 0 ) acc = (double) NAN;
       return rb_float_new((double) (acc));
     }
     /* L.1 / L.7: loop-interchange fast path with inner-tiling
@@ -11243,6 +11586,25 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11322,6 +11684,25 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+{
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11447,6 +11828,25 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_INNER + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11477,8 +11877,8 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -11607,6 +12007,25 @@ max_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    {
+  int __li_susp = 0;
+  for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+    if ( __li_buf_acc[__j] == (double) (-INFINITY) ) { __li_susp = 1; break; }
+  }
+  if ( __li_susp ) {
+    int8_t __li_buf_seen[512];
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) __li_buf_seen[__j] = 0;
+    for ( ca_size_t __li_i = 0; __li_i < __li_M; __li_i++ ) {
+      const double *__li_row = __li_plane + __li_i * __li_M_stride + __li_tile;
+      for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+        __li_buf_seen[__j] |= (__li_row[__j] == __li_row[__j]);
+      }
+    }
+    for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
+      if ( ! __li_buf_seen[__j] ) __li_buf_acc[__j] = (double) NAN;
+    }
+  }
+}
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11644,6 +12063,16 @@ ca_size_t   out_i = 0;
 #define __max_f64_EXPR(__x) ((double)(__x))
       CA_SLAB_REDUCE_MAX8_EX(double, double, st, p, m, acc, -INFINITY, __max_f64_EXPR, masked_cnt);
 #undef __max_f64_EXPR
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (acc == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          acc = (double) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
@@ -11762,6 +12191,7 @@ max_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -11841,6 +12271,7 @@ max_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -11966,6 +12397,7 @@ max_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -11996,8 +12428,8 @@ max_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12126,6 +12558,7 @@ max_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -12212,7 +12645,7 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -12281,6 +12714,7 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -12360,6 +12794,7 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -12485,6 +12920,7 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -12515,8 +12951,8 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12645,6 +13081,7 @@ max_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -13376,6 +13813,17 @@ minmax_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
       float hi = -INFINITY;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(float, st, p, m, lo, INFINITY, if (v < lo) lo = v; if (v > hi) hi = v;, masked_cnt);
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (lo == (INFINITY) && hi == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          lo = (float) NAN;
+          hi = (float) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask_a ) {
           ca_create_mask(co_a);
@@ -13431,6 +13879,17 @@ minmax_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
       double hi = -INFINITY;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(double, st, p, m, lo, INFINITY, if (v < lo) lo = v; if (v > hi) hi = v;, masked_cnt);
+      /* all-NaN fix-up (all_nan_result: :nan). */
+      if ( (lo == (INFINITY) && hi == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          lo = (double) NAN;
+          hi = (double) NAN;
+        }
+      }
       if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
         if ( ! op_mask_a ) {
           ca_create_mask(co_a);
@@ -14020,7 +14479,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(float, st, p, m, best_v, INFINITY, if (v < best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -14062,7 +14532,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(double, st, p, m, best_v, INFINITY, if (v < best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -14707,7 +15188,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(float, st, p, m, best_v, -INFINITY, if (v > best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -14749,7 +15241,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(double, st, p, m, best_v, -INFINITY, if (v > best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -15640,7 +16143,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(float, st, p, m, best_v, INFINITY, if (v < best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -15710,7 +16224,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(double, st, p, m, best_v, INFINITY, if (v < best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -16587,7 +17112,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(float, st, p, m, best_v, -INFINITY, if (v > best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(float, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;
@@ -16657,7 +17193,18 @@ ca_size_t   out_i = 0;
       int64_t best_i = 0;
       ca_size_t masked_cnt = 0;
       CA_SLAB_REDUCE_T_EX(double, st, p, m, best_v, -INFINITY, if (v > best_v) { best_v = v; best_i = idx; }, masked_cnt);
-      if ( (min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count) ) {
+      int __anf_all_nan = 0;
+      /* all-NaN fix-up (all_nan_result: :undef). */
+      if ( (best_v == (-INFINITY)) && masked_cnt < st.slab_elements ) {
+        int64_t   __anf_seen = 0;
+        ca_size_t __anf_mc   = 0;
+        CA_SLAB_REDUCE_T_EX(double, st, p, m, __anf_seen, 0, __anf_seen |= (v == v), __anf_mc);
+        (void) __anf_mc;
+        if ( ! __anf_seen ) {
+          __anf_all_nan = 1;
+        }
+      }
+      if ( ((min_count < 0 ? masked_cnt == st.slab_elements : st.slab_elements - masked_cnt < min_count)) || __anf_all_nan ) {
         if ( ! op_mask ) {
           ca_create_mask(co);
           op_mask = (boolean8_t *) co->mask->ptr;