carray 3.0.0 → 3.0.2

data/ext/carray_kernels_reduce_aggregate.c

@@ -34,6 +34,7 @@ static inline VALUE BOOL2VAL (boolean8_t x) { return x ? Qtrue : Qfalse; }
 #endif
 
 #include "ca_op_powi.h"
+#include "ca_op_cmplx64.h"
 
 /* ===== sum_ki ============================================ */
 
@@ -136,6 +137,7 @@ sum_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -215,6 +217,7 @@ sum_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -340,6 +343,7 @@ sum_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -370,8 +374,8 @@ sum_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -500,6 +504,7 @@ sum_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -655,6 +660,7 @@ sum_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -734,6 +740,7 @@ sum_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -859,6 +866,7 @@ sum_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -889,8 +897,8 @@ sum_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1019,6 +1027,7 @@ sum_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int k
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -1174,6 +1183,7 @@ sum_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -1253,6 +1263,7 @@ sum_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -1378,6 +1389,7 @@ sum_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -1408,8 +1420,8 @@ sum_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1538,6 +1550,7 @@ sum_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -1693,6 +1706,7 @@ sum_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -1772,6 +1786,7 @@ sum_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -1897,6 +1912,7 @@ sum_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -1927,8 +1943,8 @@ sum_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2057,6 +2073,7 @@ sum_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -2212,6 +2229,7 @@ sum_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -2291,6 +2309,7 @@ sum_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -2416,6 +2435,7 @@ sum_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -2446,8 +2466,8 @@ sum_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2576,6 +2596,7 @@ sum_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -2731,6 +2752,7 @@ sum_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -2810,6 +2832,7 @@ sum_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -2935,6 +2958,7 @@ sum_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -2965,8 +2989,8 @@ sum_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3095,6 +3119,7 @@ sum_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -3250,6 +3275,7 @@ sum_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -3329,6 +3355,7 @@ sum_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -3454,6 +3481,7 @@ sum_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -3484,8 +3512,8 @@ sum_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3614,6 +3642,7 @@ sum_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -3769,6 +3798,7 @@ sum_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -3848,6 +3878,7 @@ sum_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -3973,6 +4004,7 @@ sum_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -4003,8 +4035,8 @@ sum_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4133,6 +4165,7 @@ sum_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -4288,6 +4321,7 @@ sum_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -4367,6 +4401,7 @@ sum_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -4492,6 +4527,7 @@ sum_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -4522,8 +4558,8 @@ sum_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4652,6 +4688,7 @@ sum_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -4807,6 +4844,7 @@ sum_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -4886,6 +4924,7 @@ sum_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -5011,6 +5050,7 @@ sum_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -5041,8 +5081,8 @@ sum_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5171,6 +5211,7 @@ sum_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -5326,6 +5367,7 @@ sum_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -5405,6 +5447,7 @@ sum_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -5530,6 +5573,7 @@ sum_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -5560,8 +5604,8 @@ sum_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5690,6 +5734,7 @@ sum_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -5845,6 +5890,7 @@ sum_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -5924,6 +5970,7 @@ sum_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -6049,6 +6096,7 @@ sum_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -6079,8 +6127,8 @@ sum_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6209,6 +6257,7 @@ sum_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -6364,6 +6413,7 @@ sum_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -6443,6 +6493,7 @@ sum_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -6568,6 +6619,7 @@ sum_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -6598,8 +6650,8 @@ sum_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6728,6 +6780,7 @@ sum_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -6814,7 +6867,7 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -6883,6 +6936,7 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -6962,6 +7016,7 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -7087,6 +7142,7 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -7117,8 +7173,8 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7247,6 +7303,7 @@ sum_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, i
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -7500,6 +7557,7 @@ prod_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -7579,6 +7637,7 @@ prod_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -7704,6 +7763,7 @@ prod_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -7734,8 +7794,8 @@ prod_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7864,6 +7924,7 @@ prod_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -8019,6 +8080,7 @@ prod_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -8098,6 +8160,7 @@ prod_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -8223,6 +8286,7 @@ prod_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -8253,8 +8317,8 @@ prod_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -8383,6 +8447,7 @@ prod_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -8538,6 +8603,7 @@ prod_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -8617,6 +8683,7 @@ prod_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -8742,6 +8809,7 @@ prod_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -8772,8 +8840,8 @@ prod_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -8902,6 +8970,7 @@ prod_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -9057,6 +9126,7 @@ prod_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -9136,6 +9206,7 @@ prod_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -9261,6 +9332,7 @@ prod_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -9291,8 +9363,8 @@ prod_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9421,6 +9493,7 @@ prod_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -9576,6 +9649,7 @@ prod_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -9655,6 +9729,7 @@ prod_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -9780,6 +9855,7 @@ prod_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -9810,8 +9886,8 @@ prod_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9940,6 +10016,7 @@ prod_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10095,6 +10172,7 @@ prod_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -10174,6 +10252,7 @@ prod_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -10299,6 +10378,7 @@ prod_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10329,8 +10409,8 @@ prod_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10459,6 +10539,7 @@ prod_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10614,6 +10695,7 @@ prod_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -10693,6 +10775,7 @@ prod_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -10818,6 +10901,7 @@ prod_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10848,8 +10932,8 @@ prod_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10978,6 +11062,7 @@ prod_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11133,6 +11218,7 @@ prod_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11212,6 +11298,7 @@ prod_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11337,6 +11424,7 @@ prod_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11367,8 +11455,8 @@ prod_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -11497,6 +11585,7 @@ prod_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11652,6 +11741,7 @@ prod_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11731,6 +11821,7 @@ prod_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -11856,6 +11947,7 @@ prod_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -11886,8 +11978,8 @@ prod_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12016,6 +12108,7 @@ prod_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -12171,6 +12264,7 @@ prod_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -12250,6 +12344,7 @@ prod_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -12375,6 +12470,7 @@ prod_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -12405,8 +12501,8 @@ prod_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12535,6 +12631,7 @@ prod_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -12690,6 +12787,7 @@ prod_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -12769,6 +12867,7 @@ prod_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -12894,6 +12993,7 @@ prod_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -12924,8 +13024,8 @@ prod_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -13054,6 +13154,7 @@ prod_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -13209,6 +13310,7 @@ prod_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -13288,6 +13390,7 @@ prod_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -13413,6 +13516,7 @@ prod_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -13443,8 +13547,8 @@ prod_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -13573,6 +13677,7 @@ prod_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -13728,6 +13833,7 @@ prod_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -13807,6 +13913,7 @@ prod_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -13932,6 +14039,7 @@ prod_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -13962,8 +14070,8 @@ prod_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -14092,6 +14200,7 @@ prod_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -14178,7 +14287,7 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -14247,6 +14356,7 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -14326,6 +14436,7 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -14451,6 +14562,7 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -14481,8 +14593,8 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -14611,6 +14723,7 @@ prod_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -14865,6 +14978,7 @@ mean_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -14944,6 +15058,7 @@ mean_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -15069,6 +15184,7 @@ mean_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -15099,8 +15215,8 @@ mean_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -15229,6 +15345,7 @@ mean_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -15387,6 +15504,7 @@ mean_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -15466,6 +15584,7 @@ mean_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -15591,6 +15710,7 @@ mean_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -15621,8 +15741,8 @@ mean_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -15751,6 +15871,7 @@ mean_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -15909,6 +16030,7 @@ mean_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -15988,6 +16110,7 @@ mean_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -16113,6 +16236,7 @@ mean_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -16143,8 +16267,8 @@ mean_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -16273,6 +16397,7 @@ mean_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -16431,6 +16556,7 @@ mean_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -16510,6 +16636,7 @@ mean_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -16635,6 +16762,7 @@ mean_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -16665,8 +16793,8 @@ mean_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -16795,6 +16923,7 @@ mean_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -16953,6 +17082,7 @@ mean_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -17032,6 +17162,7 @@ mean_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -17157,6 +17288,7 @@ mean_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -17187,8 +17319,8 @@ mean_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -17317,6 +17449,7 @@ mean_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -17475,6 +17608,7 @@ mean_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -17554,6 +17688,7 @@ mean_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -17679,6 +17814,7 @@ mean_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -17709,8 +17845,8 @@ mean_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -17839,6 +17975,7 @@ mean_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -17997,6 +18134,7 @@ mean_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -18076,6 +18214,7 @@ mean_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -18201,6 +18340,7 @@ mean_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -18231,8 +18371,8 @@ mean_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -18361,6 +18501,7 @@ mean_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -18519,6 +18660,7 @@ mean_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -18598,6 +18740,7 @@ mean_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -18723,6 +18866,7 @@ mean_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -18753,8 +18897,8 @@ mean_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -18883,6 +19027,7 @@ mean_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -19041,6 +19186,7 @@ mean_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -19120,6 +19266,7 @@ mean_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -19245,6 +19392,7 @@ mean_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -19275,8 +19423,8 @@ mean_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -19405,6 +19553,7 @@ mean_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -19563,6 +19712,7 @@ mean_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -19642,6 +19792,7 @@ mean_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -19767,6 +19918,7 @@ mean_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -19797,8 +19949,8 @@ mean_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -19927,6 +20079,7 @@ mean_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -20085,6 +20238,7 @@ mean_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
             }
@@ -20164,6 +20318,7 @@ mean_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
             }
@@ -20289,6 +20444,7 @@ mean_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
               }
@@ -20319,8 +20475,8 @@ mean_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -20449,6 +20605,7 @@ mean_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
               }
@@ -20607,6 +20764,7 @@ mean_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
             }
@@ -20686,6 +20844,7 @@ mean_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
             }
@@ -20811,6 +20970,7 @@ mean_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
               }
@@ -20841,8 +21001,8 @@ mean_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -20971,6 +21131,7 @@ mean_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (((int64_t)__li_M) ? __li_buf_acc[__j] / (cmplx128_t) ((int64_t)__li_M) : 0);
               }
@@ -21129,6 +21290,7 @@ mean_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -21208,6 +21370,7 @@ mean_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
             }
@@ -21333,6 +21496,7 @@ mean_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -21363,8 +21527,8 @@ mean_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -21493,6 +21657,7 @@ mean_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (((int64_t)__li_M) ? __li_buf_acc[__j] / (double) ((int64_t)__li_M) : 0);
               }
@@ -21582,7 +21747,7 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -21651,6 +21816,7 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (((int64_t)__li_M) ? rb_funcall(__li_buf_acc[__j], rb_intern("/"), 1, LONG2NUM(((int64_t)__li_M))) : Qnil);
             }
@@ -21730,6 +21896,7 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (((int64_t)__li_M) ? rb_funcall(__li_buf_acc[__j], rb_intern("/"), 1, LONG2NUM(((int64_t)__li_M))) : Qnil);
             }
@@ -21855,6 +22022,7 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (((int64_t)__li_M) ? rb_funcall(__li_buf_acc[__j], rb_intern("/"), 1, LONG2NUM(((int64_t)__li_M))) : Qnil);
               }
@@ -21885,8 +22053,8 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -22015,6 +22183,7 @@ mean_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes,
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (((int64_t)__li_M) ? rb_funcall(__li_buf_acc[__j], rb_intern("/"), 1, LONG2NUM(((int64_t)__li_M))) : Qnil);
               }