carray 3.0.0 → 3.0.2

data/ext/carray_kernels_reduce_cumulative.c

@@ -34,6 +34,7 @@ static inline VALUE BOOL2VAL (boolean8_t x) { return x ? Qtrue : Qfalse; }
 #endif
 
 #include "ca_op_powi.h"
+#include "ca_op_cmplx64.h"
 
 /* ===== count_ki ============================================ */
 
@@ -134,6 +135,7 @@ count_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -213,6 +215,7 @@ count_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -338,6 +341,7 @@ count_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -368,8 +372,8 @@ count_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -498,6 +502,7 @@ count_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -639,6 +644,7 @@ count_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -718,6 +724,7 @@ count_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -843,6 +850,7 @@ count_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -873,8 +881,8 @@ count_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1003,6 +1011,7 @@ count_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -1144,6 +1153,7 @@ count_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -1223,6 +1233,7 @@ count_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -1348,6 +1359,7 @@ count_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -1378,8 +1390,8 @@ count_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -1508,6 +1520,7 @@ count_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -1649,6 +1662,7 @@ count_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -1728,6 +1742,7 @@ count_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -1853,6 +1868,7 @@ count_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -1883,8 +1899,8 @@ count_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2013,6 +2029,7 @@ count_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -2154,6 +2171,7 @@ count_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -2233,6 +2251,7 @@ count_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -2358,6 +2377,7 @@ count_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -2388,8 +2408,8 @@ count_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -2518,6 +2538,7 @@ count_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -2659,6 +2680,7 @@ count_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -2738,6 +2760,7 @@ count_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -2863,6 +2886,7 @@ count_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -2893,8 +2917,8 @@ count_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3023,6 +3047,7 @@ count_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3164,6 +3189,7 @@ count_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3243,6 +3269,7 @@ count_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3368,6 +3395,7 @@ count_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3398,8 +3426,8 @@ count_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -3528,6 +3556,7 @@ count_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3669,6 +3698,7 @@ count_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3748,6 +3778,7 @@ count_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -3873,6 +3904,7 @@ count_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -3903,8 +3935,8 @@ count_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4033,6 +4065,7 @@ count_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -4174,6 +4207,7 @@ count_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -4253,6 +4287,7 @@ count_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -4378,6 +4413,7 @@ count_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -4408,8 +4444,8 @@ count_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -4538,6 +4574,7 @@ count_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -4679,6 +4716,7 @@ count_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -4758,6 +4796,7 @@ count_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -4883,6 +4922,7 @@ count_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -4913,8 +4953,8 @@ count_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5043,6 +5083,7 @@ count_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, in
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -5232,6 +5273,7 @@ accumulate_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -5311,6 +5353,7 @@ accumulate_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
             }
@@ -5436,6 +5479,7 @@ accumulate_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -5466,8 +5510,8 @@ accumulate_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -5596,6 +5640,7 @@ accumulate_ki_native_i8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int8_t) (__li_buf_acc[__j]);
               }
@@ -5751,6 +5796,7 @@ accumulate_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -5830,6 +5876,7 @@ accumulate_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
             }
@@ -5955,6 +6002,7 @@ accumulate_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -5985,8 +6033,8 @@ accumulate_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6115,6 +6163,7 @@ accumulate_ki_native_u8 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint8_t) (__li_buf_acc[__j]);
               }
@@ -6270,6 +6319,7 @@ accumulate_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -6349,6 +6399,7 @@ accumulate_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
             }
@@ -6474,6 +6525,7 @@ accumulate_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -6504,8 +6556,8 @@ accumulate_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -6634,6 +6686,7 @@ accumulate_ki_native_i16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int16_t) (__li_buf_acc[__j]);
               }
@@ -6789,6 +6842,7 @@ accumulate_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -6868,6 +6922,7 @@ accumulate_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
             }
@@ -6993,6 +7048,7 @@ accumulate_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -7023,8 +7079,8 @@ accumulate_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7153,6 +7209,7 @@ accumulate_ki_native_u16 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint16_t) (__li_buf_acc[__j]);
               }
@@ -7308,6 +7365,7 @@ accumulate_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -7387,6 +7445,7 @@ accumulate_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
             }
@@ -7512,6 +7571,7 @@ accumulate_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -7542,8 +7602,8 @@ accumulate_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -7672,6 +7732,7 @@ accumulate_ki_native_i32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int32_t) (__li_buf_acc[__j]);
               }
@@ -7827,6 +7888,7 @@ accumulate_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -7906,6 +7968,7 @@ accumulate_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
             }
@@ -8031,6 +8094,7 @@ accumulate_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -8061,8 +8125,8 @@ accumulate_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -8191,6 +8255,7 @@ accumulate_ki_native_u32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint32_t) (__li_buf_acc[__j]);
               }
@@ -8346,6 +8411,7 @@ accumulate_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -8425,6 +8491,7 @@ accumulate_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -8550,6 +8617,7 @@ accumulate_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -8580,8 +8648,8 @@ accumulate_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -8710,6 +8778,7 @@ accumulate_ki_native_i64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -8865,6 +8934,7 @@ accumulate_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -8944,6 +9014,7 @@ accumulate_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
             }
@@ -9069,6 +9140,7 @@ accumulate_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -9099,8 +9171,8 @@ accumulate_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9229,6 +9301,7 @@ accumulate_ki_native_u64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (uint64_t) (__li_buf_acc[__j]);
               }
@@ -9384,6 +9457,7 @@ accumulate_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -9463,6 +9537,7 @@ accumulate_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (float) (__li_buf_acc[__j]);
             }
@@ -9588,6 +9663,7 @@ accumulate_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -9618,8 +9694,8 @@ accumulate_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -9748,6 +9824,7 @@ accumulate_ki_native_f32 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (float) (__li_buf_acc[__j]);
               }
@@ -9903,6 +9980,7 @@ accumulate_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -9982,6 +10060,7 @@ accumulate_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (double) (__li_buf_acc[__j]);
             }
@@ -10107,6 +10186,7 @@ accumulate_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10137,8 +10217,8 @@ accumulate_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10267,6 +10347,7 @@ accumulate_ki_native_f64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxe
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (double) (__li_buf_acc[__j]);
               }
@@ -10422,6 +10503,7 @@ accumulate_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx64_t) (__li_buf_acc[__j]);
             }
@@ -10501,6 +10583,7 @@ accumulate_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx64_t) (__li_buf_acc[__j]);
             }
@@ -10626,6 +10709,7 @@ accumulate_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx64_t) (__li_buf_acc[__j]);
               }
@@ -10656,8 +10740,8 @@ accumulate_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -10786,6 +10870,7 @@ accumulate_ki_native_cmplx64 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx64_t) (__li_buf_acc[__j]);
               }
@@ -10941,6 +11026,7 @@ accumulate_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -11020,6 +11106,7 @@ accumulate_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
             }
@@ -11145,6 +11232,7 @@ accumulate_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -11175,8 +11263,8 @@ accumulate_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -11305,6 +11393,7 @@ accumulate_ki_native_cmplx128 (VALUE self, CArray *ca, int8_t *slab_axes, int8_t
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (cmplx128_t) (__li_buf_acc[__j]);
               }
@@ -11460,6 +11549,7 @@ accumulate_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (boolean8_t) (__li_buf_acc[__j]);
             }
@@ -11539,6 +11629,7 @@ accumulate_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (boolean8_t) (__li_buf_acc[__j]);
             }
@@ -11664,6 +11755,7 @@ accumulate_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (boolean8_t) (__li_buf_acc[__j]);
               }
@@ -11694,8 +11786,8 @@ accumulate_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -11824,6 +11916,7 @@ accumulate_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (boolean8_t) (__li_buf_acc[__j]);
               }
@@ -11908,7 +12001,7 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
       ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
       (void) masked_cnt;
       ca_lazy_arena_enter();
-      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire(__chunk_elems * sizeof(VALUE));
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
       while ( __outer_off < __outer ) {
         ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
         ca_size_t __n = __r * __inner;
@@ -11977,6 +12070,7 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -12056,6 +12150,7 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
             }
@@ -12181,6 +12276,7 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -12211,8 +12307,8 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12341,6 +12437,7 @@ accumulate_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t n
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (VALUE) (__li_buf_acc[__j]);
               }
@@ -12594,6 +12691,7 @@ count_true_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -12673,6 +12771,7 @@ count_true_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -12798,6 +12897,7 @@ count_true_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -12828,8 +12928,8 @@ count_true_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -12958,6 +13058,7 @@ count_true_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t nax
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -13161,6 +13262,7 @@ count_false_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t na
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               op[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -13240,6 +13342,7 @@ count_false_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t na
                 (void) v;
               }
             }
+
             for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
               __li_op_k[__li_o * __li_INNER + __li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
             }
@@ -13365,6 +13468,7 @@ count_false_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t na
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -13395,8 +13499,8 @@ count_false_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t na
        write stride 1 (= contig output tail) both preserved -> SIMD
        tile reduce + write maintained.
 
-       Performance characteristic (deliver-via-view, per the CLAUDE.md
-       "deliver the materials" principle): bench (b2 pattern, M=200, K=5, eff_INNER
+       Performance characteristic (deliver-via-view -- the surface
+       prioritises delivering the cells over avoiding a copy): bench (b2 pattern, M=200, K=5, eff_INNER
        =360, INNER_pre_K=16) yields 3674 us vs eager-entity 1545 us
        = 2.38x slow.  Root cause is the multi-parent data layout
        (= 5 separate 9 MB regions instead of one contig 46 MB),
@@ -13525,6 +13629,7 @@ count_false_ki_native_bool (VALUE self, CArray *ca, int8_t *slab_axes, int8_t na
                   (void) v;
                 }
               }
+    
               for ( ca_size_t __j = 0; __j < __li_tile_len; __j++ ) {
                 __li_op_k[__li_tile + __j] = (int64_t) (__li_buf_acc[__j]);
               }
@@ -14487,6 +14592,160 @@ ca_size_t   out_i = 0;
       return vout;
     }
 
+static VALUE
+count_equal_ki_native_object (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int keep_axis, VALUE value_arg, ca_size_t min_count)
+{
+    /* P.4.5.3b/c streaming chunked reduce: full reduction over lazy unmasked.  */
+    /* P.4.5.3c (N-D): outer-axis chunking, 1-D is the natural sub-case.        */
+    if ( naxes == ca->ndim && ca->ndim >= 1 && !keep_axis &&
+         ca_is_lazy_view(ca) && ! ca_has_mask(ca) ) {
+      ca_size_t __inner = 1;
+      int       __k;
+      for ( __k = 1; __k < ca->ndim; __k++ ) __inner *= ca->dim[__k];
+      ca_size_t __target = 4096;   /* L1d-friendly element budget (32KB for f64) */
+      ca_size_t __rows   = (__inner > 0) ? (__target / __inner) : __target;
+      if ( __rows < 1 ) __rows = 1;       /* at least one row per chunk */
+      ca_size_t __chunk_elems = __rows * __inner;
+      ca_size_t __outer       = ca->dim[0];
+      ca_size_t __starts[CA_RANK_MAX]  = {0};
+      ca_size_t __counts[CA_RANK_MAX];
+      ca_size_t __strides[CA_RANK_MAX];
+      ca_size_t __s = sizeof(VALUE);
+      for ( __k = ca->ndim - 1; __k >= 0; __k-- ) {
+        __strides[__k] = __s;
+        __s *= ca->dim[__k];
+      }
+      for ( __k = 1; __k < ca->ndim; __k++ ) __counts[__k] = ca->dim[__k];
+      ca_size_t __outer_off = 0;
+      int64_t acc;
+      acc = (0);
+      ca_size_t masked_cnt = 0;  /* unused on streaming (no mask) */
+      (void) masked_cnt;
+      ca_lazy_arena_enter();
+      VALUE *__chunk = (VALUE *) ca_lazy_arena_acquire_object(__chunk_elems);
+      while ( __outer_off < __outer ) {
+        ca_size_t __r = (__outer - __outer_off < __rows) ? (__outer - __outer_off) : __rows;
+        ca_size_t __n = __r * __inner;
+        __starts[0] = __outer_off;
+        __counts[0] = __r;
+        ca_xfer_stride(ca, __starts, __counts, __strides, __chunk, CA_XFER_GET);
+        ca_size_t __i;
+        for ( __i = 0; __i < __n; __i++ ) {
+          VALUE v = __chunk[__i];
+          if (RTEST(rb_equal(v, value_arg))) acc += 1;
+        }
+        __outer_off += __r;
+      }
+      ca_lazy_arena_release(__chunk);
+      ca_lazy_arena_exit();
+      return LL2NUM((int64_t) (acc));
+    }
+VALUE   vout  = rb_ca_new_reduced(self, slab_axes, naxes, CA_INT64, keep_axis);
+CArray *co;
+GetCArray(vout, co);
+int64_t *op = (int64_t *) co->ptr;
+ca_iter_state st;
+int rc = ca_iter_state_init_l2(&st, ca, CA_SLAB_AXES,
+                               slab_axes, naxes, 0);
+if ( rc != CA_ITER_OK ) {
+  rb_raise(rb_eRuntimeError,
+           "count_equal_ki: kernel_iterator init failed rc=%d", rc);
+}
+char       *p;
+boolean8_t *m;
+ca_size_t   out_i = 0;
+      boolean8_t *op_mask = NULL;   /* lazily allocated on first UNDEF */
+      while ( ca_iter_state_next_slab_axes(&st, &p, &m) ) {
+      int64_t acc;
+      ca_size_t masked_cnt = 0;
+      CA_SLAB_REDUCE_T_EX(VALUE, st, p, m, acc, 0, if (RTEST(rb_equal(v, value_arg))) acc += 1, masked_cnt);
+      if ( (min_count < 0 ? 0 : st.slab_elements - masked_cnt < min_count) ) {
+        if ( ! op_mask ) {
+          ca_create_mask(co);
+          op_mask = (boolean8_t *) co->mask->ptr;
+        }
+        op_mask[out_i] = 1;
+        op[out_i++] = (int64_t) 0;   /* sentinel; mask bit is what counts */
+      } else {
+        op[out_i++] = (int64_t) (acc);
+      }
+      }
+      ca_iter_state_finish(&st);
+      if ( naxes == ca->ndim && !keep_axis ) {
+        if ( op_mask && op_mask[0] ) return CA_UNDEF;
+        return LL2NUM(op[0]);
+      }
+      return vout;
+    }
+
+static VALUE
+count_equal_ki_native_fixlen (VALUE self, CArray *ca, int8_t *slab_axes, int8_t naxes, int keep_axis, const char *value_arg, ca_size_t min_count)
+{
+  ca_size_t K = ca->bytes;   /* uniform fixlen byte width */
+  VALUE   vout = rb_ca_new_reduced(self, slab_axes, naxes, CA_INT64, keep_axis);
+  CArray *co;
+  GetCArray(vout, co);
+  char       *op = (char *) co->ptr;
+  ca_iter_state st;
+  int rc = ca_iter_state_init_l2(&st, ca, CA_SLAB_AXES, slab_axes, naxes, 0);
+  if ( rc != CA_ITER_OK ) {
+    rb_raise(rb_eRuntimeError, "count_equal_ki: kernel_iterator init failed rc=%d", rc);
+  }
+  char       *p;
+  boolean8_t *m;
+  ca_size_t   out_i   = 0;
+  boolean8_t *op_mask = NULL;   /* lazily allocated on first UNDEF */
+  while ( ca_iter_state_next_slab_axes(&st, &p, &m) ) {
+    int64_t     cnt    = 0;
+    ca_size_t   masked_cnt = 0;
+    int8_t      sndim   = st.slab_ndim;
+    ca_size_t   sidx[CA_RANK_MAX] = { 0 };
+    ca_size_t   total   = st.slab_elements;
+    for ( ca_size_t idx = 0; idx < total; idx++ ) {
+      ca_size_t doff = 0, moff = 0;
+      for ( int8_t sk = 0; sk < sndim; sk++ ) {
+        doff += sidx[sk] * st.slab_strides[sk];
+        moff += sidx[sk] * st.slab_mask_strides[sk];
+      }
+      if ( m != NULL && m[moff] ) {
+        masked_cnt++;
+      }
+      else {
+        const char *q = (const char *) p + doff;
+        if ( memcmp(q, value_arg, (size_t) K) == 0 ) {
+          cnt++;
+        }
+      }
+      /* row-major odometer (innermost slab axis fastest) so idx
+         matches CA_SLAB_REDUCE_T's flat slab index. */
+      for ( int8_t sk = (int8_t)(sndim - 1); sk >= 0; sk-- ) {
+        if ( ++sidx[sk] < st.slab_dims[sk] ) break;
+        sidx[sk] = 0;
+      }
+    }
+    if ( min_count < 0 ? 0
+                       : st.slab_elements - masked_cnt < min_count ) {
+      if ( ! op_mask ) {
+        ca_create_mask(co);
+        op_mask = (boolean8_t *) co->mask->ptr;
+      }
+      op_mask[out_i] = 1;
+      ((int64_t *) op)[out_i] = 0;   /* sentinel; mask bit is what counts */
+      out_i++;
+    }
+    else {
+      ((int64_t *) op)[out_i] = cnt;
+      out_i++;
+    }
+  }
+  ca_iter_state_finish(&st);
+  if ( naxes == ca->ndim && !keep_axis ) {
+    if ( op_mask && op_mask[0] ) return CA_UNDEF;
+    return LL2NUM(((int64_t *) op)[0]);
+  }
+  return vout;
+}
+
 VALUE
 rb_ca_count_equal_ki (int argc, VALUE *argv, VALUE self)
 {
@@ -14567,8 +14826,19 @@ rb_ca_count_equal_ki (int argc, VALUE *argv, VALUE self)
       result = count_equal_ki_native_f64(self, src, slab_axes, naxes, keep_axis, value_arg, min_count);
       break;
     }
+    case CA_OBJECT: {
+      VALUE value_arg = (VALUE) (VALUE)(rval);
+      result = count_equal_ki_native_object(self, src, slab_axes, naxes, keep_axis, value_arg, min_count);
+      break;
+    }
+    case CA_FIXLEN: {
+      char *value_arg = ALLOCA_N(char, src->bytes);
+      rb_ca_obj2ptr(self, rval, value_arg);
+      result = count_equal_ki_native_fixlen(self, src, slab_axes, naxes, keep_axis, value_arg, min_count);
+      break;
+    }
     default:
-      rb_raise(rb_eCADataTypeError, "count_equal_ki: source data_type :%s not supported (expected one of: i8, u8, i16, u16, i32, u32, i64, u64, f32, f64)", ca_type_name[src->data_type]);
+      rb_raise(rb_eCADataTypeError, "count_equal_ki: source data_type :%s not supported (expected one of: i8, u8, i16, u16, i32, u32, i64, u64, f32, f64, object, fixlen)", ca_type_name[src->data_type]);
   }
   if ( ! NIL_P(rfval) ) {
     if ( result == CA_UNDEF ) {