blifutils 0.0.1

data/test/sqrt8.blif

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+# Module sqrt8
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 6 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  radicand<8>, go<1>
+#  Outputs: squareRoot<4>, done<1>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ......................... 6
+#  Number of primitives: ......................... 0
+#  Maximum primitive input bit width: ............ 0
+#  Average primitive input bit width: ............ 0
+#
+#  Number of inputs: ............................. 2
+#  Number of outputs: ............................ 2
+#  Number of input bits: ......................... 9
+#  Number of output bits: ........................ 5
+#
+#  Number of nets: .............................. 16
+#  Maximum number of fanout per net: ............. 1
+#  Average number of fanout per net: ........... 1.0
+#
+#  Number of instanciated modules: ............... 2
+#    Module   Instances
+#    sqrt8_PO ....... 1
+#    sqrt8_PC ....... 1
+
+.model sqrt8
+.inputs radicand[7] radicand[6] radicand[5] radicand[4] radicand[3] radicand[2] radicand[1] radicand[0]
+.inputs go[0]
+.outputs squareRoot[3] squareRoot[2] squareRoot[1] squareRoot[0]
+.outputs done[0]
+.search sqrt8_PO.blif
+.search sqrt8_PC.blif
+.subckt sqrt8_PO radicand[0]=radicand[0] radicand[1]=radicand[1] radicand[2]=radicand[2] radicand[3]=radicand[3] radicand[4]=radicand[4] radicand[5]=radicand[5] radicand[6]=radicand[6] radicand[7]=radicand[7] state[0]=n0 state[1]=n1 squareRoot[0]=squareRoot[0] squareRoot[1]=squareRoot[1] squareRoot[2]=squareRoot[2] squareRoot[3]=squareRoot[3]
+.subckt sqrt8_PC go[0]=go[0] done[0]=done[0] state[0]=n0 state[1]=n1
+.end
+

data/test/sqrt8.piccolo

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+/* This module computes 8-bit square root
+ * It is completely expanded so that each part can be seen in yEd
+ */
+
+
+module sqrt8(input<8> radicand, input go, output<4> squareRoot, output done) :
+	wire<2> state
+{
+	instance sqrt8_PC(go, done, state);
+	instance sqrt8_PO(radicand, state, squareRoot);
+}
+
+
+module sqrt8_PO(input<8> radicand, input<2> state, output<4> squareRoot) :
+	wire<4> sqrtr,
+	wire    fbit
+{
+	instance sqrt8_PO_work(state, radicand, sqrtr, fbit);
+	instance sqrt8_PO_sqrtr(state, fbit, sqrtr);
+	instance sqrt8_PO_output(state, sqrtr, squareRoot);
+}
+
+
+module sqrt8_PO_work(input<2> state, input<8> radicand, input<4> sqrtr, output fbit) :
+	reg<16> work,
+	wire<8> diff
+{
+	diff = work[15:8] - (2b00 : sqrtr : 2b01);
+	fbit = diff[7];
+
+	switch (state) {
+		case 'd1:
+			work = work[13:0] : 2b00;
+		case 'd2:
+			if (!fbit) {
+				work[15:8] = diff;
+			}
+		default:
+			work = 8b0 : radicand;
+	}
+}
+
+
+module sqrt8_PO_sqrtr(input<2> state, input fbit, output<4> sqrtr) :
+	reg<4>  sqrtrInt
+{
+	switch (state) {
+		case 'd0:
+			sqrtrInt = 'b0;
+		case 'd2:
+			sqrtrInt = sqrtrInt[2:0] : (~fbit);
+	}
+
+	sqrtr = sqrtrInt;
+}
+	
+
+module sqrt8_PO_output(input<2> state, input<4> sqrtr, output<4> squareRoot) :
+	reg<4>  squareRootInt
+{
+	switch (state) {
+		case 'd3:
+			squareRootInt = sqrtr;
+	}
+
+	squareRoot = squareRootInt;
+}
+
+
+module sqrt8_PC(input go, output done, output<2> state) : 
+	wire<2> counter
+{
+	instance sqrt8_PC_state(go, counter, state);
+	instance sqrt8_PC_counter(state, counter);
+	instance sqrt8_PC_done(state, done);
+}
+
+
+module sqrt8_PC_done(input<2> state, output done) : 
+	reg doneInt
+{
+	switch (state) {
+		case 'd3:
+			doneInt = 'b1;
+		default:
+			doneInt = 'b0;
+	}
+
+	done = doneInt;
+}
+		 
+
+module sqrt8_PC_counter(input<2> state, output<2> counter) : 
+	reg<2> counterInt
+{
+	switch (state) {
+		case 'd0:
+			counterInt = 'd0;
+		case 'd2:
+			counterInt = counterInt + 'd1;
+	}
+
+	counter = counterInt;
+}
+
+
+module sqrt8_PC_state(input go, input<2> counter, output<2> state) : 
+	reg<2> stateInt := 'd0
+{
+	switch (stateInt) {
+		case 'd0:
+			if (go) {
+				stateInt = 'd1;
+			}
+
+		case 'd1:
+			stateInt = 'd2;
+
+		case 'd2:
+			if (counter == 'd3) {
+				stateInt = 'd3;
+			} else {
+				stateInt = 'd1;
+			}
+
+		case 'd3:
+			stateInt = 'd0;
+	}
+
+	state = stateInt;
+}
+

data/test/sqrt8_PC.blif

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+# Module sqrt8_PC
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 70 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  go<1>
+#  Outputs: done<1>, state<2>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ......................... 6
+#  Number of primitives: ......................... 0
+#  Maximum primitive input bit width: ............ 0
+#  Average primitive input bit width: ............ 0
+#
+#  Number of inputs: ............................. 1
+#  Number of outputs: ............................ 2
+#  Number of input bits: ......................... 1
+#  Number of output bits: ........................ 3
+#
+#  Number of nets: ............................... 6
+#  Maximum number of fanout per net: ............. 3
+#  Average number of fanout per net: ........... 1.7
+#
+#  Number of instanciated modules: ............... 3
+#    Module           Instances
+#    sqrt8_PC_done .......... 1
+#    sqrt8_PC_state ......... 1
+#    sqrt8_PC_counter ....... 1
+
+.model sqrt8_PC
+.inputs _clk_
+.inputs go[0]
+.outputs done[0]
+.outputs state[1] state[0]
+.search sqrt8_PC_done.blif
+.search sqrt8_PC_state.blif
+.search sqrt8_PC_counter.blif
+.subckt sqrt8_PC_done state[0]=state[0] state[1]=state[1] done[0]=done[0] _clk_=_clk_
+.subckt sqrt8_PC_state go[0]=go[0] counter[0]=n0 counter[1]=n1 state[0]=state[0] state[1]=state[1] _clk_=_clk_
+.subckt sqrt8_PC_counter state[0]=state[0] state[1]=state[1] counter[0]=n0 counter[1]=n1 _clk_=_clk_
+.end
+

data/test/sqrt8_PC_counter.blif

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+# Module sqrt8_PC_counter
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 93 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  state<2>
+#  Outputs: counter<2>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ......................... 8
+#  Number of primitives: ......................... 6
+#  Maximum primitive input bit width: ............ 4
+#  Average primitive input bit width: .......... 2.2
+#
+#  Number of inputs: ............................. 1
+#  Number of outputs: ............................ 1
+#  Number of input bits: ......................... 2
+#  Number of output bits: ........................ 2
+#
+#  Number of nets: ............................... 8
+#  Maximum number of fanout per net: ............. 4
+#  Average number of fanout per net: ........... 1.9
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output selector ........................ 2
+#  Register ...................................... 2
+#  Single output NOT gate ........................ 1
+#  Single output XOR gate ........................ 1
+#
+#  Number of register bits: ...................... 2
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 4
+#  Average selector total input bit width: ..... 4.0
+#  Maximum selector input bit width: ............. 2
+#  Average selector input bit width: ........... 2.0
+#  Maximum selector selector bit width: .......... 2
+#  Average selector selector bit width: ........ 2.0
+
+.model sqrt8_PC_counter
+.inputs _clk_
+.inputs state[1] state[0]
+.outputs counter[1] counter[0]
+.latch n0 counter[0] re _clk_ 0
+.latch n1 counter[1] re _clk_ 0
+.names counter[1] counter[0] n3
+10 1
+01 1
+.names state[0] state[1] counter[0] n2 n0
+1-1- 1
+01-1 1
+.names state[0] state[1] counter[1] n3 n1
+1-1- 1
+01-1 1
+.names counter[0] n2
+0 1
+.end
+

data/test/sqrt8_PC_done.blif

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+# Module sqrt8_PC_done
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 79 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  state<2>
+#  Outputs: done<1>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ......................... 4
+#  Number of primitives: ......................... 2
+#  Maximum primitive input bit width: ............ 2
+#  Average primitive input bit width: .......... 1.5
+#
+#  Number of inputs: ............................. 1
+#  Number of outputs: ............................ 1
+#  Number of input bits: ......................... 2
+#  Number of output bits: ........................ 1
+#
+#  Number of nets: ............................... 4
+#  Maximum number of fanout per net: ............. 1
+#  Average number of fanout per net: ........... 1.0
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output selector ........................ 1
+#  Register ...................................... 1
+#
+#  Number of register bits: ...................... 1
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 2
+#  Average selector total input bit width: ..... 2.0
+#  Maximum selector input bit width: ............. 0
+#  Average selector input bit width: ........... 0.0
+#  Maximum selector selector bit width: .......... 2
+#  Average selector selector bit width: ........ 2.0
+
+.model sqrt8_PC_done
+.inputs _clk_
+.inputs state[1] state[0]
+.outputs done[0]
+.latch n0 done[0] re _clk_ 0
+.names state[0] state[1]  n0
+11 1
+.end
+

data/test/sqrt8_PC_state.blif

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+# Module sqrt8_PC_state
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 107 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  go<1>, counter<2>
+#  Outputs: state<2>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ........................ 11
+#  Number of primitives: ......................... 8
+#  Maximum primitive input bit width: ............ 5
+#  Average primitive input bit width: .......... 2.0
+#
+#  Number of inputs: ............................. 2
+#  Number of outputs: ............................ 1
+#  Number of input bits: ......................... 3
+#  Number of output bits: ........................ 2
+#
+#  Number of nets: .............................. 11
+#  Maximum number of fanout per net: ............. 4
+#  Average number of fanout per net: ........... 1.6
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output NOT gate ........................ 3
+#  Single output selector ........................ 2
+#  Register ...................................... 2
+#  Single output  OR gate ........................ 1
+#
+#  Number of register bits: ...................... 2
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 5
+#  Average selector total input bit width: ..... 4.5
+#  Maximum selector input bit width: ............. 2
+#  Average selector input bit width: ........... 1.5
+#  Maximum selector selector bit width: .......... 3
+#  Average selector selector bit width: ........ 3.0
+
+.model sqrt8_PC_state
+.inputs _clk_
+.inputs go[0]
+.inputs counter[1] counter[0]
+.outputs state[1] state[0]
+.latch n0 state[0] re _clk_ 0
+.latch n1 state[1] re _clk_ 0
+.names n4 n5 n3
+1- 1
+-1 1
+.names n3 n2
+0 1
+.names go[0] state[0] state[1] state[0] n0
+10-- 1
+-01- 1
+0001 1
+.names go[0] state[0] state[1] n2 state[1] n1
+-10-- 1
+-011- 1
+000-1 1
+.names counter[0] n4
+0 1
+.names counter[1] n5
+0 1
+.end
+

data/test/sqrt8_PO.blif

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+# Module sqrt8_PO
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 14 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  radicand<8>, state<2>
+#  Outputs: squareRoot<4>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ......................... 6
+#  Number of primitives: ......................... 0
+#  Maximum primitive input bit width: ............ 0
+#  Average primitive input bit width: ............ 0
+#
+#  Number of inputs: ............................. 2
+#  Number of outputs: ............................ 1
+#  Number of input bits: ........................ 10
+#  Number of output bits: ........................ 4
+#
+#  Number of nets: .............................. 19
+#  Maximum number of fanout per net: ............. 3
+#  Average number of fanout per net: ........... 1.4
+#
+#  Number of instanciated modules: ............... 3
+#    Module          Instances
+#    sqrt8_PO_output ....... 1
+#    sqrt8_PO_sqrtr ........ 1
+#    sqrt8_PO_work ......... 1
+
+.model sqrt8_PO
+.inputs _clk_
+.inputs radicand[7] radicand[6] radicand[5] radicand[4] radicand[3] radicand[2] radicand[1] radicand[0]
+.inputs state[1] state[0]
+.outputs squareRoot[3] squareRoot[2] squareRoot[1] squareRoot[0]
+.search sqrt8_PO_output.blif
+.search sqrt8_PO_sqrtr.blif
+.search sqrt8_PO_work.blif
+.subckt sqrt8_PO_output state[0]=state[0] state[1]=state[1] sqrtr[0]=n0 sqrtr[1]=n1 sqrtr[2]=n2 sqrtr[3]=n3 squareRoot[0]=squareRoot[0] squareRoot[1]=squareRoot[1] squareRoot[2]=squareRoot[2] squareRoot[3]=squareRoot[3] _clk_=_clk_
+.subckt sqrt8_PO_sqrtr state[0]=state[0] state[1]=state[1] fbit[0]=n4 sqrtr[0]=n0 sqrtr[1]=n1 sqrtr[2]=n2 sqrtr[3]=n3 _clk_=_clk_
+.subckt sqrt8_PO_work state[0]=state[0] state[1]=state[1] radicand[0]=radicand[0] radicand[1]=radicand[1] radicand[2]=radicand[2] radicand[3]=radicand[3] radicand[4]=radicand[4] radicand[5]=radicand[5] radicand[6]=radicand[6] radicand[7]=radicand[7] sqrtr[0]=n0 sqrtr[1]=n1 sqrtr[2]=n2 sqrtr[3]=n3 fbit[0]=n4 _clk_=_clk_
+.end
+

data/test/sqrt8_PO_output.blif

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+# Module sqrt8_PO_output
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 58 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  state<2>, sqrtr<4>
+#  Outputs: squareRoot<4>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ........................ 11
+#  Number of primitives: ......................... 8
+#  Maximum primitive input bit width: ............ 4
+#  Average primitive input bit width: .......... 2.5
+#
+#  Number of inputs: ............................. 2
+#  Number of outputs: ............................ 1
+#  Number of input bits: ......................... 6
+#  Number of output bits: ........................ 4
+#
+#  Number of nets: .............................. 14
+#  Maximum number of fanout per net: ............. 4
+#  Average number of fanout per net: ........... 1.7
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output selector ........................ 4
+#  Register ...................................... 4
+#
+#  Number of register bits: ...................... 4
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 4
+#  Average selector total input bit width: ..... 4.0
+#  Maximum selector input bit width: ............. 2
+#  Average selector input bit width: ........... 2.0
+#  Maximum selector selector bit width: .......... 2
+#  Average selector selector bit width: ........ 2.0
+
+.model sqrt8_PO_output
+.inputs _clk_
+.inputs state[1] state[0]
+.inputs sqrtr[3] sqrtr[2] sqrtr[1] sqrtr[0]
+.outputs squareRoot[3] squareRoot[2] squareRoot[1] squareRoot[0]
+.latch n0 squareRoot[0] re _clk_ 0
+.latch n1 squareRoot[1] re _clk_ 0
+.latch n2 squareRoot[2] re _clk_ 0
+.latch n3 squareRoot[3] re _clk_ 0
+.names state[0] state[1] squareRoot[0] sqrtr[0] n0
+-01- 1
+0-1- 1
+11-1 1
+.names state[0] state[1] squareRoot[1] sqrtr[1] n1
+-01- 1
+0-1- 1
+11-1 1
+.names state[0] state[1] squareRoot[2] sqrtr[2] n2
+-01- 1
+0-1- 1
+11-1 1
+.names state[0] state[1] squareRoot[3] sqrtr[3] n3
+-01- 1
+0-1- 1
+11-1 1
+.end
+