blifutils 0.0.1

data/examples/zpu/compile_zpu_program/Makefile

@@ -0,0 +1,114 @@
+TARGET = zpu_helloworld
+
+SRCC       += main.c
+
+OPTIMISATION = 2
+WARNINGS = -W -Wall
+
+## The toolchain path ##
+#TC      = /opt/zpugcc/bin/zpu-elf
+TC      = zpu-elf
+CC      = $(TC)-gcc
+LD      = $(TC)-gcc
+AR      = $(TC)-ar
+SIZE    = $(TC)-size
+OBJCOPY = $(TC)-objcopy
+OBJDUMP = $(TC)-objdump
+
+
+
+OBJS      += $(SRCC:.c=.o) $(SRCS:.s=.o)
+ASM       += $(SRCC:.c=.S)
+
+
+INCLUDEPATH  += -I.
+COMMONFLAGS  += -O$(OPTIMISATION) -phi -g
+CFLAGS       += $(COMMONFLAGS) $(INCLUDEPATH) $(WARNINGS)
+LDLIBS       += -lm
+LIBDIR       += -L .
+
+
+
+LDFLAGS      += $(COMMONFLAGS) $(LIBDIR)
+
+
+LDFLAGS += -Wl,--gc-sections -Wl,--relax -Wl,-Map=./$(TARGET).map
+
+ifdef LD_FILE
+LDFLAGS += -Wl,-T$(LD_FILE)
+endif
+
+
+all: $(TARGET).bin
+
+
+################################################################################
+############################### ELF output #####################################
+################################################################################
+
+
+$(TARGET).elf: $(OBJS) 
+	$(LD) -o $(TARGET).elf $(LDFLAGS) $(OBJS) -Wl,--no-whole-archive $(LDLIBS)
+	$(SIZE) $(TARGET).elf
+
+%.o : %.c
+	$(CC) $(CFLAGS) -c $< -o $@
+
+%.o : %.s
+	$(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@
+
+disasm: $(TARGET).elf
+	$(OBJDUMP) -h -S -D -z $(TARGET).elf > $(TARGET).lss
+
+
+################################################################################
+################################### ASM ########################################
+################################################################################
+
+
+asm: $(ASM)
+
+%.S : %.c
+	$(CC) $(CFLAGS) -S $< -o $@
+
+
+################################################################################
+############################ HEX and BIN output ################################
+################################################################################
+
+
+hex: $(TARGET).hex 
+
+$(TARGET).hex: $(TARGET).elf
+	$(OBJCOPY) -O ihex $(TARGET).elf $@
+
+bin: $(TARGET).bin
+
+$(TARGET).bin: $(TARGET).elf
+	$(OBJCOPY) -O binary $(TARGET).elf $@
+
+size: $(TARGET).elf
+	$(SIZE) $<
+
+
+################################################################################
+################################### Clean ######################################
+################################################################################
+
+
+clean:
+	@rm -fv $(OBJS) 
+	@rm -fv $(ASM) 
+	@rm -fv $(TARGET).hex
+	@rm -fv $(TARGET).bin 
+	@rm -fv $(TARGET)_BigEndian.bin 
+	@rm -fv $(TARGET)_BigEndian_back.bin 
+	@rm -fv $(TARGET).elf
+	@rm -fv $(TARGET).map
+	@rm -fv $(TARGET).lss
+
+
+
+################################################################################
+################################### END ########################################
+################################################################################

data/examples/zpu/compile_zpu_program/README.md

@@ -0,0 +1,10 @@
+
+To compile main.c, you will need the ZPU toolchain.
+It can be found at https://github.com/zylin/zpugcc
+
+Once zpu-elf-gcc is in your path, just type 
+
+$ make
+
+This will compile zpu_helloworld.bin.
+

data/examples/zpu/compile_zpu_program/main.c

@@ -0,0 +1,68 @@
+
+void print_char(char c)
+{
+	*(char*)0x8003 = c;
+}
+
+
+void print_int(int v)
+{
+	char buf[10];
+	int i;
+	int tmp;
+
+	if (v == 0) {
+		print_char('0');
+		return;
+	}
+
+	if (v < 0) {
+		print_char('-');
+		v = -v;
+	}
+
+	i = 0;
+	while (v > 0) {
+		tmp = v / 10;
+		buf[i++] = v - tmp*10 + '0';
+		v = tmp;
+	}
+
+	for (i--; i >= 0; i--)
+		print_char(buf[i]);
+}
+
+void print_string(const char *str)
+{
+	char c;
+
+	while ((c = *str++)) 
+		print_char(c);
+}
+
+
+int main()
+{
+	int i;
+	int fib_n = -1;
+	int fib_np1 = 1;
+	int fib_np2;
+
+	print_string("Hello, world!\n");
+	print_string("What you see is the simulation of a BLIF netlist implementing a processor,\n");
+	print_string("which is itself executing a helloworld in the simulation.\n\n");
+
+	print_string("Here are the first 26 Fibonacci numbers:\n");
+	for (i = 0; i < 26; i++) {
+		fib_np2 = fib_n + fib_np1;
+		fib_n   = fib_np1;
+		fib_np1 = fib_np2;
+		print_int(i);
+		print_string(" -> ");
+		print_int(fib_np2);
+		print_char('\n');
+	}
+
+	return 0;
+}
+

data/examples/zpu/simulate_zpu.rb

@@ -0,0 +1,23 @@
+#!/usr/bin/env ruby
+
+require 'blifutils'
+
+netlist = BlifUtils::read('zpu_mem16.blif')
+
+puts '-'*60
+puts netlist.analyze
+puts '-'*60
+
+netlist.create_simulation_file_for_model
+
+puts '-- Compiling testbench '.ljust(60, '-')
+testbench_exec = 'zpu_simulation'
+cmd = "g++ -W -Wall -I. -o #{testbench_exec} testbench_zpu.cc zpu_mem16_cpp_sim.o"
+puts "Executing: #{cmd}"
+abort unless system cmd
+puts "You can now execute the testbench with \"./#{testbench_exec} <zpu_compiled_program>\""
+
+puts '-- Executing simulation '.ljust(60, '-')
+cmd = "./#{testbench_exec} zpu_helloworld.bin"
+puts "Executing: #{cmd}"
+abort unless system cmd

data/examples/zpu/testbench_zpu.cc

@@ -0,0 +1,132 @@
+#include "zpu_mem16_cpp_header.hh"
+#include <cstdlib>
+#include <cstdio>
+#include <cmath>
+#include <ctime>
+#include <unistd.h>
+
+
+int main(int argc, char *argv[])
+{
+	uint32_t mem[8192];
+	uint32_t addr(0);
+	uint32_t word;
+	int byte;
+	FILE *inFile(NULL);
+	unsigned int cclock(0);
+	ZpuMem16SimulationClass *dut;
+    clock_t startTime, stopTime;
+	bool valid;
+
+	if (argc != 2) {
+		fprintf(stderr, "usage: %s <bin_file>\n", argv[0]);
+		return EXIT_FAILURE;
+	}
+
+	if ((inFile = fopen(argv[1], "r")) == NULL) {
+		fprintf(stderr, "Cannot open file \"%s\"\n", argv[1]);
+		return EXIT_FAILURE;
+	}
+
+	/* Load simulation memory in big-endian */
+	for (addr = 0; addr < (sizeof(mem) / 4); addr++) {
+		word = 0;
+
+		byte = fgetc(inFile);
+		if (byte == EOF) {
+			break;
+		}
+		word |= byte << 24;
+		byte = fgetc(inFile);
+		if (byte == EOF) {
+			break;
+		}
+		word |= byte << 16;
+		byte = fgetc(inFile);
+		if (byte == EOF) {
+			break;
+		}
+		word |= byte << 8;
+		byte = fgetc(inFile);
+		if (byte == EOF) {
+			break;
+		}
+		word |= byte;
+		mem[addr] = word;
+	}
+
+	fclose(inFile);
+
+	printf("Read %u bytes from file '%s' (memory filled %.1f%%)\n",
+			(addr << 2), argv[1], (float)addr * 100.0f / (float)(sizeof(mem) / 4.0f));
+
+	for (; addr < (sizeof(mem) / 4); addr++) {
+		mem[addr] = 0;
+	}
+
+	dut = new ZpuMem16SimulationClass();
+
+	printf("Starting simulation\n");
+
+	startTime = clock();
+
+	dut->reset();
+	dut->INPUT_VECTOR_DAT_I->setValue(0UL);
+	dut->INPUT_VECTOR_ACK_I->setValue(0UL);
+	dut->propagate();
+
+	/* Simulate a wishbone bus */
+	while (dut->OUTPUT_NET_BREAKPOINT->getValue() != 1) {
+		if (dut->OUTPUT_NET_CYC_O->getValue() == 1) {
+			addr = dut->OUTPUT_VECTOR_ADR_O->getValue(&valid);
+			if (valid != true) {
+				std::cerr << "\033[1;31mADR_O not valid (" << cclock << ")\033[0m" << std::endl;
+				exit(EXIT_FAILURE);
+			}
+			if (dut->OUTPUT_NET_WE_O->getValue() == 1) {
+				if (addr >= (sizeof(mem) / 4)) {
+					//printf("\naddr: 0x%x ", addr);
+					uint64_t car = dut->OUTPUT_VECTOR_DAT_O->getValue(&valid);
+					if (valid != true) {
+						std::cerr << "\033[1;31mDAT_O not valid (" << cclock << ")\033[0m" << std::endl;
+						exit(EXIT_FAILURE);
+					}
+					write(1, &car, 1);
+				} else {
+					mem[addr] = (uint32_t)dut->OUTPUT_VECTOR_DAT_O->getValue(&valid);
+					if (valid != true) {
+						std::cerr << "\033[1;31mDAT_O not valid (" << cclock << ")\033[0m" << std::endl;
+						exit(EXIT_FAILURE);
+					}
+				}
+				//printf("Write 0x%08x @ 0x%08x\n", mem[addr], addr << 2);
+			} else {
+				dut->INPUT_VECTOR_DAT_I->setValue((uint64_t)mem[addr]);
+				//printf("Read  0x%08x @ 0x%08x\n", mem[addr], addr << 2);
+			}
+			dut->INPUT_NET_ACK_I->setValue(1);
+			dut->propagate();
+			dut->clock();
+			cclock++;
+			dut->INPUT_NET_ACK_I->setValue(0);
+			dut->propagate();
+		} else {
+			dut->clock();
+			cclock++;
+			dut->propagate();
+		}
+	}
+
+	stopTime = clock();
+
+	printf("Simulation ended\n");
+	float execTime = (float)(stopTime - startTime)/(float)(CLOCKS_PER_SEC);
+	printf("%u clock cycles in %.3f s\n", cclock, execTime);
+	printf("Simulation average clock speed: %u Hz\n", (unsigned int)((float)cclock / execTime));
+
+
+	delete dut;
+
+	return EXIT_SUCCESS;
+}
+

data/examples/zpu/zpu_mem16.blif

@@ -0,0 +1,3519 @@
+.model zpu_mem16
+.inputs _clk_ DAT_I[31] DAT_I[30] DAT_I[29] DAT_I[28] DAT_I[27] DAT_I[26] \
+ DAT_I[25] DAT_I[24] DAT_I[23] DAT_I[22] DAT_I[21] DAT_I[20] DAT_I[19] \
+ DAT_I[18] DAT_I[17] DAT_I[16] DAT_I[15] DAT_I[14] DAT_I[13] DAT_I[12] \
+ DAT_I[11] DAT_I[10] DAT_I[9] DAT_I[8] DAT_I[7] DAT_I[6] DAT_I[5] DAT_I[4] \
+ DAT_I[3] DAT_I[2] DAT_I[1] DAT_I[0] ACK_I[0]
+.outputs CYC_O[0] STB_O[0] WE_O[0] ADR_O[13] ADR_O[12] ADR_O[11] ADR_O[10] \
+ ADR_O[9] ADR_O[8] ADR_O[7] ADR_O[6] ADR_O[5] ADR_O[4] ADR_O[3] ADR_O[2] \
+ ADR_O[1] ADR_O[0] DAT_O[31] DAT_O[30] DAT_O[29] DAT_O[28] DAT_O[27] DAT_O[26] \
+ DAT_O[25] DAT_O[24] DAT_O[23] DAT_O[22] DAT_O[21] DAT_O[20] DAT_O[19] \
+ DAT_O[18] DAT_O[17] DAT_O[16] DAT_O[15] DAT_O[14] DAT_O[13] DAT_O[12] \
+ DAT_O[11] DAT_O[10] DAT_O[9] DAT_O[8] DAT_O[7] DAT_O[6] DAT_O[5] DAT_O[4] \
+ DAT_O[3] DAT_O[2] DAT_O[1] DAT_O[0] BREAKPOINT[0]
+.clock clk
+.latch li000 lo000 re clk 0
+.latch li001 lo001 re clk 0
+.latch li002 lo002 re clk 0
+.latch n182_1 n52 re clk 0
+.latch li004 lo004 re clk 0
+.latch li005 lo005 re clk 0
+.latch li006 lo006 re clk 0
+.latch li007 lo007 re clk 0
+.latch li008 lo008 re clk 0
+.latch li009 lo009 re clk 0
+.latch li010 lo010 re clk 0
+.latch li011 lo011 re clk 0
+.latch li012 lo012 re clk 0
+.latch li013 lo013 re clk 0
+.latch li014 lo014 re clk 0
+.latch li015 lo015 re clk 0
+.latch li016 lo016 re clk 0
+.latch li017 lo017 re clk 0
+.latch li018 lo018 re clk 0
+.latch li019 lo019 re clk 0
+.latch li020 lo020 re clk 0
+.latch li021 lo021 re clk 0
+.latch li022 lo022 re clk 0
+.latch li023 lo023 re clk 0
+.latch li024 lo024 re clk 0
+.latch li025 lo025 re clk 0
+.latch li026 lo026 re clk 0
+.latch li027 lo027 re clk 0
+.latch li028 lo028 re clk 0
+.latch li029 lo029 re clk 0
+.latch li030 lo030 re clk 0
+.latch li031 lo031 re clk 0
+.latch li032 lo032 re clk 0
+.latch li033 lo033 re clk 0
+.latch li034 lo034 re clk 0
+.latch li035 lo035 re clk 0
+.latch li036 lo036 re clk 0
+.latch li037 lo037 re clk 0
+.latch li038 lo038 re clk 0
+.latch li039 lo039 re clk 0
+.latch li040 lo040 re clk 0
+.latch li041 lo041 re clk 0
+.latch li042 lo042 re clk 0
+.latch li043 lo043 re clk 0
+.latch li044 lo044 re clk 0
+.latch li045 lo045 re clk 0
+.latch li046 lo046 re clk 0
+.latch li047 lo047 re clk 0
+.latch li048 lo048 re clk 0
+.latch li049 lo049 re clk 0
+.latch n371_1 n32 re clk 0
+.latch n376_1 n34 re clk 0
+.latch n381_1 n36 re clk 0
+.latch n386_1 n38 re clk 0
+.latch n391_1 n58 re clk 0
+.latch n396_1 n5A re clk 0
+.latch n401_1 n5C re clk 0
+.latch n406_1 n5E re clk 0
+.latch n411_1 n60 re clk 0
+.latch n416_1 n62 re clk 0
+.latch n421_1 n64 re clk 0
+.latch n426_1 n4F re clk 0
+.latch n431_1 n76 re clk 0
+.latch n436_1 n78 re clk 0
+.latch n441_1 n7A re clk 0
+.latch n446_1 n7C re clk 0
+.latch n451_1 n7E re clk 0
+.latch n456_1 n80 re clk 0
+.latch n461_1 n82 re clk 0
+.latch n466_1 n84 re clk 0
+.latch n471_1 n86 re clk 0
+.latch n476_1 n88 re clk 0
+.latch n481_1 n8A re clk 0
+.latch n486_1 n8C re clk 0
+.latch n491_1 n8E re clk 0
+.latch n496_1 n90 re clk 0
+.latch n501_1 n92 re clk 0
+.latch n506_1 n94 re clk 0
+.latch n511_1 n117 re clk 0
+.latch n516_1 n119 re clk 0
+.latch n521_1 n11B re clk 0
+.latch n526_1 n11D re clk 0
+.latch n531_1 n11F re clk 0
+.latch n536_1 n121 re clk 0
+.latch n541_1 n123 re clk 0
+.latch n546_1 n125 re clk 0
+.latch n551_1 n127 re clk 0
+.latch n556_1 n129 re clk 0
+.latch n561_1 n12B re clk 0
+.latch n566_1 n12D re clk 0
+.latch n571_1 n12F re clk 0
+.latch n576_1 n131 re clk 0
+.latch n581_1 n1E1 re clk 0
+.latch n586_1 n1E3 re clk 0
+.latch n591_1 n14F re clk 0
+.latch n596_1 n151 re clk 0
+.latch n601 n153 re clk 0
+.latch n606 n155 re clk 0
+.latch n611 n157 re clk 0
+.latch n616 n159 re clk 0
+.latch n621 n15B re clk 0
+.latch n626 n15D re clk 0
+.latch n631 n15F re clk 0
+.latch n636 n161 re clk 0
+.latch n641 n163 re clk 0
+.latch n646 n165 re clk 0
+.latch n651 n167 re clk 0
+.latch n656 n169 re clk 0
+.latch n661 n1E5 re clk 0
+.latch n666 n1E7 re clk 0
+.latch n671 n1E9 re clk 0
+.latch n676 n1EB re clk 0
+.latch n681 n1ED re clk 0
+.latch n686 n1EF re clk 0
+.latch n691 n1F1 re clk 0
+.latch n696 n1F3 re clk 0
+.latch n701 n1F5 re clk 0
+.latch n706 n1F7 re clk 0
+.latch n711 n1F9 re clk 0
+.latch n716 n1FB re clk 0
+.latch n721 n1FD re clk 0
+.latch n726 n1FF re clk 0
+.latch n731 n201 re clk 0
+.latch n736 n203 re clk 0
+.latch n741 n42D re clk 0
+.latch n746 n42F re clk 0
+.latch n751 n431 re clk 0
+.latch n756 n433 re clk 0
+.latch n761 n435 re clk 0
+.latch n766 n437 re clk 0
+.latch n771 n439 re clk 0
+.latch n776 n43B re clk 0
+.latch n781 n43D re clk 0
+.latch n786 n43F re clk 0
+.latch n791 n441 re clk 0
+.latch n796 n443 re clk 0
+.latch n801 n445 re clk 0
+.latch n806 n447 re clk 0
+.latch n811 n449 re clk 0
+.latch n816 n44B re clk 0
+.latch n821 n44D re clk 0
+.latch n826 n44F re clk 0
+.latch n831 n451 re clk 0
+.latch n836 n453 re clk 0
+.latch n841 n455 re clk 0
+.latch n846 n457 re clk 0
+.latch n851 n459 re clk 0
+.latch n856 n45B re clk 0
+.latch n861 n45D re clk 0
+.latch n866 n45F re clk 0
+.latch n871 n461 re clk 0
+.latch n876 n463 re clk 0
+.latch n881 n465 re clk 0
+.latch n886 n467 re clk 0
+.latch n891 n469 re clk 0
+.latch n896 n46B re clk 0
+.names ACK_I[0] lo000 n32 n36 n38 n34 li000
+--0001 0
+--1111 0
+11---- 0
+.names lo001 n32 n34 n38 li001
+-011 1
+-101 1
+1--1 1
+.names n32 n34 n36 n38 li002
+1111 1
+.names n36 lo004 n561 n117 n558 li004
+----1 1
+0111- 1
+.names n569 lo004 n566 n559 n564 n558
+---10 1
+--0-0 1
+11--0 1
+.names n562 lo004 n563 n58 n117 n560 n559
+--1011 1
+--1101 1
+-10001 1
+-10111 1
+01-011 1
+01-101 1
+1-0001 1
+1-0111 1
+.names n561 n36 n560
+11 1
+.names n38 n34 n561
+01 1
+.names n62 n64 n4F n60 n562
+0001 1
+.names n4F n64 n62 n563
+011 1
+.names n34 n7A lo004 n565 n36 n38 n564
+---0-- 0
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+.names n32 n117 n38 lo004 n34 n36 n565
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+-0-11- 0
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+1----- 0
+.names n567 n58 n117 n568 n566
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+001 1
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+.names n32 n576 n571 li005
+-10 1
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+.names lo005 n574 n572 n563 n562 n573 n571
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+--10-1 1
+--11-0 1
+-0-111 1
+1--000 1
+.names n117 n119 n577
+01 1
+10 1
+.names n585 n32 n579 n583 li006
+--01 0
+00-- 0
+.names lo006 n580 n581 n562 n563 n560 n579
+--0-11 1
+-0-101 1
+1--001 1
+.names n58 n5A n119 n581 n117 n580
+-0011 1
+-0110 1
+-1010 1
+-1111 1
+0--11 1
+00000 1
+01100 1
+1--10 1
+10101 1
+11001 1
+.names n582 n5C n11B n581
+000 1
+011 1
+101 1
+110 1
+.names n5A n119 n117 n58 n582
+-111 1
+1-11 1
+11-- 1
+.names n569 lo006 n567 n580 n584 n583
+----0 0
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+.names n11B n153 n36 n34 n38 n32 n584
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+0---01 1
+.names n7E n586 lo006 n34 n36 n38 n585
+--1-01 1
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+.names n117 n119 n11B n586
+-10 1
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+1-0 1
+.names n593 n32 n560 n588 n591 li007
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+.names lo007 n589 n590 n563 n562 n588
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+-1001 1
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+.names n58 n117 n5A n119 n581 n589
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+11011 1
+11101 1
+.names n582 n5C n11B n5E n11D n590
+-0000 1
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+00-00 1
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+11-10 1
+.names n569 lo007 n592 n590 n589 n567 n591
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+11---- 0
+.names n11D n155 n36 n34 n38 n32 n592
+--00-1 1
+--11-1 1
+-0--11 1
+0---01 1
+.names n80 n594 lo007 n36 n38 n34 n593
+--1-10 1
+--11-0 1
+-0-111 1
+-01--1 1
+1--000 1
+.names n595 n11D n38 n36 n594
+0011 1
+1111 1
+.names n117 n119 n11B n595
+000 1
+.names n605 n32 n597 n602 li008
+--01 0
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+.names n598 n600 n60 n563 n560 n597
+-0011 1
+-1111 1
+1--01 1
+.names lo008 n599 n600 n562 n598
+-011 1
+-101 1
+1--0 1
+.names n589 n590 n599
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