blifutils 0.0.1

data/test/sqrt8_PO_sqrtr.blif

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+# Module sqrt8_PO_sqrtr
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 44 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  state<2>, fbit<1>
+#  Outputs: sqrtr<4>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ........................ 12
+#  Number of primitives: ......................... 9
+#  Maximum primitive input bit width: ............ 4
+#  Average primitive input bit width: .......... 2.3
+#
+#  Number of inputs: ............................. 2
+#  Number of outputs: ............................ 1
+#  Number of input bits: ......................... 3
+#  Number of output bits: ........................ 4
+#
+#  Number of nets: .............................. 12
+#  Maximum number of fanout per net: ............. 4
+#  Average number of fanout per net: ........... 2.1
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output selector ........................ 4
+#  Register ...................................... 4
+#  Single output NOT gate ........................ 1
+#
+#  Number of register bits: ...................... 4
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 4
+#  Average selector total input bit width: ..... 4.0
+#  Maximum selector input bit width: ............. 2
+#  Average selector input bit width: ........... 2.0
+#  Maximum selector selector bit width: .......... 2
+#  Average selector selector bit width: ........ 2.0
+
+.model sqrt8_PO_sqrtr
+.inputs _clk_
+.inputs state[1] state[0]
+.inputs fbit[0]
+.outputs sqrtr[3] sqrtr[2] sqrtr[1] sqrtr[0]
+.latch n0 sqrtr[0] re _clk_ 0
+.latch n1 sqrtr[1] re _clk_ 0
+.latch n2 sqrtr[2] re _clk_ 0
+.latch n3 sqrtr[3] re _clk_ 0
+.names fbit[0] n4
+0 1
+.names state[0] state[1] sqrtr[0] n4 n0
+1-1- 1
+01-1 1
+.names state[0] state[1] sqrtr[0] sqrtr[1] n1
+011- 1
+1--1 1
+.names state[0] state[1] sqrtr[1] sqrtr[2] n2
+011- 1
+1--1 1
+.names state[0] state[1] sqrtr[2] sqrtr[3] n3
+011- 1
+1--1 1
+.end
+

data/test/sqrt8_PO_work.blif

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+# Module sqrt8_PO_work
+# Generated by PICCOLO on Sunday 26 November 2017 at 17:05:04
+# Defined line 24 from file "/home/theotime/Documents/projects/blifutils/test/sqrt8.piccolo"
+#
+# INTERFACE:
+#  Inputs:  state<2>, radicand<8>, sqrtr<4>
+#  Outputs: fbit<1>
+#
+# NETLIST ANALYSIS:
+#
+#  Number of components: ........................ 72
+#  Number of primitives: ........................ 68
+#  Maximum primitive input bit width: ............ 6
+#  Average primitive input bit width: .......... 2.4
+#
+#  Number of inputs: ............................. 3
+#  Number of outputs: ............................ 1
+#  Number of input bits: ........................ 14
+#  Number of output bits: ........................ 1
+#
+#  Number of nets: .............................. 82
+#  Maximum number of fanout per net: ............ 16
+#  Average number of fanout per net: ........... 2.0
+#
+#  Number of instanciated modules: ............... 0
+#
+#  Primitives:
+#  Single output selector ....................... 16
+#  Register ..................................... 16
+#  Single output XOR gate ....................... 11
+#  Single output AND gate ....................... 10
+#  Single output NOT gate ........................ 9
+#  Single output  OR gate ........................ 6
+#
+#  Number of register bits: ..................... 16
+#  Number of constant bits: ...................... 0
+#
+#  Maximum selector total input bit width: ....... 6
+#  Average selector total input bit width: ..... 5.4
+#  Maximum selector input bit width: ............. 3
+#  Average selector input bit width: ........... 2.9
+#  Maximum selector selector bit width: .......... 3
+#  Average selector selector bit width: ........ 2.5
+
+.model sqrt8_PO_work
+.inputs _clk_
+.inputs state[1] state[0]
+.inputs radicand[7] radicand[6] radicand[5] radicand[4] radicand[3] radicand[2] radicand[1] radicand[0]
+.inputs sqrtr[3] sqrtr[2] sqrtr[1] sqrtr[0]
+.outputs fbit[0]
+.latch n11 n10 re _clk_ 0
+.latch n13 n12 re _clk_ 0
+.latch n15 n14 re _clk_ 0
+.latch n17 n16 re _clk_ 0
+.latch n19 n18 re _clk_ 0
+.latch n1B n1A re _clk_ 0
+.latch n1D n1C re _clk_ 0
+.latch n1F n1E re _clk_ 0
+.latch n1 n0 re _clk_ 0
+.latch n3 n2 re _clk_ 0
+.latch n5 n4 re _clk_ 0
+.latch n7 n6 re _clk_ 0
+.latch n9 n8 re _clk_ 0
+.latch nB nA re _clk_ 0
+.latch nD nC re _clk_ 0
+.latch nF nE re _clk_ 0
+.names fbit[0] n27
+0 1
+.names n0 n20
+0 1
+.names n28 n0 n21
+10 1
+01 1
+.names n28 n0 n29
+11 1
+.names n2 n29 n3D
+1- 1
+-1 1
+.names sqrtr[0] n2A
+0 1
+.names n4 n2A n2B
+10 1
+01 1
+.names n2B n3D n22
+10 1
+01 1
+.names n4 n2A n2C
+11 1
+.names n2B n3D n2D
+11 1
+.names n2C n2D n3E
+1- 1
+-1 1
+.names sqrtr[1] n2E
+0 1
+.names n6 n2E n2F
+10 1
+01 1
+.names n2F n3E n23
+10 1
+01 1
+.names n6 n2E n30
+11 1
+.names n2F n3E n31
+11 1
+.names n30 n31 n3F
+1- 1
+-1 1
+.names sqrtr[2] n32
+0 1
+.names n8 n32 n33
+10 1
+01 1
+.names n33 n3F n24
+10 1
+01 1
+.names n8 n32 n34
+11 1
+.names n33 n3F n35
+11 1
+.names n34 n35 n40
+1- 1
+-1 1
+.names sqrtr[3] n36
+0 1
+.names nA n36 n37
+10 1
+01 1
+.names n37 n40 n25
+10 1
+01 1
+.names nA n36 n38
+11 1
+.names n37 n40 n39
+11 1
+.names n38 n39 n41
+1- 1
+-1 1
+.names n3A n41 n26
+10 1
+01 1
+.names n3A n41 n3B
+11 1
+.names nC n3B n42
+1- 1
+-1 1
+.names n3C n42 fbit[0]
+10 1
+01 1
+.names state[0] state[1] n10 radicand[0] n11
+011- 1
+00-1 1
+11-1 1
+.names state[0] state[1] n12 radicand[1] n13
+011- 1
+00-1 1
+11-1 1
+.names state[0] state[1] n10 n14 radicand[2] n15
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names state[0] state[1] n12 n16 radicand[3] n17
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names state[0] state[1] n14 n18 radicand[4] n19
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names state[0] state[1] n16 n1A radicand[5] n1B
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names state[0] state[1] n18 n1C radicand[6] n1D
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names state[0] state[1] n1A n1E radicand[7] n1F
+101-- 1
+01-1- 1
+00--1 1
+11--1 1
+.names n27 state[0] state[1] n1C n0 n20 n1
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n1E n2 n21 n3
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n0 n4 n22 n5
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n2 n6 n23 n7
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n4 n8 n24 n9
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n6 nA n25 nB
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] n8 nC n26 nD
+-101-- 1
+001-1- 1
+101--1 1
+.names n27 state[0] state[1] nA fbit[0] nE nF
+-101-- 1
+101-1- 1
+001--1 1
+.names n2 n28
+0 1
+.names nC n3A
+0 1
+.names nE n3C
+0 1
+.end
+

data/test/test_blifutils.rb

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+#!/usr/bin/env ruby
+
+require 'blifutils'
+
+golden_model_names = [
+	"sqrt8", 
+	"sqrt8_PO", 
+	"sqrt8_PO_output", 
+	"sqrt8_PO_sqrtr", 
+	"sqrt8_PO_work", 
+	"sqrt8_PC", 
+	"sqrt8_PC_done", 
+	"sqrt8_PC_state", 
+	"sqrt8_PC_counter"
+]
+
+golden_model_analyze = {
+	name:      "sqrt8", 
+	nb_inputs:      10, 
+	nb_outputs:      5, 
+	is_blackbox: false, 
+	nb_nets:       115, 
+	nb_edges:      248, 
+	nb_nodes:      106, 
+	nb_latches:     29, 
+	nb_gates:       77, 
+	nb_subckt:       0, 
+	gates: {
+		gates_per_nb_inputs: {
+			4 => 13, 
+			1 => 19, 
+			2 => 30, 
+			5 =>  7, 
+			6 =>  8
+		}, 
+		nb_buffers:   5, 
+		nb_constants: 0
+	}
+}
+
+golden_level = 16
+
+
+input_file_name = File.join(File.dirname(File.expand_path(__FILE__)), 'sqrt8.blif')
+
+netlist = BlifUtils::read(input_file_name)
+
+model_names = netlist.models.collect{|model| model.name}
+abort "FAIL: Retreived models have different names" if model_names != golden_model_names
+
+sqrt8_flattened = netlist.flatten('sqrt8')
+
+analyze = sqrt8_flattened.analyze_to_hash
+analyze.each{|k, v| puts "#{k} -> #{v}"}
+abort "FAIL: Flattened model is different from the golden model" if analyze != golden_model_analyze
+
+level = sqrt8_flattened.level
+puts "Logic level: #{level}"
+abort "FAIL: logic level different from golden level" if level != golden_level
+
+netlist.clear.add_model(sqrt8_flattened).create_simulation_file_for_model('sqrt8')
+
+testbench_dir  = '.'
+testbench_src  = 'testbench_sqrt8.cc'
+testbench_obj  = 'sqrt8_cpp_sim.o'
+testbench_exec = 'sqrt8_cpp_sim'
+
+cmd = "g++ -W -Wall -I#{testbench_dir} -o #{testbench_exec} #{testbench_src} #{testbench_obj}"
+puts "Executing: #{cmd}"
+res = system cmd
+abort "Cannot find g++" if res.nil?
+abort unless res
+
+puts "Executing: #{testbench_exec}"
+abort unless system "./#{testbench_exec}"
+
+puts
+puts 'TEST PASSED'
+

data/test/testbench_sqrt8.cc

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+#include <cmath>
+#include "sqrt8_cpp_header.hh"
+
+int main(void)
+{
+	uint64_t in, out, golden;
+	int iterations = 0, nb_errors = 0;
+
+	Sqrt8SimulationClass *dut = new Sqrt8SimulationClass();
+
+	dut->reset();
+
+	for (in = 0; in < 256; in++) {
+		iterations++;
+
+		dut->INPUT_VECTOR_radicand->setValue(in);
+		dut->INPUT_NET_go->setValue(1);
+		dut->cycle();
+		dut->INPUT_NET_go->setValue(0);
+		dut->cycle();
+
+		while (dut->OUTPUT_NET_done->getValue() != 1) {
+			dut->clock();
+			dut->propagate();
+		}
+
+		out = dut->OUTPUT_VECTOR_squareRoot->getValue(NULL);
+		golden = (int)sqrt(in);
+		if (out != golden) {
+			std::cerr << "sqrt(" << in << ") => " << out << " (should be " << golden << ")" << std::endl;
+			nb_errors += 1;
+		}
+		else
+			std::cout << "sqrt(" << in << ") = " << out << std::endl;
+	}
+
+	delete dut;
+
+	if (nb_errors > 0) {
+		std::cerr << "C++ simulation: FAILED: " << nb_errors << "/" << iterations << " errors (" << (float)nb_errors*100.0f/(float)iterations << std::endl;
+		return EXIT_FAILURE;
+	}
+
+	std::cout << "C++ simulation: PASSED" << std::endl;
+
+	return EXIT_SUCCESS;
+}
+

metadata

@@ -0,0 +1,102 @@
+--- !ruby/object:Gem::Specification
+name: blifutils
+version: !ruby/object:Gem::Version
+  version: 0.0.1
+platform: ruby
+authors:
+- Théotime Bollengier
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2017-11-26 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: rltk
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '3.0'
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 3.0.1
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '3.0'
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 3.0.1
+description: BlifUtils is a library to handle BLIF logic netlists in Ruby. It can
+  read and write files in the BLIF format, elaborate internal representations of the
+  netlists, analyze it, flattent modules, write the modules as VHDL entities, and
+  generate C++ code for fast simulation of the netlists.
+email: theotime.bollengier@gmail.com
+executables:
+- blifutils
+extensions: []
+extra_rdoc_files: []
+files:
+- LICENSE
+- README.md
+- bin/blifutils
+- examples/zpu/compile_zpu_program/Makefile
+- examples/zpu/compile_zpu_program/README.md
+- examples/zpu/compile_zpu_program/main.c
+- examples/zpu/simulate_zpu.rb
+- examples/zpu/testbench_zpu.cc
+- examples/zpu/zpu_helloworld.bin
+- examples/zpu/zpu_mem16.blif
+- examples/zpu/zpu_mem16.piccolo
+- lib/blifutils.rb
+- lib/blifutils/ast.rb
+- lib/blifutils/blif_to_vhdl.rb
+- lib/blifutils/elaborator.rb
+- lib/blifutils/layering.rb
+- lib/blifutils/level_analyzer.rb
+- lib/blifutils/lexer.rb
+- lib/blifutils/netlist.rb
+- lib/blifutils/parser.rb
+- lib/blifutils/simulator_generator.rb
+- share/blimulator_cpp_classes.cc
+- share/blimulator_cpp_classes.hh
+- test/sqrt8.blif
+- test/sqrt8.piccolo
+- test/sqrt8_PC.blif
+- test/sqrt8_PC_counter.blif
+- test/sqrt8_PC_done.blif
+- test/sqrt8_PC_state.blif
+- test/sqrt8_PO.blif
+- test/sqrt8_PO_output.blif
+- test/sqrt8_PO_sqrtr.blif
+- test/sqrt8_PO_work.blif
+- test/test_blifutils.rb
+- test/testbench_sqrt8.cc
+homepage: http://github.com/TheotimeBollengier/blifutils
+licenses:
+- GPL-3.0
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubyforge_project: 
+rubygems_version: 2.6.12
+signing_key: 
+specification_version: 4
+summary: BlifUtils is a library to handle BLIF netlists in Ruby.
+test_files: []