badline 0.5.0 → 0.6.0

data/lib/badline/snapshot/vice/c64_mem.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # C64MEM 0.1: the CPU port, the cartridge's EXROM and GAME lines, and
+      # the 64K of RAM. The lines are written inactive, to match the empty
+      # cartridge port the snapshot shows VICE, and aren't read: badline
+      # takes them from its own cartridge.
+      #
+      # The floating port bits 6 and 7 carry their charge both ways. VICE's
+      # clocks for when the charge drains are written as zero and not read:
+      # the charge lasts as long as badline holds it.
+      module C64Mem
+        NAME = "C64MEM"
+        MAJOR = 0
+        MINOR = 1
+        FLOATING = [0x40, 0x80].freeze
+
+        module_function
+
+        def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+        def export(computer)
+          bus = computer.address_bus
+          ddr, port_out, floating = bus.port_state
+          fields = FieldWriter.new.byte(port_out).byte(ddr).byte(0).byte(0)
+          fields.bytes(Array.new(0x10000) { |addr| computer.ram.peek(addr) })
+          fields.byte((port_out & ddr) | (floating & ~ddr)).byte(bus.peek(1)).byte(ddr)
+          fields.dword(0).dword(0)
+          charged = FLOATING.map { |bit| floating.anybits?(bit) }
+          draining = FLOATING.map { |bit| floating.anybits?(bit) && ddr.nobits?(bit) }
+          (charged + draining).each { |set| fields.flag(set) }
+          fields.section(NAME, MAJOR, MINOR)
+        end
+
+        # The port is set without a bus write, which would leave the VIC's
+        # phi1 byte in the RAM under $00 and $01.
+        def import(section, computer)
+          fields = FieldReader.new(section)
+          data = fields.byte
+          ddr = fields.byte
+          fields.skip(2) # EXROM and GAME
+          computer.ram.write(0, fields.bytes(0x10000))
+          fields.skip(3 + 8)
+          charge = FLOATING.sum { |bit| fields.flag? ? bit : 0 }
+          driven = ddr & AddressBus::PORT_FLOATING
+          computer.address_bus.restore_port(ddr, data, (data & driven) | (charge & ~driven & 0xff))
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/cias.rb

@@ -0,0 +1,89 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # CIA1 and CIA2 2.3: the registers, both timers' counters and
+      # latches, the interrupt flags and mask, the TOD clock, its alarm and
+      # latch, and the shift register.
+      #
+      # Each timer's VICE state word carries its start, one-shot and input
+      # bits and whether its count pipeline is full, which is what badline's
+      # pipeline holds between loads. A load or one-shot stop in flight,
+      # the TOD divider's phase within a tenth and the shift register's
+      # progress through a byte are approximations both ways.
+      module CIAs
+        MAJOR = 2
+        MINOR = 3
+        NAMES = %w[CIA1 CIA2].freeze
+
+        # VICE's timer state bits.
+        START = 0x001
+        COUNT2 = 0x002
+        ONESHOT = 0x008
+        PHI2IN = 0x020
+        COUNT3 = 0x040
+        COUNT = 0x800
+
+        module_function
+
+        def export(computer)
+          [computer.cia1, computer.cia2].each_with_index.map do |cia, i|
+            fields = FieldWriter.new
+            registers(cia, fields)
+            time_of_day(cia.time_of_day, fields)
+            internals(cia, fields)
+            fields.section(NAMES[i], MAJOR, MINOR)
+          end
+        end
+
+        def registers(cia, fields)
+          cia.port_registers.each { |value| fields.byte(value) }
+          fields.word(cia.timer_a).word(cia.timer_b)
+          cia.time_of_day.registers.first(4).each { |value| fields.byte(value) }
+          fields.byte(cia.serial.data).byte(cia.interrupt_control.value)
+          fields.byte(cia.control_a.value).byte(cia.control_b.value)
+          fields.word(cia.timer_a_latch).word(cia.timer_b_latch).byte(cia.interrupt_status.value)
+          ta, tb = cia.timers
+          fields.byte((ta.toggle ? 0x40 : 0) | (tb.toggle ? 0x80 : 0) |
+                      (ta.underflowed ? 0x04 : 0) | (tb.underflowed ? 0x08 : 0))
+          fields.byte(cia.serial.steps.clamp(0, 0xff))
+        end
+
+        def time_of_day(tod, fields)
+          registers = tod.registers
+          registers[4, 4].each { |value| fields.byte(value) }
+          fields.byte(0) # cycles since the ICR was read
+          fields.byte(registers[9] | (registers[8] << 1)) # latched, stopped
+          tod.latched_fields.each { |value| fields.byte(value) }
+          fields.qword(tod.cycles_to_tenth)
+        end
+
+        def internals(cia, fields)
+          cia.timers.each { |timer| fields.word(timer_state(timer)) }
+          serial = cia.serial
+          shift = serial.shift_register
+          fields.byte(shift & 0xff).flag(!serial.pending.nil?).flag(cia.interrupted?)
+          fields.byte(cia.time_of_day.pulses)
+          fields.byte(shift >> 8).byte(0)
+          fields.byte((serial.sp_in ? 0x80 : 0) | (serial.cnt_in ? 0x40 : 0))
+        end
+
+        def timer_state(timer)
+          control = timer.control.value
+          pipe = timer.pipe
+          (control & (START | ONESHOT)) | (control.nobits?(0x60) ? PHI2IN : 0) |
+            (pipe.anybits?(0b10) ? COUNT2 : 0) | (pipe.anybits?(0b01) ? COUNT3 | COUNT : 0)
+        end
+
+        # Later minor versions add fields at the end.
+        def reads?(section) = section.major == MAJOR && section.minor >= MINOR
+
+        def import(section, computer)
+          cia = section.name == NAMES.first ? computer.cia1 : computer.cia2
+          Import.new(FieldReader.new(section)).apply(cia)
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/cias_import.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      module CIAs
+        # Reads a CIA module and puts it into one of badline's CIAs.
+        class Import
+          def initialize(fields)
+            @fields = fields
+            f = fields
+            @ports = f.bytes(4)
+            @counters = [f.word, f.word]
+            @clock = f.bytes(4)
+            @sdr, @mask, @control_a, @control_b = f.bytes(4)
+            @latches = [f.word, f.word]
+            @status, @toggles = f.bytes(2)
+            read_time_of_day
+            read_internals
+          end
+
+          def apply(cia)
+            @ports.each_with_index { |value, port| cia.poke(cia.start + port, value) }
+            cia.timer_a, cia.timer_b = @counters
+            cia.timer_a_latch, cia.timer_b_latch = @latches
+            cia.interrupt_control.value = @mask & 0x1f
+            cia.interrupt_status.value = @status
+            cia.serial.restore_shift(@sdr, @shift)
+            load_timers(cia)
+            cia.time_of_day.fifty_hz = @control_a.anybits?(0x80)
+            cia.time_of_day.restore_fields(@clock, @alarm, @latch)
+            cia.time_of_day.restore_divider(@stopped, @pulses, @ticks)
+          end
+
+          private
+
+          def read_time_of_day
+            f = @fields
+            f.skip(1) # the shift register's half-bits
+            @alarm = f.bytes(4)
+            f.skip(1) # cycles since the ICR was read
+            state = f.byte
+            @stopped = state.anybits?(2)
+            latch = f.bytes(4)
+            @latch = state.anybits?(1) ? latch : nil
+            @ticks = f.qword
+          end
+
+          def read_internals
+            f = @fields
+            @states = [f.word, f.word]
+            @shift = f.byte
+            f.skip(2) # whether the SDR holds a byte to send, the IRQ line
+            @pulses = f.byte.clamp(0, 5)
+          end
+
+          # Each timer takes its control register without the load strobe,
+          # its output toggle, and whether its count pipeline is full.
+          def load_timers(cia)
+            [@control_a, @control_b].zip(cia.timers).each_with_index do |(control, timer), i|
+              state = @states[i]
+              pipe = (state.anybits?(COUNT2) ? 0b10 : 0) | (state.anybits?(COUNT3) ? 0b01 : 0)
+              timer.restore_pipeline(control, @toggles.anybits?(0x40 << i), pipe)
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/main_cpu.rb

@@ -0,0 +1,76 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # The 6510 as x64sc saves it: MAINCPU 1.4 from VICE 3.8 on, 1.2
+      # before, and MAINC64CPU 1.5, the same fields under a new name, in
+      # VICE's development versions. The clock, the registers, the last
+      # opcode, the ANE and LXA log levels, whether the CPU is jammed and the
+      # BA low flags, then the interrupt bookkeeping: the IRQ, NMI and
+      # pending-IRQ clocks, the stolen cycles and when they were stolen, the
+      # IRQ and NMI source counts, the pending interrupts and the IRQ and NMI
+      # delays. 1.2 lacks the log levels and the jammed flag.
+      #
+      # Written: the registers as they stand, which between instructions is
+      # the whole CPU. VICE's interrupt clocks and delays are written as long
+      # past, with the IRQ and NMI source counts and a pending NMI.
+      #
+      # Read: the clock and the registers. The CPU starts on an instruction
+      # boundary, as VICE's snapshot is taken on one, and a pending NMI is
+      # taken there.
+      module MainCPU
+        NAME = "MAINCPU"
+        TRUNK_NAME = "MAINC64CPU"
+        MAJOR = 1
+        MINOR = 4
+        # The versions read, by name, and whether each has the log levels
+        # and the jammed flag.
+        VERSIONS = { "MAINCPU 1.2" => false, "MAINCPU 1.4" => true, "MAINC64CPU 1.5" => true }.freeze
+        IK_NMI = 0x01
+        IK_IRQ = 0x02
+
+        module_function
+
+        def export(computer)
+          cpu = computer.cpu
+          fields = FieldWriter.new.qword(computer.cycles)
+          [cpu.a, cpu.x, cpu.y, cpu.stack_pointer].each { |register| fields.byte(register) }
+          fields.word(cpu.program_counter).byte(cpu.p)
+          fields.dword(0).dword(0).dword(0).dword(cpu.jammed? ? 1 : 0).dword(0)
+          5.times { fields.qword(0) }
+          interrupts(computer, fields)
+          fields.qword(0).qword(0)
+          fields.section(NAME, MAJOR, MINOR)
+        end
+
+        def interrupts(computer, fields)
+          irqs = [computer.vic.interrupted?, computer.cia1.interrupted?].count(true)
+          nmis = computer.cia2.interrupted? ? 1 : 0
+          pending = (irqs.positive? ? IK_IRQ : 0) | (computer.cpu.nmi ? IK_NMI : 0)
+          fields.dword(irqs).dword(nmis).dword(pending)
+        end
+
+        # The module a snapshot has, under either name.
+        def find(container) = container[NAME] || container[TRUNK_NAME]
+
+        def reads?(section) = VERSIONS.key?(section.to_s)
+
+        def import(section, computer)
+          fields = FieldReader.new(section)
+          clock = fields.qword
+          cpu = computer.cpu
+          cpu.a, cpu.x, cpu.y, cpu.stack_pointer = Array.new(4) { fields.byte }
+          cpu.program_counter = fields.word
+          cpu.p = fields.byte
+          fields.skip(VERSIONS.fetch(section.to_s) ? 20 : 8)
+          fields.skip(40 + 8)
+          pending = fields.dword
+          cpu.resume(clock)
+          cpu.nmi = pending.anybits?(IK_NMI)
+          computer.resume_at(clock)
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/peripherals.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # The modules x64sc refuses a snapshot without, for the parts badline
+      # doesn't model in VICE's terms: the cartridge port, the file system
+      # drives, the glue logic, memory expansions, the tape port, the
+      # control ports and the user port. Each is written as a machine with
+      # nothing attached leaves it, with the joysticks released and the
+      # glue logic's VIC bank taken from CIA 2. A cartridge or tape badline
+      # has attached is carried by the BADLINE module only.
+      module Peripherals
+        # The glue logic's VIC bank, and its pending bank change.
+        GLUE = "GLUE"
+
+        FIXED = [
+          ["C64CART", 0, 1, [0x00]], # no cartridge
+          ["FSDRIVE", 0, 0, Array.new(258, 0)] # no file system drive open
+        ].freeze
+
+        AFTER_VIC = [
+          ["C64MEMHACKS", 0, 0, [0x00]], # no memory expansion hack
+          ["TAPEPORT", 1, 0, [0x01, 0x01]], # tape port on, datasette in it
+          ["JOYPORT0", 0, 0, [0x01]], ["JOYSTICK0", 1, 2, [0x00, 0x00]], # joysticks, released
+          ["JOYPORT1", 0, 0, [0x01]], ["JOYSTICK1", 1, 2, [0x00, 0x00]],
+          ["USERPORT", 1, 0, [0x01, 0x00]] # user port on, nothing in it
+        ].freeze
+
+        module_function
+
+        def cartridge_port = section(*FIXED[0])
+
+        def drives = section(*FIXED[1])
+
+        def glue(computer)
+          bank = ~computer.cia2.port_a_lines & 0x03
+          FieldWriter.new.byte(0).byte(bank).byte(0).section(GLUE, 1, 0)
+        end
+
+        def rest = AFTER_VIC.map { |entry| section(*entry) }
+
+        def section(name, major, minor, bytes) = FieldWriter.new.bytes(bytes).section(name, major, minor)
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/restore.rb

@@ -0,0 +1,125 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # Restores a machine from a snapshot VICE wrote, through the modules
+      # badline reads.
+      module Restore
+        # The modules badline reads, in the order it applies them: the VIC
+        # comes last, as it is clocked to its cycle through memory and CIA 2.
+        # MAINCPU and C64MEM hold the machine itself, so a version badline
+        # doesn't read fails the restore; the others are left out and
+        # reported.
+        READ = [MainCPU::NAME, C64Mem::NAME, "CIA1", "CIA2", SIDRegisters::NAME, SIDExtended::NAME,
+                VICII::NAME].freeze
+        REQUIRED = [MainCPU::NAME, C64Mem::NAME].freeze
+
+        module_function
+
+        # Applies the modules badline reads to `computer`, and returns a
+        # Report naming what it applied and, with a reason, what it left out.
+        # The snapshot goes into a new machine first, so one that fails leaves
+        # `computer` as it was, and one of a machine built another way fails
+        # too. Then the machine is taken to power-on with its cartridge out,
+        # so nothing it was doing carries into the snapshot's machine.
+        def import(container, computer)
+          setup = Vice.setup(container)
+          ours = Setup.of(computer.address_bus)
+          raise FormatError, "the snapshot is of a machine with #{setup}, not #{ours}" unless setup == ours
+
+          apply(container, setup.build)
+          prepare(computer)
+          report = apply(container, computer)
+          Report.new(applied: report.applied, ignored: report.ignored + drives(computer))
+        end
+
+        # Applies the modules badline reads to a machine built as the
+        # snapshot's was (setup), and returns the Report.
+        def apply(container, computer)
+          applied = []
+          ignored = []
+          READ.each do |name|
+            section = find(name, container)
+            next unless section
+
+            reason = refusal(name, section, container)
+            if reason
+              ignored << "#{section}: #{reason}, left out"
+            else
+              import_module(name, section, computer)
+              applied << section.name
+            end
+          end
+          Report.new(applied:, ignored: ignored + left_out(container, applied))
+        end
+
+        # The module a snapshot has for one badline reads, under any of its
+        # names.
+        def find(name, container)
+          case name
+          when MainCPU::NAME then MainCPU.find(container)
+          when VICII::NAME then VICII.find(container)
+          else container[name]
+          end
+        end
+
+        def prepare(computer)
+          computer.address_bus.detach_cartridge if computer.address_bus.cartridge
+          computer.power_cycle!
+        end
+
+        # Why badline leaves the module out, or nil when it reads it.
+        def refusal(name, section, container)
+          reason = if !reads?(name, section) then "badline doesn't read this version"
+                   elsif name == SIDExtended::NAME && !resid?(container) then "another SID engine wrote it"
+                   end
+          raise FormatError, "#{section}: #{reason}" if reason && REQUIRED.include?(name)
+
+          reason
+        end
+
+        def reads?(name, section)
+          case name
+          when MainCPU::NAME then MainCPU.reads?(section)
+          when C64Mem::NAME then C64Mem.reads?(section)
+          when SIDRegisters::NAME then SIDRegisters.reads?(section)
+          when SIDExtended::NAME then SIDExtended.reads?(section)
+          when VICII::NAME then VICII.reads?(section)
+          else CIAs.reads?(section)
+          end
+        end
+
+        def import_module(name, section, computer)
+          case name
+          when MainCPU::NAME then MainCPU.import(section, computer)
+          when C64Mem::NAME then C64Mem.import(section, computer)
+          when SIDRegisters::NAME then SIDRegisters.import(section, computer)
+          when SIDExtended::NAME then SIDExtended.import(section, computer)
+          when VICII::NAME then VICII.import(section, computer)
+          else CIAs.import(section, computer)
+          end
+        end
+
+        # SIDEXTENDED holds the engine's own state, and badline reads reSID's.
+        def resid?(container)
+          sid = container[SIDRegisters::NAME]
+          !sid.nil? && SIDRegisters.engine(sid) == SIDRegisters::RESID
+        end
+
+        def left_out(container, applied)
+          read = READ + [MainCPU::TRUNK_NAME, VICII::TRUNK_NAME]
+          container.sections.reject { |section| applied.include?(section.name) || read.include?(section.name) }
+                   .map { |section| "#{section}: badline doesn't read this module, left out" }
+        end
+
+        def drives(computer)
+          lines = []
+          lines << "the disk mounted in device 8 stays mounted" if computer.mounted?
+          lines << "the 1541 stays on the serial bus, reset" if computer.drive1541
+          lines
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/sid_extended.rb

@@ -0,0 +1,96 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # SIDEXTENDED 1.4 for the reSID engine: the state reSID keeps between
+      # cycles, voice by voice. badline's SID follows reSID's model, so its
+      # oscillators, noise registers and envelopes map across field by
+      # field. x64sc won't load a snapshot without this module when it runs
+      # reSID. A module another engine wrote has another layout, and isn't
+      # read.
+      #
+      # After the 32 registers, the data bus byte and its countdown, each
+      # field is written for the three voices in turn: the phase, the noise
+      # register, the envelope's rate and exponential counters, its level,
+      # state and hold-at-zero flag, its rate and exponential periods and
+      # pipeline, then the noise register's shift pipeline and reset
+      # countdown, the floating output's countdown and the pulse level. The
+      # voice mask and two bytes before it end the module.
+      module SIDExtended
+        NAME = "SIDEXTENDED"
+        MAJOR = 1
+        MINOR = 4
+        WAVEFORM_FIELDS = 6
+        ENVELOPE_FIELDS = 8
+        # What VICE's own snapshots carry for reSID's voice mask.
+        VOICE_MASK = 0xf7
+
+        # Each field's width, and where it sits among a voice's oscillator
+        # fields (Waveform#resid_fields, :waveform) or envelope fields
+        # (Envelope#resid_fields, :envelope).
+        FIELDS = [
+          [:dword, :waveform, 0], [:dword, :waveform, 1], [:word, :envelope, 0], [:word, :envelope, 1],
+          [:byte, :envelope, 2], [:byte, :envelope, 3], [:byte, :envelope, 4], [:word, :envelope, 5],
+          [:word, :envelope, 6], [:byte, :envelope, 7], [:byte, :waveform, 2], [:dword, :waveform, 3],
+          [:dword, :waveform, 4], [:word, :waveform, 5]
+        ].freeze
+
+        module_function
+
+        def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+        # `computer`'s SID must have caught up.
+        def export(computer)
+          sid = computer.sid
+          fields = FieldWriter.new.bytes(Array.new(0x20) { |reg| sid.register(reg) })
+          value, ttl = sid.bus_state
+          fields.byte(value).dword(ttl)
+          voices = sid.voices.map { |voice| [voice.waveform.resid_fields, voice.envelope.resid_fields] }
+          FIELDS.each do |width, part, index|
+            voices.each { |waveform, envelope| write(fields, width, (part == :waveform ? waveform : envelope)[index]) }
+          end
+          fields.byte(0).byte(0).byte(VOICE_MASK).section(NAME, MAJOR, MINOR)
+        end
+
+        def write(fields, width, value)
+          case width
+          when :byte then fields.byte(value)
+          when :word then fields.word(value)
+          else fields.dword(value)
+          end
+        end
+
+        def import(section, computer)
+          sid = computer.sid
+          voices = sid.voices
+          fields = FieldReader.new(section).skip(0x20)
+          sid.restore_bus(fields.byte, fields.dword)
+          waveforms = Array.new(voices.length * WAVEFORM_FIELDS, 0)
+          envelopes = Array.new(voices.length * ENVELOPE_FIELDS, 0)
+          FIELDS.each do |width, part, index|
+            voices.length.times do |n|
+              if part == :waveform
+                waveforms[(n * WAVEFORM_FIELDS) + index] = value(fields, width)
+              else
+                envelopes[(n * ENVELOPE_FIELDS) + index] = value(fields, width)
+              end
+            end
+          end
+          voices.each_with_index do |voice, n|
+            voice.waveform.restore_resid_fields(waveforms, n * WAVEFORM_FIELDS)
+            voice.envelope.restore_resid_fields(envelopes, n * ENVELOPE_FIELDS)
+          end
+        end
+
+        def value(fields, width)
+          case width
+          when :byte then fields.byte
+          when :word then fields.word
+          else fields.dword
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/sid_registers.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # SID 1.5, the module every VICE SID engine writes: the number of
+      # extra SIDs, whether sound is on, the engine, the model and the 32
+      # registers as last written. The engine's own state goes in
+      # SIDEXTENDED, which is reSID's and badline doesn't read.
+      #
+      # Read: the registers are written to the SID in order, so the voices
+      # start again from the gates as they stand, with their envelopes and
+      # oscillators from zero.
+      module SIDRegisters
+        NAME = "SID"
+        MAJOR = 1
+        MINOR = 5
+        RESID = 1
+        MODELS = %i[mos6581 mos8580].freeze
+
+        module_function
+
+        def export(computer)
+          sid = computer.sid
+          fields = FieldWriter.new.byte(0).byte(1).byte(RESID).byte(MODELS.index(sid.model))
+          fields.bytes(Array.new(0x20) { |reg| sid.register(reg) })
+          fields.section(NAME, MAJOR, MINOR)
+        end
+
+        # 1.4 added the registers as last written, which badline reads.
+        def reads?(section) = section.major == MAJOR && section.minor >= 4
+
+        def engine(section) = FieldReader.new(section).skip(2).byte
+
+        def model(section)
+          MODELS.fetch(FieldReader.new(section).skip(3).byte, :mos6581)
+        end
+
+        def import(section, computer)
+          registers = FieldReader.new(section).skip(4).bytes(0x20)
+          registers.first(0x19).each_with_index { |value, reg| computer.sid.poke(0xd400 + reg, value) }
+        end
+      end
+    end
+  end
+end