badline 0.5.0 → 0.6.0

data/lib/badline/cartridge/retro_replay.rb

@@ -2,6 +2,44 @@
 
 module Badline
   class Cartridge
+    # A Retro Replay's registers, RAM and flash, for a snapshot.
+    module RetroReplayState
+      private
+
+      def save_jumpers(out)
+        out.boolean(true).boolean(@flash_jumper).boolean(@bank_jumper)
+      end
+
+      def save_mapper(out)
+        [@active, @frozen, @phi1_ultimax, @ram_enabled, @ram_at_a000, @allow_bank, @no_freeze, @reu_mapping,
+         @write_once].each { |flag| out.boolean(flag) }
+        out.int(@bank).int(RetroReplay::CONTROL_MODES.index(@config))
+        @ram_data.each { |data| out.blob(data) }
+        @flash.save_state(out)
+      end
+
+      def load_mapper(input)
+        load_flags(input)
+        @bank = input.int
+        @config = RetroReplay::CONTROL_MODES.fetch(input.int)
+        @ram_data.each { |data| input.blob_into(data) }
+        @flash.load_state(input)
+        map_windows
+      end
+
+      def load_flags(input)
+        @active = input.boolean?
+        @frozen = input.boolean?
+        @phi1_ultimax = input.boolean?
+        @ram_enabled = input.boolean?
+        @ram_at_a000 = input.boolean?
+        @allow_bank = input.boolean?
+        @no_freeze = input.boolean?
+        @reu_mapping = input.boolean?
+        @write_once = input.boolean?
+      end
+    end
+
     # Retro Replay: an Am29F010 flash chip of two 64K halves, each eight 8K
     # ROM banks, and four 8K RAM banks, with the Action Replay's register at
     # $DE00 and an extended one at $DE01. The Nordic Replay (subtype 1) adds
@@ -44,6 +82,7 @@ module Badline
     # the half in bit 5.
     class RetroReplay < Cartridge
       include Freezer
+      include RetroReplayState
 
       CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
       IO1_PAGE = 0x1e00
@@ -212,11 +251,15 @@ module Badline
       end
 
       def configure
+        map_windows
+        changed!
+      end
+
+      def map_windows
         self.mode = @config
         @rom = flash_window(@bank)
         @roml = roml_window
         @romh = romh_window
-        changed!
       end
 
       def roml_window

data/lib/badline/cartridge/rgcd.rb

@@ -28,6 +28,16 @@ module Badline
 
       private
 
+      def save_mapper(out)
+        save_windows(out, [*@banks, EMPTY_BANK])
+        out.boolean(@disabled)
+      end
+
+      def load_mapper(input)
+        load_windows(input, [*@banks, EMPTY_BANK])
+        @disabled = input.boolean?
+      end
+
       def select(value)
         value ^= 0x07 if @hucky
         if value.anybits?(0x08)

data/lib/badline/cartridge/super_games.rb

@@ -20,6 +20,16 @@ module Badline
 
       private
 
+      def save_mapper(out)
+        save_windows(out, [*@roml_banks, *@romh_banks, EMPTY_BANK])
+        out.boolean(@locked)
+      end
+
+      def load_mapper(input)
+        load_windows(input, [*@roml_banks, *@romh_banks, EMPTY_BANK])
+        @locked = input.boolean?
+      end
+
       def select(value)
         @roml = bank(@roml_banks, value & 0x03)
         @romh = bank(@romh_banks, value & 0x03)

data/lib/badline/cartridge/zaxxon.rb

@@ -31,6 +31,14 @@ module Badline
         def peek(addr)
           @bank.peek(addr)
         end
+
+        def save_state(out)
+          out.int([*@banks, EMPTY_BANK].index { |bank| bank.equal?(@bank) })
+        end
+
+        def load_state(input)
+          @bank = [*@banks, EMPTY_BANK].fetch(input.int)
+        end
       end
 
       def reset
@@ -39,6 +47,14 @@ module Badline
 
       private
 
+      def save_mapper(out)
+        @romh.save_state(out)
+      end
+
+      def load_mapper(input)
+        @romh.load_state(input)
+      end
+
       def install_chips(chips)
         roml, romh = banks_from(chips)
         @romh = High.new(romh)

data/lib/badline/cartridge.rb

@@ -69,9 +69,28 @@ module Badline
         end
         mapper.new(crt, **)
       end
+
+      # A cartridge built afresh from what save_setup wrote, before
+      # load_state puts its state in.
+      def from_setup(input)
+        return GeoRAM.new(size: input.int) if input.int == GEO_RAM_SETUP
+
+        crt = Storage::CRTFile.new(bytes: input.string)
+        return RetroReplay.new(crt, flash_jumper: input.boolean?, bank_jumper: input.boolean?) if input.boolean?
+
+        from_crt(crt)
+      end
     end
 
+    # What save_setup writes first: a cartridge from a CRT image, or a
+    # GEO-RAM.
+    CRT_SETUP = 0
+    GEO_RAM_SETUP = 1
+
+    # Keeps the image it was built from, so a snapshot's machine can build
+    # the same cartridge before the snapshot's state goes into it.
     def initialize(crt)
+      @crt = crt
       @name = crt.name
       @exrom = crt.exrom
       @game = crt.game
@@ -88,6 +107,31 @@ module Badline
       @on_change = block
     end
 
+    # What builds the same cartridge afresh (Cartridge.from_setup): the CRT
+    # image it was built from, and the jumpers of a mapper that has them.
+    def save_setup(out)
+      out.int(CRT_SETUP).string(Storage::CRTFile.encode(@crt))
+      save_jumpers(out)
+    end
+
+    # The lines, the pull on NMI, the button and the mapper's own state.
+    # Loading sets them without calling back into the machine, which maps
+    # the cartridge again afterwards.
+    def save_state(out)
+      out.marker("CARTRIDGE")
+      out.int(@exrom).int(@game).boolean(@nmi).boolean(@button == true)
+      save_mapper(out)
+    end
+
+    def load_state(input)
+      input.marker("CARTRIDGE")
+      @exrom = input.int
+      @game = input.int
+      @nmi = input.boolean?
+      @button = input.boolean?
+      load_mapper(input)
+    end
+
     # Called with the level of the cartridge's pull on the NMI line when it
     # changes. The line is wired-OR with CIA 2's.
     def on_nmi_change(&block)
@@ -142,6 +186,34 @@ module Badline
 
     private
 
+    def save_jumpers(out)
+      out.boolean(false)
+    end
+
+    def save_mapper(_out); end
+
+    def load_mapper(_input); end
+
+    # Where the ROML and ROMH windows point, as their places in `windows`,
+    # the banks and views the mapper picks them from, or -1 for none.
+    def save_windows(out, windows)
+      out.int(window_index(@roml, windows)).int(window_index(@romh, windows))
+    end
+
+    def load_windows(input, windows)
+      @roml = window_at(input.int, windows)
+      @romh = window_at(input.int, windows)
+    end
+
+    def window_index(window, windows)
+      return -1 if window.nil?
+
+      windows.index { |candidate| candidate.equal?(window) } ||
+        raise(ArgumentError, "#{self.class.name}: a window that isn't among its banks")
+    end
+
+    def window_at(index, windows) = index.negative? ? nil : windows.fetch(index)
+
     def nmi=(level)
       return if @nmi == level
 

data/lib/badline/cia/interrupt_register.rb

@@ -34,6 +34,23 @@ module Badline
 
       def interrupted? = status.value >= 0x80
 
+      def save_state(out)
+        out.int(@mask.value).int(@status.value).int(@pending)
+        [@read, @read_last_cycle, @read_two_cycles_ago].each { |read| out.optional_int(read) }
+        out.boolean(@timer_b_bug).boolean(@quiet)
+      end
+
+      def load_state(input)
+        @mask.value = input.int
+        @status.value = input.int
+        @pending = input.int
+        @read = input.optional_int
+        @read_last_cycle = input.optional_int
+        @read_two_cycles_ago = input.optional_int
+        @timer_b_bug = input.boolean?
+        @quiet = input.boolean?
+      end
+
       # Raises IR on this cycle.
       def assert_now
         status.interrupt = true

data/lib/badline/cia/serial.rb

@@ -62,6 +62,19 @@ module Badline
         @sp_out = true
       end
 
+      # The bits shifted so far, and the byte waiting to go out after the
+      # one shifting.
+      attr_reader :steps, :pending
+
+      def shift_register = @shift
+
+      # Sets the data register and the shift register, as a VICE snapshot
+      # gives them.
+      def restore_shift(data, shift)
+        @data = data
+        @shift = shift
+      end
+
       def output?
         @control.serial_mode?
       end
@@ -71,6 +84,25 @@ module Badline
         @cnt = level unless output?
       end
 
+      def save_state(out)
+        out.int(@data).int(@shift).int(@steps).optional_int(@empty_in).optional_int(@busy_in)
+        out.boolean(@busy).boolean(@abandoned).optional_int(@pending).boolean(@underflow_high).boolean(@in_flight)
+        out.int(@flight_up).int(@flight_down).boolean(@idle)
+        [@cnt, @cnt_in, @sp_in, @sp_out].each { |level| out.boolean(level) }
+      end
+
+      def load_state(input)
+        @data = input.int
+        @shift = input.int
+        @steps = input.int
+        @empty_in = input.optional_int
+        @busy_in = input.optional_int
+        @busy = input.boolean?
+        @abandoned = input.boolean?
+        @pending = input.optional_int
+        load_lines(input)
+      end
+
       def write(value)
         @data = value
         @pending = LOAD_DELAY
@@ -132,6 +164,18 @@ module Badline
 
       private
 
+      def load_lines(input)
+        @underflow_high = input.boolean?
+        @in_flight = input.boolean?
+        @flight_up = input.int
+        @flight_down = input.int
+        @idle = input.boolean?
+        @cnt = input.boolean?
+        @cnt_in = input.boolean?
+        @sp_in = input.boolean?
+        @sp_out = input.boolean?
+      end
+
       # Without an underflow, a register with nothing counting down and
       # nothing in the delay lines has nothing to do on a cycle.
       def idle?

data/lib/badline/cia/state.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    # A snapshot of the chip: everything it holds but its wiring, the ports,
+    # the PB4 and CNT levels, the timers, the interrupt register, the serial
+    # port and the TOD clock.
+    module State
+      def save_state(out)
+        out.marker("CIA")
+        out.int(@data_port_a).int(@data_port_b).int(@data_dir_a).int(@data_dir_b)
+        out.boolean(@port_b4_high).boolean(@port_b4_driven_high).boolean(@cnt_high).boolean(@cnt_rise)
+        out.int(@control_a.value).int(@control_b.value)
+        @ta.save_state(out)
+        @tb.save_state(out)
+        @icr.save_state(out)
+        @serial.save_state(out)
+        @tod.save_state(out)
+      end
+
+      def load_state(input)
+        input.marker("CIA")
+        @data_port_a = input.int
+        @data_port_b = input.int
+        @data_dir_a = input.int
+        @data_dir_b = input.int
+        @port_b4_high = input.boolean?
+        @port_b4_driven_high = input.boolean?
+        @cnt_high = input.boolean?
+        @cnt_rise = input.boolean?
+        @control_a.value = input.int
+        @control_b.value = input.int
+        load_parts(input)
+      end
+
+      private
+
+      def load_parts(input)
+        @ta.load_state(input)
+        @tb.load_state(input)
+        @icr.load_state(input)
+        @serial.load_state(input)
+        @tod.load_state(input)
+      end
+    end
+  end
+end

data/lib/badline/cia/timer.rb

@@ -42,6 +42,26 @@ module Badline
         settle
       end
 
+      # The counter, the latch and the pipeline between them. The control
+      # register is the CIA's to save.
+      def save_state(out)
+        out.int(@counter).int(@latch).int(@pipe).int(@load_delay).boolean(@reload).boolean(@underflowed)
+        out.int(@oneshot_linger).boolean(@toggle).boolean(@settled).boolean(@empty)
+      end
+
+      def load_state(input)
+        @counter = input.int
+        @latch = input.int
+        @pipe = input.int
+        @load_delay = input.int
+        @reload = input.boolean?
+        @underflowed = input.boolean?
+        @oneshot_linger = input.int
+        @toggle = input.boolean?
+        @settled = input.boolean?
+        @empty = input.boolean?
+      end
+
       def write_control(value)
         @toggle = true if value.anybits?(0x01) && !started?
         @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
@@ -59,6 +79,19 @@ module Badline
         @counter = @latch unless started?
       end
 
+      # Whether the timer's PB output toggle is high, and its count pipeline
+      # as two bits, the newer stage high.
+      attr_reader :toggle, :pipe
+
+      # Sets the control register without its load strobe, the toggle and
+      # the count pipeline, as a VICE snapshot gives them.
+      def restore_pipeline(control, toggle, pipe)
+        @control.value = control & ~0x10
+        @toggle = toggle
+        @pipe = pipe
+        settle
+      end
+
       private
 
       def started?

data/lib/badline/cia.rb

@@ -3,11 +3,13 @@
 require "badline/cia/interrupt_register"
 require "badline/cia/serial"
 require "badline/cia/timer"
+require "badline/cia/state"
 
 module Badline
   # CIA (Complex Interface Adapter) chip
   class CIA
     include Addressable
+    include State
 
     # The original NMOS 6526 of the breadbin C64, and the HMOS 6526A of the
     # C64C, which differs from it only in its interrupt control register.
@@ -19,6 +21,12 @@ module Badline
     # read_a and read_b, and on CIA 1 drives PB4 through port_b4_high?.
     attr_accessor :peripheral
 
+    # Timer A and timer B.
+    def timers = [@ta, @tb]
+
+    # Port A and B's data and direction registers.
+    def port_registers = [@data_port_a, @data_port_b, @data_dir_a, @data_dir_b]
+
     def interrupt_status = @icr.status
 
     def interrupt_control = @icr.mask
@@ -62,6 +70,7 @@ module Badline
 
       @peripheral = peripheral
       @port_b4_handler = nil
+      @port_a_handler = nil
       @port_b4_high = true
       reset!
     end
@@ -87,6 +96,7 @@ module Badline
       @ta = Timer.new(@control_a)
       @tb = Timer.new(@control_b)
       @serial = Serial.new(@control_a)
+      @port_a_handler&.call
     end
 
     # Register a change handler on the PB4 line. On CIA 1, this feeds the
@@ -95,6 +105,13 @@ module Badline
       @port_b4_handler = handler
     end
 
+    # Register a handler for writes that can move port A's lines: to the
+    # data register or DDR, and the reset. On CIA 2, this tells the drives
+    # on the serial bus that the C64 may have moved a line.
+    def on_port_a_write(&handler)
+      @port_a_handler = handler
+    end
+
     # A falling edge on the FLAG pin. On CIA 1 the datasette's tape read
     # line drives it, on CIA 2 the serial bus SRQ.
     def flag! = raise_interrupt(:flag)
@@ -153,9 +170,9 @@ module Badline
 
     def poke(addr, value)
       case offset_of(addr) & 0x0f
-      when 0x00 then @data_port_a = value
+      when 0x00 then update_port_a { @data_port_a = value }
       when 0x01 then update_port_b { @data_port_b = value }
-      when 0x02 then @data_dir_a = value
+      when 0x02 then update_port_a { @data_dir_a = value }
       when 0x03 then update_port_b { @data_dir_b = value }
       when 0x04 then @ta.write_latch_low(value)
       when 0x05 then @ta.write_latch_high(value)
@@ -174,6 +191,11 @@ module Badline
 
     private
 
+    def update_port_a
+      yield
+      @port_a_handler&.call
+    end
+
     def update_port_b
       yield
       @port_b4_driven_high = driven_lines(@data_port_b, @data_dir_b).anybits?(0x10)

data/lib/badline/computer/attachments.rb

@@ -0,0 +1,132 @@
+# frozen_string_literal: true
+
+module Badline
+  class Computer
+    # What plugs into the machine besides its chips, the cartridge, the
+    # disk device 8 serves through the traps, a true 1541 and an REU, and
+    # their state for a snapshot.
+    module Attachments
+      # Puts the cartridge in the expansion port and wires its clock and NMI
+      # line to the machine, leaving the machine's state as it is. A
+      # restored snapshot's cartridge comes back through here.
+      def connect_cartridge(cartridge)
+        cartridge.clock = -> { @cycles }
+        cartridge.on_nmi_change { |level| @cartridge_nmi = level }
+        address_bus.attach_cartridge(cartridge)
+      end
+
+      # Puts the storage in device 8. Mounting again swaps the disk at any
+      # point while the machine runs: the drive keeps its RAM, which only a
+      # drive reset clears, and its status.
+      def mount(storage)
+        return @drive.insert(storage) if @drive
+
+        @drive = KernalTrap::Drive.new(storage)
+        load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, drive: @drive)
+        cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
+        @serial_trap = KernalTrap::Serial.new(cpu:, bus: address_bus, drive: @drive, device: serial_trap_device).install
+        save_trap = @save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, drive: @drive)
+        cpu.install_trap(KernalTrap::Save::ADDRESS) { save_trap.call }
+      end
+
+      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
+      # serial traps, so the KERNAL's routines go out over the serial bus.
+      # Mounting again starts a new drive, with its RAM cleared.
+      def unmount
+        return unless @drive
+
+        cpu.remove_trap(KernalTrap::Load::ADDRESS)
+        cpu.remove_trap(KernalTrap::Save::ADDRESS)
+        @serial_trap.device = nil
+        @serial_trap = nil
+        @save_trap = nil
+        @drive = nil
+      end
+
+      # Whether device 8 serves a disk or directory through the traps.
+      def mounted? = !@drive.nil?
+
+      # Unplugs the Drive1541, leaving the serial bus with nothing on it.
+      def detach_drive1541
+        return unless @drive1541
+
+        @iec_bus&.detach(@drive1541)
+        @drive1541 = nil
+        @serial_trap&.device = serial_trap_device
+      end
+
+      private
+
+      def save_cartridge(out)
+        cartridge = address_bus.cartridge
+        out.boolean(!cartridge.nil?)
+        cartridge&.save_setup(out)
+      end
+
+      # A cartridge comes back built afresh from the setup it was built
+      # with, before the address bus puts its state into it.
+      def load_cartridge(input)
+        if input.boolean?
+          connect_cartridge(Cartridge.from_setup(input))
+        elsif address_bus.cartridge
+          address_bus.detach_cartridge
+        end
+      end
+
+      # The disk device 8 serves through the traps, with the traps' own
+      # state: open channels, the drive's status and RAM, a SAVE under way.
+      def save_trap_drive(out)
+        out.boolean(!@drive.nil?)
+        return unless @drive
+
+        @drive.save_state(out)
+        @serial_trap.save_state(out)
+        @save_trap.save_state(out)
+      end
+
+      def load_trap_drive(input)
+        return unmount unless input.boolean?
+
+        storage = Storage.reopen(input)
+        unmount
+        mount(storage)
+        @drive.load_state(input)
+        @serial_trap.load_state(input)
+        @save_trap.load_state(input)
+      end
+
+      # The serial bus, whose presence decides what CIA 2's port A reads,
+      # and a true 1541 on it.
+      def save_serial_bus(out)
+        out.boolean(!@iec_bus.nil?).boolean(!@drive1541.nil?)
+        return unless @drive1541
+
+        out.int(@drive1541.device)
+        @drive1541.save_state(out)
+      end
+
+      def load_serial_bus(input)
+        iec_bus if input.boolean?
+        return detach_drive1541 unless input.boolean?
+
+        device = input.int
+        detach_drive1541 if @drive1541 && @drive1541.device != device
+        attach_drive1541(Drive1541.new(device:)) unless @drive1541
+        @drive1541.load_state(input)
+      end
+
+      # The REU, which the setup says the machine has, and whether it has
+      # asked for the bus. Its IRQ line reaches the CPU as it was.
+      def save_reu(out)
+        @reu&.save_state(out)
+        out.boolean(@dma)
+      end
+
+      def load_reu(input)
+        @reu&.load_state(input)
+        @reu_irq = @reu ? @reu.irq? : false
+        @dma = input.boolean?
+      end
+    end
+  end
+end