badline 0.14.0 → 0.15.1

data/lib/badline/plus4/keyed_parts.rb

@@ -0,0 +1,172 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    class CPUPort
+      # The port's registers in a keyed snapshot module (Snapshot::Keyed),
+      # under `prefix`. The serial bus's lines and the datasette's write
+      # line are driven again from them once everything is loaded
+      # (#restored!), without recording an edge on the tape.
+      module KeyedState
+        def save_fields(out, prefix)
+          out.int("#{prefix}ddr", @ddr).int("#{prefix}data", @data)
+        end
+
+        def load_fields(input, prefix)
+          @ddr = input.byte("#{prefix}ddr", @ddr)
+          @data = input.byte("#{prefix}data", @data)
+        end
+
+        def restored!
+          @serial_bus.host_lines = serial_lines
+          @datasette.write_level = levels.anybits?(CLK_OUT)
+        end
+      end
+
+      include KeyedState
+    end
+
+    class KeyboardPort
+      # The 6529's latch in a keyed snapshot module (BL-KEYPORT).
+      module KeyedState
+        def save_fields(out) = out.int("output", @output)
+
+        def load_fields(input)
+          @output = input.byte("output", @output)
+        end
+      end
+
+      include KeyedState
+    end
+
+    class UserPort
+      # The 6529's latch in a keyed snapshot module (BL-USERPORT).
+      module KeyedState
+        def save_fields(out) = out.int("output", @output)
+
+        def load_fields(input)
+          @output = input.byte("output", @output)
+        end
+      end
+
+      include KeyedState
+    end
+
+    class ACIA
+      # The registers, the status, the shift register and when the
+      # transmitter's character ends, in a keyed snapshot module (BL-ACIA).
+      # What the device on the user port has still to send stays with the
+      # host, and the receiver starts on it again once loaded (#restored!).
+      # A snapshot from before the transmitter's timing was saved starts
+      # its character clock on load.
+      module KeyedState
+        def save_fields(out)
+          out.int("command", @command).int("control", @control).int("errors", @errors)
+          out.bool("receiver_full", @receiver_full).bool("transmitter_empty", @transmitter_empty).bool("irq", @irq)
+          out.int("receive_data", @receive_data).int("transmit_data", @transmit_data).int("shifting", @shifting)
+          out.int("transmit_at", @transmit_at).int("transmit_remainder", @transmit_remainder)
+        end
+
+        def load_fields(input)
+          @command = input.byte("command", @command)
+          @control = input.byte("control", @control)
+          @errors = input.masked("errors", 0, PARITY_ERROR | FRAMING_ERROR | OVERRUN)
+          @receiver_full = input.bool("receiver_full", false)
+          @transmitter_empty = input.bool("transmitter_empty", true)
+          @irq = input.bool("irq", false)
+          @receive_data = input.byte("receive_data", 0)
+          @transmit_data = input.byte("transmit_data", 0)
+          @shifting = input.int("shifting", IDLE)
+          @transmit_remainder = input.int("transmit_remainder", 0)
+          transmit_at = input.optional_int("transmit_at")
+          @transmit_at = transmit_at || NEVER
+          @clock_lost = transmit_at.nil?
+        end
+
+        def restored!
+          @receive_at = NEVER
+          @lines = modem_lines
+          start_transmitting if @clock_lost && transmitter_on?
+          @clock_lost = false
+          start_receiving
+          changed
+        end
+      end
+
+      include KeyedState
+    end
+
+    class Bus
+      # The ROM bank latch, whether ROM is selected and the last byte on the
+      # bus, under `prefix`, and the cartridges' ROMs by slot (#save_slot_fields),
+      # in keyed snapshot modules (Snapshot::Keyed). The TED learns which
+      # memory is selected, and the pages are mapped again, once they are
+      # loaded (#restored!). The BASIC, KERNAL and function ROMs come with
+      # the model.
+      module KeyedState
+        # The cartridge slots, as xplus4 names them: cartridge 1 or 2, the
+        # low ($8000) or the high ($C000) half.
+        SLOTS = %w[c1lo c2lo c1hi c2hi].freeze
+
+        def save_fields(out, prefix)
+          out.int("#{prefix}low_bank", @low_bank).int("#{prefix}high_bank", @high_bank)
+          out.bool("#{prefix}rom_selected", @rom_selected).int("#{prefix}data", @data)
+        end
+
+        def load_fields(input, prefix)
+          @low_bank = input.masked("#{prefix}low_bank", @low_bank, 0x03)
+          @high_bank = input.masked("#{prefix}high_bank", @high_bank, 0x03)
+          @rom_selected = input.bool("#{prefix}rom_selected", @rom_selected)
+          @data = input.byte("#{prefix}data", @data)
+        end
+
+        # Whether a cartridge's ROM is in any slot.
+        def cartridge?
+          index = 0
+          while index < SLOTS.length
+            return true unless slot_rom(index).nil?
+
+            index += 1
+          end
+          false
+        end
+
+        # Each slot's ROM, 16K, under its name. An empty slot writes
+        # nothing.
+        def save_slot_fields(out)
+          SLOTS.each_with_index do |name, index|
+            rom = slot_rom(index)
+            rom&.save_fields(out, name)
+          end
+          out
+        end
+
+        # A slot the module holds nothing for is left empty.
+        def load_slot_fields(input)
+          SLOTS.each_with_index do |name, index|
+            bytes = input.bytes(name, "".b).bytes
+            if index < 2
+              @low_roms[2 + index] = slot(bytes, 0x8000)
+            else
+              @high_roms[index] = slot(bytes, 0xc000)
+            end
+          end
+        end
+
+        def restored!
+          @ted.rom_selected = @rom_selected
+          map_ram
+        end
+
+        private
+
+        def slot_rom(index) = index < 2 ? @low_roms[2 + index] : @high_roms[index]
+
+        # A slot's ROM from its bytes at `start`, or none.
+        def slot(bytes, start) = bytes.empty? ? nil : ROM.new(bytes, length: bytes.length, start:)
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/plus4/keyed_state.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The machine's own fields in a keyed snapshot module (Snapshot::Keyed,
+    # BL-MACHINE): the family, its setup by name (Snapshot::Plus4Setup), the
+    # cycle count, and the host's typing still to feed and on_init handlers
+    # still to run under host.*. The badline version that wrote it is
+    # written for reports and never read.
+    module KeyedState
+      # How many more on_init handlers the machine a snapshot was taken of had
+      # yet to run than this one has. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      # Whether a snapshot saves now (Machine::Settling): the CPU between
+      # instructions or jammed.
+      def settled_for_snapshot? = @cpu.boundary? || @cpu.jammed?
+
+      # The sound's voices and the SID card's, run up to this cycle.
+      def settle_chips_for_snapshot
+        @sound.catch_up!
+        @sid_card&.catch_up!
+      end
+
+      def save_machine_fields(out)
+        out.text("family", "plus4").text("written_by", VERSION)
+        Snapshot::Plus4Setup.of(self).write_fields(out)
+        out.int("cycles", @cycles)
+        pending = @pending_keys
+        out.ints("host.pending_keys", pending) if pending
+        out.int("host.init_pending", booting? ? @init_handlers.length : 0)
+      end
+
+      def load_machine_fields(input)
+        @cycles = input.int("cycles", @cycles)
+        pending = input.ints("host.pending_keys", [])
+        @pending_keys = pending.empty? ? nil : pending.dup
+        @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+      end
+    end
+
+    include KeyedState
+  end
+end

data/lib/badline/plus4/ram_expansion.rb

@@ -0,0 +1,145 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # Hannes's RAM expansion, 256K or 1M in 64K banks, and Csory's 256K on
+    # the same board, from Solder's register notes and the board's GAL
+    # equations (plus4world, "256K RAM (Hannes)").
+    #
+    # The control register is a 6529 at $FD16, which reads back what was
+    # written. The expansion decodes $FD10-$FD1F further, so the user port
+    # answers only at $FD10, and the rest of the range is open.
+    #
+    # - Bits 0-1, and bits 2-3 on the 1M: the bank the CPU sees above the
+    #   switch bound. All ones is the standard bank, the RAM below the
+    #   bound, which bits 0-3 pick inverted: bank 3 of the 256K and bank
+    #   15 of the 1M.
+    # - Bit 6: the TED fetches from the CPU's bank when set, and from the
+    #   standard bank when clear.
+    # - Bit 7: the switch bound, $4000 when set, $1000 when clear.
+    # - Bits 4-5: on the Csory board, two different bits switch Csory's
+    #   mapping on (the notes' gate version; its table names 10 and its
+    #   GAL 01).
+    #
+    # The register is all ones at power-on and after a reset, so the
+    # machine starts in the standard bank, with the TED following it.
+    #
+    # Csory's mapping puts one 16K block of the 256K, picked by bits 0-3
+    # of a write-only latch at $FD15, in the 16K window of the CPU's 64K
+    # that bits 6-7 pick. The standard bank holds blocks 0-3. The TED sees
+    # the block too while bit 6 of $FD16 is set. On the Csory board the
+    # TED reads the KERNAL wherever it fetches from the high ROM, whichever
+    # bank the ROM latch selects.
+    class RAMExpansion
+      # Each expansion by name: its 64K banks, and whether it has Csory's
+      # mapping.
+      KINDS = { hannes256: [4, false], hannes1m: [16, false], csory256: [4, true] }.freeze
+
+      # Whose design each is, as the pause menu names it.
+      NAMES = { hannes256: "HANNES", hannes1m: "HANNES", csory256: "CSORY" }.freeze
+
+      CONTROL = 0x06
+      CSORY_LATCH = 0x05
+
+      # The register at $FD16, and Csory's latch at $FD15.
+      attr_reader :kind, :control, :csory_latch
+
+      # +ram+ is the machine's own 64K, the standard bank, and +view+ the
+      # Bus::MirroredRAM the bus reads it through.
+      def initialize(kind, ram, view)
+        @kind = kind
+        count, csory = KINDS.fetch(kind)
+        @csory = csory
+        @mask = count - 1
+        size = (count - 1) * 0x10000
+        @extra = Memory.new(Array.new(size, Bus::RAM_POWER_ON), length: size, start: 0)
+        @banks = [view] + Array.new(count - 1) { |index| Bus::MirroredRAM.new(@extra, 0xffff, index * 0x10000) }
+        @blocks = csory ? Array.new(16) { |block| block_view(ram, block) } : []
+        @control = 0xff
+        @csory_latch = 0
+      end
+
+      # The size in K.
+      def size_kb = (@mask + 1) * 64
+
+      # Whether the TED reads the KERNAL for the whole high ROM.
+      def kernal_for_ted? = @csory
+
+      # A write to $FD11-$FD1F: the control register at $FD16, and on the
+      # Csory board, Csory's latch at $FD15.
+      def poke(addr, value)
+        case addr & 0x0f
+        when CONTROL then @control = value
+        when CSORY_LATCH then @csory_latch = value if @csory
+        end
+      end
+
+      # The RESET line sets the register, as power-on does. Csory's latch
+      # keeps its value.
+      def reset!
+        @control = 0xff
+      end
+
+      def power_on!
+        @extra.clear!(Array.new(@extra.length, Bus::RAM_POWER_ON))
+        @csory_latch = 0
+        reset!
+      end
+
+      # Lays the RAM the CPU sees out in +cpu+ and the RAM the TED sees in
+      # +ted+, a view for each of the 256 pages.
+      def map(cpu, ted)
+        control = @control
+        bound = control.anybits?(0x80) ? 0x40 : 0x10
+        standard = @banks[0]
+        cpu.fill(standard, 0x00, bound)
+        cpu.fill(@banks[~control & @mask], bound, 0x100 - bound)
+        follows = control.anybits?(0x40)
+        if follows
+          page = 0
+          while page < 0x100
+            ted[page] = cpu[page]
+            page += 1
+          end
+        else
+          ted.fill(standard, 0x00, 0x100)
+        end
+        return unless csory_on?
+
+        latch = @csory_latch
+        block = @blocks[latch & 0x0f]
+        window = (latch >> 6) * 0x40
+        cpu.fill(block, window, 0x40)
+        ted.fill(block, window, 0x40) if follows
+      end
+
+      # The banks beyond the standard one, and Csory's latch, in a keyed
+      # snapshot module (BL-RAMEXP).
+      def save_fields(out)
+        out.int("control", @control)
+        out.int("csory_latch", @csory_latch) if @csory
+        @extra.save_fields(out, "ram")
+      end
+
+      def load_fields(input)
+        @control = input.byte("control", @control)
+        @csory_latch = input.byte("csory_latch", @csory_latch)
+        @extra.load_fields(input, "ram")
+      end
+
+      private
+
+      def csory_on?
+        control = @control
+        @csory && control.anybits?(0x10) != control.anybits?(0x20)
+      end
+
+      # Block +block+ of the 256K, from the standard bank's four on.
+      def block_view(ram, block)
+        return Bus::MirroredRAM.new(ram, 0x3fff, block * 0x4000) if block < 4
+
+        Bus::MirroredRAM.new(@extra, 0x3fff, (block - 4) * 0x4000)
+      end
+    end
+  end
+end

data/lib/badline/plus4/sid_card.rb

@@ -0,0 +1,95 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # A SID card's SID at $FD40-$FD5F, or at $FE80-$FE9F as Csory's card
+    # puts it, clocked once a TED cycle, as the cards clock it from the
+    # TED's single clock. The SID counts the
+    # cycles that have passed whenever something touches it, rather than
+    # every cycle: a CPU access runs it through the cycle the access is in,
+    # and the host, between cycles, up to the cycle about to start.
+    # `clock` answers the machine's cycles.
+    class SIDCard
+      # Where a card can put its SID.
+      ADDRESSES = [0xfd40, 0xfe80].freeze
+
+      attr_reader :sid, :address
+
+      def initialize(clock, model, address = ADDRESSES.first)
+        raise ArgumentError, format("no SID card at $%04X", address) unless ADDRESSES.include?(address)
+
+        @clock = clock
+        @address = address
+        @sid = Chips::SID.new(model:, at: address)
+        @clocked = 0
+      end
+
+      def model = @sid.model
+
+      def model=(model)
+        catch_up!
+        @sid.model = model
+      end
+
+      def peek(addr)
+        run_to(@clock.cycles + 1)
+        @sid.peek(addr)
+      end
+
+      def poke(addr, value)
+        run_to(@clock.cycles + 1)
+        @sid.poke(addr, value)
+      end
+
+      # The RES line, from the host between cycles.
+      def reset!
+        run_to(@clock.cycles)
+        @sid.reset!
+      end
+
+      # Runs the SID, its voices and its filter, up to the current cycle.
+      def catch_up!
+        run_to(@clock.cycles)
+        @sid.catch_up!
+      end
+
+      def record(rate:, clock_hz:)
+        run_to(@clock.cycles)
+        @sid.record(rate:, clock_hz:)
+      end
+
+      def drain_samples
+        run_to(@clock.cycles)
+        @sid.drain_samples
+      end
+
+      # The SID's fields in a keyed snapshot module (BL-SID), saved once the
+      # machine has settled it (#catch_up!).
+      def save_fields(out) = @sid.save_fields(out)
+
+      def load_fields(input)
+        @sid.load_fields(input)
+      end
+
+      # The SID counts on from the machine's cycle the snapshot was taken at.
+      def restored!
+        @sid.restored!
+        @clocked = @clock.cycles
+      end
+
+      private
+
+      def run_to(target)
+        clocked = @clocked
+        return if clocked >= target
+
+        sid = @sid
+        while clocked < target
+          sid.cycle!
+          clocked += 1
+        end
+        @clocked = clocked
+      end
+    end
+  end
+end

data/lib/badline/plus4/sound_mix.rb

@@ -0,0 +1,51 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # What a front end plays from a 264 with a SID card fitted: the TED's
+    # sound and the card's SID, each recorded at the audio rate and added
+    # together, clipped to a signed 16-bit sample. A sample one source has
+    # closed waits for the other's. The SID's model is the mix's, as it
+    # is a C64's sound source's, for the pause menu's Sound page.
+    class SoundMix
+      def initialize(ted_sound, sid)
+        @ted_sound = ted_sound
+        @sid = sid
+        @ted_waiting = []
+        @sid_waiting = []
+      end
+
+      def model = @sid.model
+
+      def model=(model)
+        @sid.model = model
+      end
+
+      # Starts both sources recording at `rate` samples a second, their
+      # cycles taken to run at `clock_hz`.
+      def record(rate:, clock_hz:)
+        @ted_sound.record(rate:, clock_hz:)
+        @sid.record(rate:, clock_hz:)
+        @ted_waiting = []
+        @sid_waiting = []
+      end
+
+      # Runs both sources up to the current cycle.
+      def catch_up!
+        @ted_sound.catch_up!
+        @sid.catch_up!
+      end
+
+      # The mixed samples both sources have closed since the last drain.
+      def drain_samples
+        ted = @ted_waiting.concat(@ted_sound.drain_samples)
+        sid = @sid_waiting.concat(@sid.drain_samples)
+        count = [ted.length, sid.length].min
+        mixed = Array.new(count) { |index| (ted[index] + sid[index]).clamp(-0x8000, 0x7fff) }
+        @ted_waiting = ted[count, ted.length - count] || []
+        @sid_waiting = sid[count, sid.length - count] || []
+        mixed
+      end
+    end
+  end
+end

data/lib/badline/plus4/tcbm_drive.rb

@@ -0,0 +1,120 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The 264 series' true drives: a Drives::Model1541 and a
+    # Drives::Model1581 on the serial bus (C64::TrueDrives), and a
+    # Drives::Model1551 on TCBM, its interface's TIA in the expansion port
+    # at $FEE0 for device 8 or $FEC0 for device 9. Each sits in a field of
+    # its own, so none makes another's per-cycle call a union.
+    #
+    # A device number has one drive at a time: a 1551 takes the place of a
+    # serial drive with its number, and the other way round.
+    module TCBMDrive
+      # The true drive models plug_true_drive builds.
+      TRUE_DRIVE_MODELS = %w[1541 1551].freeze
+
+      # The 1551 on TCBM, or nil.
+      attr_reader :drive1551
+
+      # The drive plug_true_drive plugs in, "1541" or "1551".
+      attr_reader :true_drive_model
+
+      # Plugs in a Drives::Model1551, its interface's TIA where its device
+      # number puts it, in place of the TCBM interface's own there, and in
+      # place of a serial drive with its number. The traps stop answering
+      # device 8 when the drive is device 8.
+      def attach_drive1551(drive)
+        detach_drive1551
+        device = drive.device
+        detach_drive1541 if @drive1541&.device == device
+        detach_drive1581 if @drive1581&.device == device
+        drive.host_clock_hz = timing.clock_hz
+        @drive1551 = drive
+        @bus.plug_tia(drive.device, drive.host_tia)
+        @serial_trap&.device = serial_trap_device
+        @init_threshold = [@init_threshold, Badline::Drives::Model1551::BOOT_CYCLES].max if @cycles < @init_threshold
+      end
+
+      # Unplugs the Drives::Model1551, leaving the TCBM interface's own TIA,
+      # if there is one, in its place.
+      def detach_drive1551
+        drive = @drive1551
+        return unless drive
+
+        @bus.plug_tia(drive.device, tcbm_tia(drive.device))
+        @drive1551 = nil
+        @serial_trap&.device = serial_trap_device
+      end
+
+      # The true drive: a 1581 ahead of a 1551 ahead of a 1541.
+      def true_drive = @drive1581 || @drive1551 || @drive1541
+
+      # Plugs in the model true_drive_model names as device 8, in place of
+      # the drive there, and returns it.
+      def plug_true_drive
+        return plug_drive1551 if @true_drive_model == "1551"
+
+        unplug_device8
+        detach_drive1581 if drive1581_on_device8?
+        Badline::Drives::Model1541.new.tap { |drive| attach_drive1541(drive) }
+      end
+
+      # Plugs in a 1551 as device 8, in place of the drive there, and
+      # returns it.
+      def plug_drive1551
+        Badline::Drives::Model1551.new.tap { |drive| attach_drive1551(drive) }
+      end
+
+      private
+
+      def init_drives(true_drive_model)
+        unless TRUE_DRIVE_MODELS.include?(true_drive_model)
+          raise ArgumentError, "no true drive model #{true_drive_model} for the Plus/4"
+        end
+
+        @true_drive_model = true_drive_model
+        @drive1541 = nil
+        @drive1551 = nil
+        @drive1581 = nil
+      end
+
+      def save_drive1551_modules(sections)
+        drive = @drive1551
+        drive&.save_modules(sections, "BL-D#{drive.device}")
+        sections
+      end
+
+      def load_drive1551_modules(modules, input, device)
+        return input.adjust("a 1551 as device #{device}, left out") unless [8, 9].include?(device)
+
+        detach_drive1551 if @drive1551 && @drive1551.device != device
+        attach_drive1551(Badline::Drives::Model1551.new(device:)) unless @drive1551
+        @drive1551.load_modules(modules, input, "BL-D#{device}")
+      end
+
+      # The TCBM interface's own TIA for +device+, or nil without one.
+      def tcbm_tia(device)
+        tias = @tias
+        return nil if tias.empty?
+
+        device == 9 ? tias[1] : tias[0]
+      end
+
+      # Device 8, unless a true drive is device 8.
+      def serial_trap_device
+        device = KernalTrap::Routine::DEVICE
+        on_device8 = @drive1551&.device == device || @drive1541&.device == device || drive1581_on_device8?
+        on_device8 ? nil : device
+      end
+
+      # Unplugs the 1541 and the 1551 if either is device 8, for a 1581 to
+      # take its place.
+      def unplug_device8
+        device = KernalTrap::Routine::DEVICE
+        detach_drive1541 if @drive1541&.device == device
+        detach_drive1551 if @drive1551&.device == device
+      end
+    end
+  end
+end

data/lib/badline/plus4/user_port.rb

@@ -6,22 +6,31 @@ module Badline
     # latch: a line reads low where the latch or the outside pulls it. With
     # nothing plugged into the user port, the outside pulls only bit 2, the
     # cassette sense switch, low while a key is down on the deck. The
-    # KERNAL's IRQ reads it there ($CFBF).
+    # KERNAL's IRQ reads it there ($CFBF), and takes P1 as RS-232's clear
+    # to send, sending through the ACIA only while it reads high.
+    #
+    # A device on the user port drives P0-P7 through #inputs, low where its
+    # bit is clear.
     class UserPort
       TAPE_SENSE = 0x04
 
       attr_reader :output
+      attr_accessor :inputs
 
       def initialize(datasette)
         @datasette = datasette
         @output = 0xff
+        @inputs = 0xff
       end
 
       def reset!
         @output = 0xff
       end
 
-      def peek(_addr) = @datasette.sense_low? ? @output & ~TAPE_SENSE : @output
+      def peek(_addr)
+        lines = @output & @inputs
+        @datasette.sense_low? ? lines & ~TAPE_SENSE : lines
+      end
 
       def poke(_addr, value)
         @output = value