badline 0.14.0 → 0.15.1

data/lib/badline/plus4/bus.rb

@@ -10,9 +10,14 @@ module Badline
     # $C000-$FCFF - the high ROM bank, or RAM; $FC00-$FCFF is always the
     #               KERNAL's while ROM is selected
     # $FD00-$FD0F - the 6551 ACIA (Plus/4 only)
-    # $FD10-$FD1F - the user port's 6529 (Plus/4 only)
+    # $FD10-$FD1F - the user port's 6529 (Plus/4 only), or with a RAM
+    #               expansion, the 6529 at $FD10 and the expansion's
+    #               registers at $FD15 and $FD16
     # $FD30-$FD3F - the keyboard's 6529 (KeyboardPort)
+    # $FD40-$FD5F - a SID card's SID, where one is fitted there
     # $FDD0-$FDDF - the ROM bank latch
+    # $FE80-$FE9F - a SID card's SID, where one is fitted there
+    # $FEC0-$FEFF - a 1551's TCBM interface, where one is plugged in
     # $FF00-$FF1F - the TED
     # $FF3E/$FF3F - a write selects ROM or RAM at $8000-$FFFF
     # $FF40-$FFFF - the high ROM bank, or RAM
@@ -27,23 +32,32 @@ module Badline
     #
     # RAM smaller than 64K repeats through the 64K, as the C16's 16K does
     # without A14 and A15. Where nothing answers, a read finds the last byte
-    # on the bus.
+    # on the bus. A RAM expansion (RAMExpansion) picks the RAM each page
+    # reads and writes, the CPU's and the TED's.
+    #
+    # The TED fetches through the same banks: the video matrix and the
+    # attributes from ROM or RAM at $8000-$FFFF as the CPU sees it, with no
+    # I/O in the way (#ted_fetch), and character and bitmap data from RAM,
+    # or from ROM with $FF12 bit 2 set, where below $8000 and in an empty
+    # bank it finds the last byte on the bus (#ted_pattern_fetch, Plus/4
+    # openmem). Each byte it fetches is left on the bus.
     class Bus
       include Addressable
 
       RAM_POWER_ON = 0x00
 
-      # RAM through a size it repeats at.
+      # RAM through a size it repeats at, from +offset+ on in +ram+.
       class MirroredRAM
-        def initialize(ram, mask)
+        def initialize(ram, mask, offset = 0)
           @ram = ram
           @mask = mask
+          @offset = offset
         end
 
-        def peek(addr) = @ram.peek(addr & @mask)
+        def peek(addr) = @ram.peek((addr & @mask) + @offset)
 
         def poke(addr, value)
-          @ram.poke(addr & @mask, value)
+          @ram.poke((addr & @mask) + @offset, value)
         end
       end
 
@@ -73,14 +87,22 @@ module Badline
         end
       end
 
-      # Page $FD: the ACIA, the user port, the keyboard port and the ROM
-      # bank latch, by the address's bits 4-7. +acia+ and +user_port+ are
-      # nil where the machine has none.
+      # Page $FD: the ACIA, the user port, the keyboard port, a SID card and
+      # the ROM bank latch, by the address's bits 4-7. +acia+, +user_port+
+      # and +sid_card+ are nil where the machine has none, and
+      # +cassette_sense+ answers in the user port's place on a machine
+      # without one (CassetteSense). The SID card decodes its 32 bytes
+      # alone, with no mirrors, as xplus4's does. A RAM expansion
+      # (RAMExpansion) leaves the user port only $FD10 of $FD10-$FD1F, and
+      # has its register at $FD16.
       class IOPage
-        def initialize(keyboard_port:, acia: nil, user_port: nil)
+        def initialize(keyboard_port:, acia: nil, user_port: nil, cassette_sense: nil, sid_card: nil)
           @bus = nil
+          @ram_expansion = nil
           @acia = acia
+          @sid_card = sid_card
           @user_port = user_port
+          @cassette_sense = cassette_sense
           @keyboard_port = keyboard_port
         end
 
@@ -88,13 +110,15 @@ module Badline
         # a write to $FDD0-$FDDF sets.
         def connect(bus)
           @bus = bus
+          @ram_expansion = bus.ram_expansion
         end
 
         def peek(addr)
           case addr & 0xf0
           when 0x00 then @acia ? @acia.peek(addr) : @bus.data
-          when 0x10 then @user_port ? @user_port.peek(addr) : @bus.data
+          when 0x10 then @ram_expansion ? expansion_peek(addr) : user_port_peek(addr)
           when 0x30 then @keyboard_port.peek(addr)
+          when 0x40, 0x50 then @sid_card ? @sid_card.peek(addr) : @bus.data
           else @bus.data
           end
         end
@@ -102,11 +126,37 @@ module Badline
         def poke(addr, value)
           case addr & 0xf0
           when 0x00 then @acia&.poke(addr, value)
-          when 0x10 then @user_port&.poke(addr, value)
+          when 0x10 then @ram_expansion ? expansion_poke(addr, value) : @user_port&.poke(addr, value)
           when 0x30 then @keyboard_port.poke(addr, value)
+          when 0x40, 0x50 then @sid_card&.poke(addr, value)
           when 0xd0 then @bus.select_banks(addr)
           end
         end
+
+        private
+
+        def expansion_peek(addr)
+          case addr & 0x0f
+          when 0x00 then user_port_peek(addr)
+          when RAMExpansion::CONTROL then @ram_expansion.control
+          else @bus.data
+          end
+        end
+
+        def expansion_poke(addr, value)
+          if addr.nobits?(0x0f)
+            @user_port&.poke(addr, value)
+          else
+            @bus.ram_expansion_written(addr, value)
+          end
+        end
+
+        def user_port_peek(addr)
+          return @user_port.peek(addr) if @user_port
+          return @cassette_sense.read(@bus.data) if @cassette_sense
+
+          @bus.data
+        end
       end
 
       # VICE's debug cartridge register at $FDCF, a spot in the I/O page
@@ -130,26 +180,50 @@ module Badline
         end
       end
 
-      # Page $FE with a 1551's TCBM interface plugged in: the 6523 TIA
-      # that talks to drive 9 at $FEC0-$FEDF and drive 8's at $FEE0-$FEFF.
-      # The rest of the page is open.
+      # Page $FE, where a 1551's TCBM interface puts its 6523 TIA: the one
+      # that talks to drive 9 at $FEC0-$FEDF and drive 8's at $FEE0-$FEFF,
+      # and where a SID card can put its SID, at $FE80-$FE9F, decoding its
+      # 32 bytes alone as xplus4's does. The rest of the page, and a place
+      # with nothing in it, is open.
       class TCBMPage
-        def initialize(bus, drive8:, drive9:)
+        # The TIA at $FEE0-$FEFF and the one at $FEC0-$FEDF, or nil.
+        attr_accessor :drive8, :drive9
+
+        # The SIDCard at $FE80-$FE9F, or nil.
+        attr_accessor :sid_card
+
+        def initialize(bus)
           @bus = bus
-          @drive8 = drive8
-          @drive9 = drive9
+          @drive8 = nil
+          @drive9 = nil
+          @sid_card = nil
         end
 
         def peek(addr)
-          return @bus.data if addr < 0xfec0
+          return low_peek(addr) if addr < 0xfec0
 
-          addr < 0xfee0 ? @drive9.peek(addr) : @drive8.peek(addr)
+          tia = addr < 0xfee0 ? @drive9 : @drive8
+          tia ? tia.peek(addr) : @bus.data
         end
 
         def poke(addr, value)
-          return if addr < 0xfec0
+          if addr < 0xfec0
+            sid_card = @sid_card
+            sid_card.poke(addr, value) if sid_card && sid_card?(addr)
+            return
+          end
+
+          tia = addr < 0xfee0 ? @drive9 : @drive8
+          tia&.poke(addr, value)
+        end
 
-          addr < 0xfee0 ? @drive9.poke(addr, value) : @drive8.poke(addr, value)
+        private
+
+        def sid_card?(addr) = (addr & 0xe0) == 0x80
+
+        def low_peek(addr)
+          sid_card = @sid_card
+          sid_card && sid_card?(addr) ? sid_card.peek(addr) : @bus.data
         end
       end
 
@@ -168,7 +242,7 @@ module Badline
         end
 
         def poke(addr, value)
-          return @bus.ram_view.poke(addr, value) if addr >= 0xff40
+          return @bus.top_ram.poke(addr, value) if addr >= 0xff40
 
           case addr
           when 0xff3e then @bus.rom_selected = true
@@ -183,17 +257,29 @@ module Badline
       # What the top page reads above $FF3F: the high ROM bank or RAM.
       attr_reader :top_memory
 
+      # The RAM the CPU sees at $FF00-$FFFF, which a write above $FF3F
+      # reaches.
+      attr_reader :top_ram
+
+      # The RAMExpansion fitted, or nil.
+      attr_reader :ram_expansion
+
       # The CPU sees ROM at $8000-$FFFF.
       attr_reader :rom_selected
 
       # +io+ is the IOPage, +model+ a Model profile, whose KERNAL it maps
       # and whose function ROMs it maps where the model has them, and
-      # +ram_kb+ the RAM fitted.
-      def initialize(ted:, port:, io:, model: Model::PLUS4, ram_kb: model.ram_kb)
+      # +ram_kb+ the RAM fitted. +ram_expansion+ names the kind of
+      # RAMExpansion to fit over 64K of it.
+      def initialize(ted:, port:, io:, model: Model::PLUS4, ram_kb: model.ram_kb, ram_expansion: nil)
         addressable_at(0, length: 2**16)
         size = ram_kb * 1024
         @ram = Memory.new(Array.new(size, RAM_POWER_ON), length: size, start: 0)
         @ram_view = MirroredRAM.new(@ram, size - 1)
+        @ram_expansion = ram_expansion ? RAMExpansion.new(ram_expansion, @ram, @ram_view) : nil
+        @cpu_ram = Array.new(256, @ram_view)
+        @ted_ram = Array.new(256, @ram_view)
+        @top_ram = @ram_view
         @ted = ted
         @open_bus = OpenBus.new(self)
         @low_roms = [ROM.load("plus4/basic.rom", 0x8000), nil, nil, nil]
@@ -202,31 +288,44 @@ module Badline
           @low_roms[1] = ROM.load("plus4/function-low.rom", 0x8000)
           @high_roms[1] = ROM.load("plus4/function-high.rom", 0xc000)
         end
+        @port = port
         @zero_page = ZeroPage.new(port, @ram_view)
         @io_page = io
         io.connect(self)
         @top_page = TopPage.new(self, ted)
-        @tcbm_page = @open_bus
+        @tcbm_page = TCBMPage.new(self)
         @debug_register = nil
         @data = 0
         @read_pages = Array.new(256, @open_bus)
         @write_pages = Array.new(256, @ram_view)
+        @ted_pages = Array.new(256, @ram_view)
+        @ted_rom_pages = Array.new(256, @open_bus)
         @low_bank = @high_bank = 0
         @rom_selected = true
         @top_memory = @ram_view
-        map_writes
-        map_reads
+        map_ram
       end
 
       def power_on!
         @ram.clear!(Array.new(@ram.length, RAM_POWER_ON))
+        @ram_expansion&.power_on!
         reset!
       end
 
-      # The RESET line selects ROM and the first bank of each.
+      # The RESET line selects ROM and the first bank of each, and sets a
+      # RAM expansion's register.
       def reset!
         @low_bank = @high_bank = 0
-        self.rom_selected = true
+        @ram_expansion&.reset!
+        @rom_selected = true
+        @ted.rom_selected = true
+        map_ram
+      end
+
+      # A write to a RAM expansion's registers in $FD11-$FD1F.
+      def ram_expansion_written(addr, value)
+        @ram_expansion.poke(addr, value)
+        map_ram
       end
 
       def rom_selected=(selected)
@@ -254,26 +353,64 @@ module Badline
 
       # Plugs in a 1551's TCBM interface, the TIAs at $FEC0-$FEFF.
       def plug_tcbm(drive8:, drive9:)
-        @tcbm_page = TCBMPage.new(self, drive8:, drive9:)
-        map_writes
-        map_reads
+        @tcbm_page.drive8 = drive8
+        @tcbm_page.drive9 = drive9
       end
 
-      # Puts a cartridge's ROM chips in the slots of cartridge 1: a chip at
-      # $8000 in low bank 2 and one at $C000 in high bank 2, each repeated
-      # through the bank's 16K.
+      # Puts a SIDCard at $FE80-$FE9F.
+      def plug_sid_card(sid_card)
+        @tcbm_page.sid_card = sid_card
+      end
+
+      # Puts +tia+ where the TCBM interface for +device+, 8 or 9, answers,
+      # or takes the one there out with nil.
+      def plug_tia(device, tia)
+        if device == 9
+          @tcbm_page.drive9 = tia
+        else
+          @tcbm_page.drive8 = tia
+        end
+      end
+
+      # Puts a cartridge's ROM chips in their slots, as a PLUS4 CARTRIDGE
+      # .crt numbers them: a chip's bank picks cartridge 1 (0) or 2 (1), in
+      # ROM banks 2 and 3, and its address the low ($8000) or the high
+      # ($C000) slot. A chip shorter than 16K repeats through the slot.
+      # Slots the chips don't name keep what they held.
       def attach_cartridge(chips)
         chips.each do |chip|
-          data = chip.data * (0x4000 / chip.data.length)
+          raise ArgumentError, "no Plus/4 cartridge slot in bank #{chip.bank}" unless chip.bank.between?(0, 1)
+
+          rom = chip.data
+          length = rom.length
+          data = Array.new(0x4000) { |i| length.zero? ? 0xff : rom[i % length] }
           if chip.address < 0xc000
-            @low_roms[2] = ROM.new(data, length: 0x4000, start: 0x8000)
+            @low_roms[2 + chip.bank] = ROM.new(data, length: 0x4000, start: 0x8000)
           else
-            @high_roms[2] = ROM.new(data, length: 0x4000, start: 0xc000)
+            @high_roms[2 + chip.bank] = ROM.new(data, length: 0x4000, start: 0xc000)
           end
         end
         map_reads
       end
 
+      # Empties both cartridges' slots, ROM banks 2 and 3, which then read
+      # as the open bus.
+      def detach_cartridges
+        @low_roms[2] = @low_roms[3] = @high_roms[2] = @high_roms[3] = nil
+        map_reads
+      end
+
+      # The slots that hold a cartridge's ROM, by xplus4's names: c1lo,
+      # c1hi, c2lo and c2hi.
+      def cartridge_slots
+        slots = []
+        slots << "c1lo" unless @low_roms[2].nil?
+        slots << "c1hi" unless @high_roms[2].nil?
+        slots << "c2lo" unless @low_roms[3].nil?
+        slots << "c2hi" unless @high_roms[3].nil?
+        slots
+      end
+
       def peek(addr)
         @data = @read_pages[addr >> 8].peek(addr)
       end
@@ -283,9 +420,42 @@ module Badline
         @write_pages[addr >> 8].poke(addr, value)
       end
 
+      # A TED fetch of the video matrix or the attributes.
+      def ted_fetch(addr)
+        @data = @ted_pages[addr >> 8].peek(addr)
+      end
+
+      # A TED fetch of character or bitmap data, from ROM when +rom+.
+      def ted_pattern_fetch(addr, rom)
+        @data = rom ? @ted_rom_pages[addr >> 8].peek(addr) : @ted_ram[addr >> 8].peek(addr)
+      end
+
       private
 
+      # Lays out the RAM a RAM expansion banks in, then every page.
+      def map_ram
+        expansion = @ram_expansion
+        if expansion
+          expansion.map(@cpu_ram, @ted_ram)
+          @zero_page = ZeroPage.new(@port, @cpu_ram[0])
+          @top_ram = @cpu_ram[0xff]
+        end
+        map_writes
+        map_reads
+      end
+
+      # Copies the RAM the CPU sees into +pages+, up to the I/O pages.
+      def copy_ram(pages)
+        cpu_ram = @cpu_ram
+        page = 1
+        while page < 0xfd
+          pages[page] = cpu_ram[page]
+          page += 1
+        end
+      end
+
       def map_writes
+        copy_ram(@write_pages) if @ram_expansion
         @write_pages[0x00] = @zero_page
         @write_pages[0xfd] = @debug_register || @io_page
         @write_pages[0xfe] = @tcbm_page
@@ -293,19 +463,48 @@ module Badline
       end
 
       def map_reads
-        @read_pages.fill(@ram_view, 0x00, 0xfd)
+        if @ram_expansion
+          copy_ram(@read_pages)
+        else
+          @read_pages.fill(@ram_view, 0x00, 0xfd)
+        end
         @read_pages[0x00] = @zero_page
-        map_roms if @rom_selected
-        @top_memory = @rom_selected ? @high_roms[@high_bank] || @open_bus : @ram_view
+        map_roms(@read_pages, @high_bank) if @rom_selected
+        @top_memory = @rom_selected ? @high_roms[@high_bank] || @open_bus : @top_ram
         @read_pages[0xfd] = @io_page
         @read_pages[0xfe] = @tcbm_page
         @read_pages[0xff] = @top_page
+        map_ted_reads
+      end
+
+      def map_ted_reads
+        expansion = @ram_expansion
+        if expansion
+          copy_ted_ram
+        else
+          @ted_pages.fill(@ram_view, 0x80, 0x80)
+        end
+        high_bank = expansion&.kernal_for_ted? ? 0 : @high_bank
+        high_rom = @high_roms[high_bank] || @open_bus
+        map_roms(@ted_pages, high_bank) if @rom_selected
+        map_roms(@ted_rom_pages, high_bank)
+        @ted_pages.fill(high_rom, 0xfd, 3) if @rom_selected
+        @ted_rom_pages.fill(high_rom, 0xfd, 3)
+      end
+
+      def copy_ted_ram
+        ted_ram = @ted_ram
+        page = 0
+        while page < 0x100
+          @ted_pages[page] = ted_ram[page]
+          page += 1
+        end
       end
 
-      def map_roms
-        @read_pages.fill(@low_roms[@low_bank] || @open_bus, 0x80, 0x40)
-        @read_pages.fill(@high_roms[@high_bank] || @open_bus, 0xc0, 0x3c)
-        @read_pages[0xfc] = @high_roms[0]
+      def map_roms(pages, high_bank)
+        pages.fill(@low_roms[@low_bank] || @open_bus, 0x80, 0x40)
+        pages.fill(@high_roms[high_bank] || @open_bus, 0xc0, 0x3c)
+        pages[0xfc] = @high_roms[0]
       end
     end
   end

data/lib/badline/plus4/cassette_sense.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The C16's and C116's cassette sense, which has no 6529 to go through:
+    # a read of $FD10-$FD1F enables a 74LS125 that drives the sense line
+    # onto data bit 2, low while a key is down on the deck (C16 schematic
+    # 251788, sheet 1, U11). Nothing drives the other bits, which keep the
+    # last byte on the bus, and a write goes nowhere.
+    class CassetteSense
+      TAPE_SENSE = 0x04
+
+      def initialize(datasette)
+        @datasette = datasette
+      end
+
+      # The byte a read finds, from +data+, the last byte on the bus.
+      def read(data) = @datasette.sense_low? ? data & ~TAPE_SENSE : data | TAPE_SENSE
+    end
+  end
+end

data/lib/badline/plus4/keyboard_port.rb

@@ -2,12 +2,19 @@
 
 module Badline
   class Plus4
-    # The keyboard: the 6529 at $FD30-$FD3F, whose eight outputs drive the
-    # key matrix's lines, and the TED's K0-K7 inputs, which $FF08 latches
-    # (Chips::TED#keyboard_port=). The KERNAL's scan ($DB11) writes each
-    # line's mask to $FD30 and $FF08 and reads the keys back from $FF08,
-    # and its key table at $E026 puts each key at line times 8 plus input
-    # bit.
+    # The keyboard and the joysticks: the 6529 at $FD30-$FD3F, whose eight
+    # outputs drive the key matrix's lines, and the TED's K0-K7 inputs,
+    # which $FF08 latches (Chips::TED#keyboard_port=). The KERNAL's scan
+    # ($DB11) writes each line's mask to $FD30 and $FF08 and reads the keys
+    # back from $FF08, and its key table at $E026 puts each key at line
+    # times 8 plus input bit.
+    #
+    # The joysticks share K0-K7. The byte written to $FF08 selects them,
+    # bit 2 low joystick 1 and bit 1 low joystick 2, as BASIC's JOY does
+    # ($FA and $FD). A selected joystick pulls up, down, left and right
+    # onto K0-K3 and its fire button onto K6 (joystick 1) or K7
+    # (joystick 2), and those lines settle against the matrix with the
+    # keys'.
     #
     # The 6529 is a quasi-bidirectional latch: a read returns what was
     # written to it.
@@ -28,8 +35,10 @@ module Badline
 
       attr_reader :keyboard, :output
 
-      def initialize(keyboard)
+      def initialize(keyboard, joystick1, joystick2)
         @keyboard = keyboard
+        @joystick1 = joystick1
+        @joystick2 = joystick2
         @output = 0xff
       end
 
@@ -43,9 +52,25 @@ module Badline
         @output = value
       end
 
-      # The K0-K7 inputs the TED latches on a write of +_value+ to $FF08:
-      # high but where a held key joins a line the 6529 pulls low.
-      def latch(_value) = @keyboard.scan(@output, 0xff).last
+      # The K0-K7 inputs the TED latches on a write of +value+ to $FF08:
+      # high but where a held key joins a line the 6529 pulls low, or a
+      # joystick +value+ selects holds a switch closed.
+      def latch(value) = @keyboard.scan(@output, joystick_lines(value)).last
+
+      private
+
+      def joystick_lines(value)
+        lines = 0xff
+        lines &= joystick_inputs(@joystick1.port_bits, 0x40) if value.nobits?(0x04)
+        lines &= joystick_inputs(@joystick2.port_bits, 0x80) if value.nobits?(0x02)
+        lines
+      end
+
+      # A joystick's switches, Input::Joystick's bits 0-4, on K0-K7: the
+      # directions on K0-K3 and the fire button on +fire+.
+      def joystick_inputs(bits, fire)
+        bits.anybits?(0x10) ? bits | 0xf0 : (bits | 0xf0) & ~fire & 0xff
+      end
     end
   end
 end

data/lib/badline/plus4/keyed_modules.rb

@@ -0,0 +1,116 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The whole machine as keyed snapshot modules (Snapshot::Keyed): BL-MACHINE
+    # with the setup, the cartridges' ROMs by slot, the CPU with its port,
+    # the TED, its sound, the SID card's SID where one is fitted, the
+    # keyboard's 6529, the user port's 6529 and the ACIA where the model
+    # has them, the TCBM interface's TIAs where one is plugged in, the RAM
+    # with the ROM bank latch and the ROM/RAM switch under bus.*, a RAM
+    # expansion's registers and banks, the datasette, device 8 through the
+    # traps and the true drives.
+    #
+    # A load maps the banks before the chips load, and works out what each
+    # unit derives from its fields once every unit is loaded.
+    module KeyedModules
+      def save_modules
+        bus = @bus
+        sections = [Snapshot::Keyed.section("BL-MACHINE") { |out| save_machine_fields(out) }]
+        sections << Snapshot::Keyed.section("BL-CART") { |out| bus.save_slot_fields(out) } if bus.cartridge?
+        save_chip_modules(sections)
+        sections << Snapshot::Keyed.section("BL-RAM") do |out|
+          bus.ram.save_fields(out, "ram")
+          bus.save_fields(out, "bus.")
+        end
+        expansion = bus.ram_expansion
+        sections << Snapshot::Keyed.section("BL-RAMEXP") { |out| expansion.save_fields(out) } if expansion
+        sections << Snapshot::Keyed.section("BL-TAPE") { |out| @datasette.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-TRAPDOS") { |out| save_trap_dos_fields(out) } if mounted?
+        save_drive_modules(sections)
+      end
+
+      # Raises Snapshot::FormatError for the modules of a machine built
+      # another way.
+      def load_modules(modules)
+        machine = modules.machine
+        check_snapshot_setup(Snapshot::Plus4Setup.read_fields(machine))
+        load_machine_fields(machine)
+        bus = @bus
+        memory = modules.required("BL-RAM")
+        bus.ram.load_fields(memory, "ram")
+        bus.load_fields(memory, "bus.")
+        bus.load_slot_fields(modules.optional("BL-CART") || Snapshot::Keyed::Reader.new("BL-CART"))
+        load_ram_expansion(modules)
+        bus.restored!
+        load_chip_modules(modules)
+        @datasette.load_fields(modules.required("BL-TAPE"))
+        trap_dos = modules.optional("BL-TRAPDOS")
+        trap_dos ? load_trap_dos_fields(trap_dos, detached: modules.detached?) : unmount
+        load_drive_modules(modules)
+        modules_restored!
+        self
+      end
+
+      private
+
+      def load_ram_expansion(modules)
+        expansion = @bus.ram_expansion
+        return if expansion.nil?
+
+        expansion.load_fields(modules.required("BL-RAMEXP"))
+      end
+
+      def save_chip_modules(sections)
+        sections << Snapshot::Keyed.section("BL-CPU") do |out|
+          @cpu.save_fields(out)
+          @port.save_fields(out, "port.")
+        end
+        sections << Snapshot::Keyed.section("BL-TED") { |out| @ted.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-TEDSOUND") { |out| @sound.save_fields(out) }
+        sid_card = @sid_card
+        sections << Snapshot::Keyed.section("BL-SID") { |out| sid_card.save_fields(out) } if sid_card
+        sections << Snapshot::Keyed.section("BL-KEYPORT") { |out| @keyboard_port.save_fields(out) }
+        user_port = @user_port
+        sections << Snapshot::Keyed.section("BL-USERPORT") { |out| user_port.save_fields(out) } if user_port
+        acia = @acia
+        sections << Snapshot::Keyed.section("BL-ACIA") { |out| acia.save_fields(out) } if acia
+        @tias.each_with_index do |tia, index|
+          sections << Snapshot::Keyed.section("BL-TIA#{index + 1}") { |out| tia.save_fields(out) }
+        end
+      end
+
+      def load_chip_modules(modules)
+        cpu = modules.required("BL-CPU")
+        @port.load_fields(cpu, "port.")
+        @ted.load_fields(modules.required("BL-TED"))
+        @sound.load_fields(modules.required("BL-TEDSOUND"))
+        @sid_card&.load_fields(modules.required("BL-SID"))
+        @keyboard_port.load_fields(modules.required("BL-KEYPORT"))
+        @user_port&.load_fields(modules.required("BL-USERPORT"))
+        @acia&.load_fields(modules.required("BL-ACIA"))
+        @tias.each_with_index { |tia, index| tia.load_fields(modules.required("BL-TIA#{index + 1}")) }
+        @cpu.load_fields(cpu)
+      end
+
+      def modules_restored!
+        @cpu.restored!
+        @ted.restored!
+        @sound.restored!(@ted)
+        @sid_card&.restored!
+        @port.restored!
+        @acia&.restored!
+        schedule
+      end
+
+      def check_snapshot_setup(setup)
+        ours = Snapshot::Plus4Setup.of(self)
+        return if setup == ours
+
+        raise Snapshot::FormatError, "the snapshot is of a #{setup}, not a #{ours}"
+      end
+    end
+
+    include KeyedModules
+  end
+end