badline 0.11.1 → 0.12.1

data/lib/badline/c128/drives.rb

@@ -2,9 +2,9 @@
 
 module Badline
   class C128
-    # The true drives on the C128's serial bus: a Drive1541, or the
-    # C128D's built-in 1571 (Drive1571), each in a field of its own, so
-    # neither makes the other's per-cycle call a union.
+    # The true drives on the C128's serial bus: a Drive1541, the C128D's
+    # built-in 1571 (Drive1571) or a 1581 (Drive1581::Slot), each in a
+    # field of its own, so none makes another's per-cycle call a union.
     module Drives
       attr_reader :drive1571
 
@@ -28,11 +28,15 @@ module Badline
         @serial_trap&.device = serial_trap_device
       end
 
-      # The true drive on the bus, the 1571 ahead of a 1541.
-      def true_drive = @drive1571 || @drive1541
+      # The true drive on the bus, a 1581 ahead of the 1571 ahead of a 1541.
+      def true_drive = @drive1581 || @drive1571 || @drive1541
 
-      # Plugs in the C128D's 1571 as device 8, and returns it.
-      def plug_true_drive = Drive1571.new.tap { |drive| attach_drive1571(drive) }
+      # Plugs in the C128D's 1571 as device 8, in place of a 1581 there, and
+      # returns it.
+      def plug_true_drive
+        detach_drive1581 if drive1581_on_device8?
+        Drive1571.new.tap { |drive| attach_drive1571(drive) }
+      end
 
       private
 
@@ -43,6 +47,7 @@ module Badline
         @save_trap = nil
         @drive1541 = nil
         @drive1571 = nil
+        @drive1581 = nil
         plug_serial_bus
         plug_fast_serial
       end
@@ -50,10 +55,25 @@ module Badline
       # Device 8, unless a true drive is on the bus as device 8.
       def serial_trap_device
         device = KernalTrap::Routine::DEVICE
-        @drive1571&.device == device || @drive1541&.device == device ? nil : device
+        @drive1571&.device == device || @drive1541&.device == device || drive1581_on_device8? ? nil : device
+      end
+
+      # A 1581 plugged in holds the machine's on_init handlers back until
+      # its DOS has booted, which takes longer than the C128 KERNAL's.
+      def drive1581_attached
+        @init_threshold = [@init_threshold, Drive1581::BOOT_CYCLES].max if @cycles < @init_threshold
       end
 
-      # A true 1541 (Computer::Attachments#save_serial_bus), then a 1571.
+      # Unplugs the 1541 and the 1571 if either is device 8, for a 1581 to
+      # take its place.
+      def unplug_device8
+        device = KernalTrap::Routine::DEVICE
+        detach_drive1541 if @drive1541&.device == device
+        detach_drive1571 if @drive1571&.device == device
+      end
+
+      # A true 1541 (Computer::Attachments#save_serial_bus), then a 1571 and
+      # a 1581.
       def save_serial_bus(out)
         out.boolean(true).boolean(!@drive1541.nil?)
         if @drive1541
@@ -61,25 +81,18 @@ module Badline
           @drive1541.save_state(out)
         end
         out.boolean(!@drive1571.nil?)
-        return unless @drive1571
-
-        out.int(@drive1571.device)
-        @drive1571.save_state(out)
+        if @drive1571
+          out.int(@drive1571.device)
+          @drive1571.save_state(out)
+        end
+        save_drive1581(out)
       end
 
       def load_serial_bus(input)
         input.boolean?
         load_drive1541(input)
         load_drive1571(input)
-      end
-
-      def load_drive1541(input)
-        return detach_drive1541 unless input.boolean?
-
-        device = input.int
-        detach_drive1541 if @drive1541 && @drive1541.device != device
-        attach_drive1541(Drive1541.new(device:)) unless @drive1541
-        @drive1541.load_state(input)
+        load_drive1581(input)
       end
 
       def load_drive1571(input)

data/lib/badline/c128/fast_serial.rb

@@ -22,6 +22,7 @@ module Badline
         drive_fast_serial if @fast_serial_out
         @drive1541&.host_cycle!
         @drive1571&.host_cycle!
+        @drive1581&.host_cycle!
       end
 
       def turn_fast_serial

data/lib/badline/c128/io_pages.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class Bus
+      # The chips at $D000-$DFFF, which the 8502 sees while I/O is mapped
+      # in and the Z80 reaches through IN and OUT.
+      module IOPages
+        private
+
+        def map_io_pages
+          @io_mapped = true
+          lay_out_io(@read_pages, @write_pages)
+          @read_pages[0xd5] = @write_pages[0xd5] = @mmu.c64_mode? ? @open_bus : @mmu
+          map_cartridge_io if @cartridge
+        end
+
+        # The chips into +reads+ and +writes+, but for the MMU's page.
+        def lay_out_io(reads, writes)
+          reads.fill(@vic, 0xd0, 4)
+          writes.fill(@vic_writes, 0xd0, 4)
+          reads[0xd4] = writes[0xd4] = @sid
+          reads[0xd6] = writes[0xd6] = @vdc
+          reads[0xd7] = writes[0xd7] = @debug_page || @open_bus
+          reads.fill(@color_ram, 0xd8, 4)
+          writes.fill(@color_ram, 0xd8, 4)
+          reads[0xdc] = writes[0xdc] = @cia1
+          reads[0xdd] = writes[0xdd] = @cia2
+          reads.fill(@open_bus, 0xde, 2)
+          writes.fill(@open_bus, 0xde, 2)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/mmu.rb

@@ -19,12 +19,11 @@ module Badline
     # A write to P0H or P1H waits until the matching P0L or P1L write
     # takes it.
     #
-    # On the C128 the Z80 runs first and hands the bus to the 8502. Here the
-    # 8502 runs from reset, with MCR as the Z80 leaves it. A machine built
-    # for C64 mode resets into C64 mode, the state the C128 KERNAL leaves
-    # when C= is held at power-on. In C64 mode the MMU answers nowhere, but
-    # the CPU's RAM bank, common RAM and the VIC's bank it holds stay in
-    # force.
+    # A reset clears MCR bit 0, so the Z80 runs first, boots and hands the
+    # bus to the 8502. A machine built for C64 mode resets into C64 mode
+    # instead, with the 8502 running, the state the C128 KERNAL leaves when
+    # C= is held at power-on. In C64 mode the MMU answers nowhere, but the
+    # CPU's RAM bank, common RAM and the VIC's bank it holds stay in force.
     class MMU
       CR = 0
       MCR = 5
@@ -86,7 +85,7 @@ module Badline
       def reset!
         fast_serial_out = fast_serial_out?
         @registers.fill(0)
-        @registers[MCR] = @reset_mode == :c64 ? MCR_C64_MODE | MCR_8502 : MCR_8502
+        @registers[MCR] = @reset_mode == :c64 ? MCR_C64_MODE | MCR_8502 : 0
         @registers[P1L] = 0x01
         @registers[VR] = VERSION
         @p0h_latch = 0
@@ -101,6 +100,9 @@ module Badline
       # CIA 1's CNT and SP drive SRQ and DATA.
       def fast_serial_out? = @registers[MCR].anybits?(MCR_FSDIR)
 
+      # Whether MCR bit 0 gives the bus to the Z80.
+      def z80? = @registers[MCR].nobits?(MCR_8502)
+
       # :c64 or :c128, the mode MCR bit 6 selects.
       def mode = c64_mode? ? :c64 : :c128
 

data/lib/badline/c128/modes.rb

@@ -2,10 +2,10 @@
 
 module Badline
   class C128
-    # Following the MMU between C128 and C64 mode: the KERNAL traps go to
-    # the KERNAL the machine runs, C= held from power-on starts it in C64
-    # mode through the C128 KERNAL, and #active_screen tells a front end
-    # which screen the mode's editor prints to.
+    # Following the MMU between C128 and C64 mode: the KERNAL traps and
+    # typed keys go to the KERNAL the machine runs, C= held from power-on
+    # starts it in C64 mode through the C128 KERNAL, and #active_screen
+    # tells a front end which screen the mode's editor prints to.
     module Modes
       # Holds C= down from power-on until the C128 KERNAL has taken the
       # machine to C64 mode, as a user does to start a C128 in C64 mode.
@@ -43,6 +43,19 @@ module Badline
         @holding_commodore = false
         @init_threshold = @cycles + Computer::INIT_THRESHOLD if @cycles < @init_threshold
       end
+
+      # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
+      # C128 mode BASIC 7.0's.
+      def feed_keyboard
+        c64 = mode == :c64
+        count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
+        return unless ram.peek(count).zero?
+
+        chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
+        ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
+        ram.poke(count, chunk.length)
+        @pending_keys = nil if @pending_keys.empty?
+      end
     end
   end
 end

data/lib/badline/c128/saved_state.rb

@@ -81,6 +81,8 @@ module Badline
         save_cartridge(out)
         @bus.save_state(out)
         @cpu.save_state(out)
+        @z80.save_state(out)
+        out.int(@z80_due).int(@chips_ahead).boolean(@cpu_reset_pending)
         save_trap_drive(out)
         save_serial_bus(out)
       end
@@ -98,9 +100,11 @@ module Badline
         @pending_keys = input.ints if input.boolean?
         @init_handlers_lost = [input.int - @init_handlers.length, 0].max
         load_cartridge(input)
+        @cpu_reset_pending = false
         @bus.load_state(input)
         push_serial_lines
         @cpu.load_state(input)
+        load_z80(input)
         load_trap_drive(input)
         load_serial_bus(input)
         push_fast_serial
@@ -108,6 +112,24 @@ module Badline
 
       private
 
+      # The Z80 and which CPU has the bus, which a state from before the
+      # Z80 leaves to the 8502. The bus, restored before it, hands the bus
+      # to its CPU without resetting the 8502.
+      def load_z80(input)
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running
+        @z80_due = @z80.cycles
+        @chips_ahead = 0
+        @cpu_reset_pending = false
+        return unless input.schema > 6
+
+        @z80.load_state(input)
+        @z80_due = input.int
+        @chips_ahead = input.int
+        @cpu_reset_pending = input.boolean?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+      end
+
       def check_setup(setup)
         ours = [@model.name, @sid.model, @c64_built ? :c64 : :c128]
         return if setup == ours

data/lib/badline/c128/z80.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+require "badline/z80/core"
+
+module Badline
+  class C128
+    # The C128's Z80A, on the Z80's side of the C128::Bus.
+    class Z80
+      include Badline::Z80::Core
+    end
+
+    # The Z80's accesses, through the pages C128::Bus lays out for it
+    # (Bus::Z80Pages). An IN or OUT first brings the chips up to the cycle
+    # it falls in, since the Z80 runs whole instructions ahead of them.
+    class Z80Bus
+      def initialize(bus)
+        @read_pages = bus.z80_read_pages
+        @write_pages = bus.z80_write_pages
+        @input_pages = bus.z80_input_pages
+        @output_pages = bus.z80_output_pages
+        @machine = nil
+      end
+
+      # The machine whose chips an IN or OUT catches up.
+      attr_writer :machine
+
+      def fetch(addr) = @read_pages[addr >> 8].peek(addr)
+
+      def read(addr) = @read_pages[addr >> 8].peek(addr)
+
+      def write(addr, value)
+        @write_pages[addr >> 8].poke(addr, value)
+      end
+
+      def input(port)
+        @machine.z80_catch_up
+        @input_pages[port >> 8].peek(port)
+      end
+
+      def output(port, value)
+        @machine.z80_catch_up
+        @output_pages[port >> 8].poke(port, value)
+      end
+
+      # Nothing drives the data bus in an interrupt acknowledge cycle.
+      def acknowledge = 0xff
+    end
+  end
+end

data/lib/badline/c128/z80_pages.rb

@@ -0,0 +1,118 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class Bus
+      # What the Z80 sees, in memory and through IN and OUT, laid over the
+      # 8502's map whenever the MMU, the port or a cartridge changes it
+      # while the Z80 has the bus.
+      #
+      # In C128 mode, with CR's RAM bank 0, the MMU translates $0000-$0FFF
+      # to $D000-$DFFF of bank 0: a read gets the Z80 BIOS, which the
+      # KERNAL ROM holds there, and a write or an IN or OUT the RAM at
+      # $Dxxx. With bank 1 those pages are RAM, common RAM's or bank 1's.
+      # $D000-$DFFF is RAM. In C64 mode the PLA decodes the Z80's memory
+      # accesses as it does the 8502's.
+      #
+      # In both modes the chips at $D000-$DFFF answer IN and OUT whether
+      # I/O is mapped in or not. The MMU's registers at $D500 take an OUT
+      # either way in C128 mode, but answer an IN only with CR's I/O bit
+      # on, memory answering it otherwise. While I/O is mapped in, the
+      # colour RAM the 8502 sees also answers at $1000-$13FF. An IN or OUT
+      # anywhere else reaches what memory has there.
+      module Z80Pages
+        # A colour RAM bank seen at $1000-$13FF.
+        class ColorWindow
+          def initialize(color_ram)
+            @color_ram = color_ram
+          end
+
+          def peek(addr) = @color_ram.peek(0xd800 | (addr & 0x3ff))
+          def poke(addr, value) = @color_ram.poke(0xd800 | (addr & 0x3ff), value)
+        end
+
+        # The Z80's memory and I/O pages, each 256 entries.
+        attr_reader :z80_read_pages, :z80_write_pages, :z80_input_pages, :z80_output_pages
+
+        # Calls the block whenever MCR bit 0 hands the bus to the other CPU.
+        def on_processor_change(&block)
+          @on_processor_change = block
+        end
+
+        # Whether the Z80 has the bus, MCR bit 0 low.
+        def z80? = @z80
+
+        private
+
+        # Lays out the Z80's pages again while it has the bus, and tells the
+        # machine if MCR bit 0 handed the bus over.
+        def update_z80!
+          z80 = @mmu.z80?
+          map_z80_pages if z80
+          return if z80 == @z80
+
+          @z80 = z80
+          @on_processor_change&.call
+        end
+
+        def build_z80_pages
+          @z80_bios = ROM.new(ROM.read("c128/kernal.rom")[0x1000, 0x1000], length: 0x1000, start: 0)
+          @z80_read_pages = Array.new(256)
+          @z80_write_pages = Array.new(256)
+          @z80_input_pages = Array.new(256)
+          @z80_output_pages = Array.new(256)
+          @z80_color_ram = [ColorWindow.new(@color_lines.color_ram(0)), ColorWindow.new(@color_lines.color_ram(1))]
+          @z80_translated = RAMWindow.new(@ram, 0xd000, 0xfff)
+          @z80 = @mmu.z80?
+          @on_processor_change = nil
+        end
+
+        def map_z80_pages
+          c128_mode = !@mmu.c64_mode?
+          bios = c128_mode && @mmu.cr < 0x40
+          @z80_read_pages.replace(@read_pages)
+          @z80_write_pages.replace(@write_pages)
+          map_z80_ram_pages if c128_mode
+          map_z80_bios if bios
+          map_z80_color_ram(c128_mode) if @io_mapped
+          @z80_input_pages.replace(@z80_read_pages)
+          @z80_output_pages.replace(@z80_write_pages)
+          @z80_input_pages.fill(@z80_translated, 0, 16) if bios
+          @io_mapped ? map_z80_io_from_cpu : map_z80_io
+        end
+
+        def map_z80_ram_pages
+          (0xd0..0xdf).each do |page|
+            ram = bank_of(page, @mmu.cpu_bank).zero? ? @ram : @bank1
+            @z80_read_pages[page] = @z80_write_pages[page] = ram
+          end
+        end
+
+        def map_z80_bios
+          @z80_read_pages.fill(@z80_bios, 0, 16)
+          @z80_write_pages.fill(@z80_translated, 0, 16)
+        end
+
+        def map_z80_color_ram(c128_mode)
+          window = @z80_color_ram[c128_mode ? @io_port.value & 0x01 : 1]
+          @z80_read_pages.fill(window, 0x10, 4)
+          @z80_write_pages.fill(window, 0x10, 4)
+        end
+
+        def map_z80_io_from_cpu
+          (0xd0..0xdf).each do |page|
+            @z80_input_pages[page] = @read_pages[page]
+            @z80_output_pages[page] = @write_pages[page]
+          end
+        end
+
+        # The chips at $D000-$DFFF while I/O is mapped out, leaving an IN
+        # at $D500 to memory.
+        def map_z80_io
+          lay_out_io(@z80_input_pages, @z80_output_pages)
+          @z80_output_pages[0xd5] = @mmu unless @mmu.c64_mode?
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/z80_turns.rb

@@ -0,0 +1,106 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The Z80's turns on the bus. MCR bit 0 hands the bus between the 8502
+    # and the Z80, and while the Z80 has it each cycle clocks the chips,
+    # then gives the Z80 2 T-states unless BA holds it. The Z80 runs whole
+    # instructions while it is behind, so an IN or OUT first brings the
+    # chips up to the cycle it falls in (#z80_catch_up), and the cycles
+    # that follow clock nothing until the machine catches up with them.
+    module Z80Turns
+      # The T-states from the start of an I/O machine cycle to the one its
+      # data moves in. 1 and 2 pass c128modez80-23, whose IN reads open
+      # bus, and 0, 3 and 4 fail it.
+      IO_DELAY = 2
+
+      attr_reader :z80
+
+      # Brings the chips up to the cycle an IN or OUT of the Z80 falls in.
+      def z80_catch_up
+        while @z80.cycles + IO_DELAY >= @z80_due
+          clock_chips
+          @chips_ahead += 1
+          @z80_due += 2
+        end
+      end
+
+      private
+
+      def build_z80
+        z80_bus = Z80Bus.new(@bus)
+        @z80 = Z80.new(z80_bus)
+        z80_bus.machine = self
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running
+        @z80_due = 0
+        @chips_ahead = 0
+        @cpu_reset_pending = @z80_running
+        @bus.on_processor_change { processor_changed }
+      end
+
+      # A cycle while the Z80 has the bus, or after it handed the bus to the
+      # 8502 while the chips were ahead.
+      def z80_cycle!
+        if @chips_ahead.positive?
+          @chips_ahead -= 1
+          @z80_turn = @z80_running || @chips_ahead.positive?
+          return
+        end
+
+        clock_chips
+        @z80_due += 2 unless @vic.ba_low?
+        z80 = @z80
+        z80.step! while @z80_running && z80.cycles < @z80_due
+      end
+
+      # The chips' share of a cycle while the Z80 has the bus, with the
+      # interrupt lines going to the Z80.
+      def clock_chips
+        handle_init if @cycles == @init_threshold
+        feed_keyboard if @pending_keys
+
+        clock_bits = @clock_bits
+        @clock_bits = @vic.clock_bits
+        @vic.test_step! if clock_bits >= 0x02
+
+        @vic.cycle!
+        @cia1.cycle!
+        @cia2.cycle!
+        @sid.cycle!
+        @datasette.cycle!
+        @vdc.cycle!
+
+        @z80.int = @cia1.interrupted? || @vic.interrupted?
+        nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
+        @restore_pulse = false
+        @nmi_asserted = nmi
+        @z80.nmi = nmi
+        clock_serial_bus
+
+        @cycles += 1
+      end
+
+      # MCR bit 0 handed the bus to the other CPU. The 8502 runs its reset
+      # vector the first time it gets the bus after a reset.
+      def processor_changed
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+        @z80_due = @z80.cycles
+        return if @z80_running || !@cpu_reset_pending
+
+        @cpu_reset_pending = false
+        @cpu.reset!
+      end
+
+      # The RES line reaches the Z80, and the 8502 waits for the bus to run
+      # its reset vector, unless the machine resets into C64 mode.
+      def reset_z80
+        @chips_ahead = 0
+        @z80_turn = @z80_running
+        @z80.reset!
+        @c64_built ? @cpu.reset! : @cpu_reset_pending = true
+      end
+    end
+  end
+end