badline 0.11.1 → 0.12.1

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data/CHANGELOG.md

@@ -1,5 +1,31 @@
 # Changelog
 
+## [0.12.1](https://github.com/elektronaut/badline/compare/v0.12.0...v0.12.1) (2026-10-10)
+
+
+### Bug Fixes
+
+* keep the 1581's idle deadline within a native build's integers ([a98848f](https://github.com/elektronaut/badline/commit/a98848f0889ca7ad4c12007976b63d54bbbf122b))
+* refuse snapshot values a native build can't hold, on CRuby too ([5ec51e8](https://github.com/elektronaut/badline/commit/5ec51e81cfabfdb585367bb2f8183516ac64d2b0))
+
+## [0.12.0](https://github.com/elektronaut/badline/compare/v0.11.1...v0.12.0) (2026-10-10)
+
+
+### Features
+
+* add the 1581's WD1772 and its .d81 disks at sector level ([b834218](https://github.com/elektronaut/badline/commit/b834218bb686ceef295f2aafada86910fe8b61a2))
+* boot C128 boot disks such as CP/M at power-on ([69359b6](https://github.com/elektronaut/badline/commit/69359b60bfe91ec0d9634e3dec4e4039044814e7))
+* emulate the 1581 drive on the C64, the VIC-20 and the C128 ([4696c5b](https://github.com/elektronaut/badline/commit/4696c5b205689b2a86f91503ce153a63ff0f6816))
+* put the C128's Z80 on its bus and boot the C128 through it ([b3d0e60](https://github.com/elektronaut/badline/commit/b3d0e603a8dc606d090917a67a52c4f31854f307))
+
+
+### Bug Fixes
+
+* let the 1571's WD1770 run its commands, so CP/M's disk BIOS finds no MFM disk ([a380768](https://github.com/elektronaut/badline/commit/a380768ae02ce5da33e73dc23147b4edb72c72ff))
+* parse --at insert of a disk list without the rest of badline ([5d6b93a](https://github.com/elektronaut/badline/commit/5d6b93a86cf4b57be3312bfb7da32980d38f2800))
+* save the KCS Power cartridge's I/O RAM in snapshots ([54fab40](https://github.com/elektronaut/badline/commit/54fab408d0d7447d5b7b977905aa7aaabf8ad92a))
+* uninstall the serial traps when the VIC-20 unmounts ([b2acc3f](https://github.com/elektronaut/badline/commit/b2acc3ff495f10ec5bff3b56aae0e89b2741bd34))
+
 ## [0.11.1](https://github.com/elektronaut/badline/compare/v0.11.0...v0.11.1) (2026-10-09)
 
 

data/CLAUDE.md

@@ -51,7 +51,7 @@ requires only the namespace file.
 | SingleStepTests 65x02 | `rake test` (100 sampled cases per opcode) | CPU, per-cycle bus traces |
 | SingleStepTests z80 | `rake test` (the first 100 cases per opcode, `Z80_SAMPLE=all` for all 1,604,000) | `Z80`: registers, flags, ports and the bus pins on every T-state |
 | Wolfgang Lorenz suite | `bin/lorenz` | CPU, CIA, interrupts |
-| VICE testbench | `bin/testbench <subtree>` | `VICII/`, `CIA/`, `interrupts/`, `CPU/`, cartridges with `--carts`, the true 1541 drive with `--drive`, the VIC-20 with `--vic20`, and the C128 in C64 mode with `--c128c64` |
+| VICE testbench | `bin/testbench <subtree>` | `VICII/`, `CIA/`, `interrupts/`, `CPU/`, cartridges with `--carts`, the true 1541 drive with `--drive`, the VIC-20 with `--vic20`, the C128 in C64 mode with `--c128c64`, in C128 mode with `--c128`, and its Z80 with `--c128-z80` |
 | VICE SID testprogs | `bin/sidtests` | SID |
 | Drive scenarios | `bin/drive_scenarios` | The true 1541 running the DOS ROM: save, format, the error channel, idle, write protect and autostart |
 | CIA offline grids | `bundle exec rspec --tag slow spec/badline/cia` | CIA timers and shift register, against a bare CIA in about 2 min |
@@ -136,10 +136,11 @@ worktree and owns a different set of files.
   fails a whole-suite run (every spec file, no filters) below 90%, while
   single-file and filtered runs skip the floor. `:slow` specs are excluded
   by default: run them with `bundle exec rspec --tag slow`
-- CI splits the spec files into shards, plain and `:slow`, by the run times
-  in `test/spec_times.json` (`bin/spec_shard`), and holds the plain shards'
-  merged coverage to the same 90%. After adding or moving expensive specs,
-  re-record the times with `bin/spec_shard --record` (its header says how)
+- `bundle exec parallel_rspec` is the whole run, `:slow` specs included,
+  in a process per core, held to the same 90% over the merged coverage.
+  CI runs it as two jobs, the plain examples (with the floor) and the
+  `:slow` ones. Agents run only the spec files they touch, with
+  plain `bundle exec rspec`, and leave whole runs to CI
 - Keep each plain example to a few hundred ms. A million cycles of a C64 or
   a C128 cost 3 to 5 s of CPU, and about three times that under coverage,
   so an example that boots a machine or runs more than about a million
@@ -215,13 +216,13 @@ the 6526A) for anything the interrupt register or the CIA model reaches; cartrid
 `testbench-drive` (`bin/testbench --drive`) and `drive-scenarios` (`bin/drive_scenarios <filter>`), plus `testbench-vic20` for the VIA; the VIC-20 (`vic20/`) →
 `testbench-vic20` (`bin/testbench --vic20`); the C128 (`c128.rb`, `c128/`), or
 the VIC-IIe, CPU or PLA code it shares with the C64 → `testbench-c128c64`
-(`bin/testbench --c128c64`); SID → `sid`, plus `sid-8580` for anything the 8580
+(`bin/testbench --c128c64`); the C128's Z80, MMU or hand-over → `testbench-c128-z80` (`bin/testbench --c128-z80`) and `testbench-c128`; SID → `sid`, plus `sid-8580` for anything the 8580
 model reaches (`bin/sidtests --sid 8580`). Leave the Lorenz chain to CI,
 unless your code has a rule in `doc/pinned-behaviour.md` that names Lorenz
 tests: the interrupt polling, CPU port and CIA timer rules. Run just the
 tests that rule names, one at a time, with
 `ruby --yjit bin/lorenz --resume <test> --stop-after <test>`. A stretch
-resumes on a fresh machine, so its cuts in the Rakefile have to stay before
+resumes on a fresh machine, so its cuts in `test/support/suites.rb` have to stay before
 `trap1`, where the tests start carrying state from one to the next. Both Lorenz
 and testbench load through the LOAD trap and type through the keyboard
 buffer, so storage, IEC and keyboard changes can move them too. A broken

data/CONTRIBUTING.md

@@ -55,17 +55,18 @@ brew install sdl2           # macOS
 apt install libsdl2-2.0-0   # Debian/Ubuntu
 ```
 
-Install the dependencies and run the specs:
+Install the dependencies and run the whole suite, a process per core, as
+CI does:
 
 ```sh
 bundle install
-bundle exec rspec
+bundle exec parallel_rspec
 ```
 
-A run of the whole suite fails if line coverage drops below 90%. Runs of
-single files or filtered examples skip that check. Specs tagged `:slow`
-boot the whole machine and are skipped by default. Run them with
-`bundle exec rspec --tag slow`.
+A run of the whole suite fails if line coverage drops below 90%. Run
+single files or filtered examples with `bundle exec rspec`, which skips
+that check. Specs tagged `:slow` boot the whole machine, and a plain
+`bundle exec rspec` skips them. Run them with `bundle exec rspec --tag slow`.
 
 The CPU is verified separately against the
 [65x02 single step tests](https://github.com/SingleStepTests/65x02), and

data/README.md

@@ -125,7 +125,7 @@ library, are covered in [doc/library.md](doc/library.md).
 | Format | Handling |
 |--------|----------|
 | `.prg`, `.p00` | Loaded into memory after boot. A program at the BASIC start (`$0801`) is `RUN`, anything else is left for you to `SYS` |
-| `.d64`, `.d71`, `.d81` | Mounted as device 8, then `LOAD"*",8,1` and `RUN`. Write-protected unless `--writable` |
+| `.d64`, `.d71`, `.d81` | Mounted as device 8, then `LOAD"*",8,1` and `RUN`. On a C128 in C128 mode a boot disk goes in a true drive instead and boots at power-on. See [Media](doc/media.md#c128-boot-disks). Write-protected unless `--writable` |
 | `.g64` | Put in a true 1541, then `LOAD"*",8,1` and `RUN`. It holds the disk's raw GCR, so copy protection that reads it works. Write-protected unless `--writable` |
 | `.m3u`, `.vfl` | A list of disk images, one path a line, relative to the list: an `.m3u` playlist, or a VICE flip list, which only unit 8's entries are taken from. Its first disk goes in as above, and the list is its set for the pause menu |
 | `.t64` | Mounted read-only as device 8 and loaded like a disk image. The files load by name, and no tape is involved |
@@ -139,7 +139,8 @@ Without `--true-drive`, device 8 is no drive at all but traps on the
 KERNAL's disk routines. Loading is instant, but fast loaders and copy
 protection that run code on the drive need `--true-drive`, which puts
 an emulated 1541 there, running its own DOS at a real 1541's speed. Its
-red LED lights in the bottom right corner of the border.
+red LED lights in the bottom right corner of the border. With
+`--true-drive`, a `.d81` goes in an emulated 1581 in place of the 1541.
 [doc/media.md](doc/media.md) has the details, and how to attach media
 from Ruby.
 
@@ -185,8 +186,11 @@ cartridge, through the KERNAL. `GO64` gets there from BASIC 7.0. A
 program that loads at `$1C01`, where BASIC 7.0 starts, runs, and other
 programs load at their own address. The disk in device 8 is served
 through the KERNAL traps in either mode, or with `--true-drive` by the
-C128D's 1571. The C128's Z80 isn't emulated:
-the 8502 starts the machine. `--model` picks the board: `c128` (the default, the flat C128
+C128D's 1571. A boot disk boots in C128 mode, as on a real C128: CP/M's
+system disks, a `.d81` such as VICE-testprogs' `c128-cpm/cpm3.d81` on a
+1581 among them, and boot games. `badline c128 cpm3.d81` comes up at
+CP/M's `A>` prompt. The Z80 starts the machine, as on a real C128, and hands
+it to the 8502. `--model` picks the board: `c128` (the default, the flat C128
 and the plastic C128D, PAL, with the 6581 SID and a VDC with 16K of
 RAM), `c128dcr` (the metal C128DCR, with the 8580, 6526As and a VDC with
 64K), and `c128ntsc` and `c128dcrntsc` for their NTSC versions. `--sid`
@@ -349,11 +353,14 @@ program or `.sid` dropped on it opens the menu to ask first.
 - **C128**: C128 mode with BASIC 7.0 and C64 mode, on the 8502 with its
   port, FAST mode, the VIC-IIe with its extra keyboard lines, the 8722
   MMU, the 8563 or 8568 VDC with its 80 column display, and 128K of RAM
-  (`badline c128`). The Z80 isn't emulated yet.
+  (`badline c128`), and the Z80, which boots the machine.
 - **1541**: an emulated drive running its own DOS (`--true-drive`).
 - **1571**: the C128D's drive running DOS 3.0, in 1541 mode and in 1571
   mode at 2 MHz with both sides of a `.d71` or `.g71`, and fast serial
   (burst) to a C128 in C128 mode (`badline c128 --true-drive`).
+- **1581**: the 3.5" drive running its own DOS on its WD1772 and 8520,
+  reading and writing `.d81` images, on the C64, the VIC-20 and the C128
+  (`--true-drive` with a `.d81`).
 - **Cartridges**: standard 8K, 16K and Ultimax, Simons' BASIC, Ocean,
   Fun Play / Power Play, Super Games, Epyx FastLoad, Westermann
   Learning, Rex Utility, C64 Game System / System 3, Dinamic, Zaxxon /

data/doc/media.md

@@ -36,6 +36,31 @@ drive's red LED lights in the bottom right corner of the border.
 A `.g64` holds the disk's raw GCR, half tracks and all, so copy
 protection and fast loaders that read it work.
 
+## The true 1581
+
+With a true drive on device 8, a `.d81` goes in an emulated 1581 in
+its place: the 3.5" drive's own DOS on its 6502, with its WD1772 reading
+and writing the image's sectors and its 8520 on the serial bus. Another
+disk image swaps the 1541 (or on the C128 the 1571) back in. On the
+C128 in C128 mode the 1581 talks fast serial (burst), as the 1571 does.
+
+## C128 boot disks
+
+At power-on the C128 KERNAL reads track 1, sector 0 of the disk in
+device 8, and when the block starts with `CBM` it loads and runs it.
+CP/M's system disks and boot games boot that way. A 1581 first loads and
+runs a `USR` file named `COPYRIGHT CBM 86` when the disk has one, which
+is how CP/M's 1581 disks hand the KERNAL their boot block.
+
+On a C128 in C128 mode, a `.d64`, `.d71` or `.d81` that boots, with that
+block or that file, goes in a true drive as device 8, a 1581 for a
+`.d81` and the C128D's 1571 otherwise, and nothing is typed, so the
+KERNAL boots it. `badline c128 cpm3.d81` comes up at CP/M's `A>`
+prompt. Other disks keep the traps and `LOAD"*",8,1`, `--true-drive`
+puts any disk in a true drive, and on the C64, the VIC-20 and a C128 in
+C64 mode nothing changes. A boot disk inserted while the machine runs
+boots at the next reset.
+
 ## Write protection
 
 Disks given on the command line, inserted from the pause menu or by an
@@ -56,7 +81,9 @@ another disk. Both write to disk images unless told otherwise:
 `disk: { read_only: true }`, as the test harnesses under `bin/` do. A
 `.g64` goes in the true 1541, and takes out a disk mounted through the
 traps, so `LOAD` and `SAVE` reach the 1541 too. With the 1541 in device
-8, a `.d64` goes in its drive as well.
+8, a `.d64` goes in its drive as well, and a `.d81` in a 1581 that takes
+the 1541's place. On a C128 in C128 mode, `attach` puts a boot disk in a
+true drive and types nothing (`Badline::Media::BootDisk`).
 
 `Badline::Media::DiskSet.around(path)` lists the disks of the set a disk
 image belongs to, which the pause menu's PREVIOUS DISK and NEXT DISK step

data/doc/pinned-behaviour.md

@@ -26,6 +26,7 @@ only catches the rows that happen to move.
 - [VIC light pen](#vic-light-pen)
 - [VIC-II 8565](#vic-ii-8565)
 - [VIC-IIe 2 MHz and TEST bit](#vic-iie-2-mhz-and-test-bit)
+- [C128 Z80 bus](#c128-z80-bus)
 - [VIC-II NTSC](#vic-ii-ntsc)
 - [VIC-II 6572 (Drean)](#vic-ii-6572-drean)
 - [CIA 6526 timer pipeline](#cia-6526-timer-pipeline)
@@ -1001,6 +1002,35 @@ $1C0E and checks the readings they print.
   per-cycle blanking. Their 8566 shows no grey dots. The 2mhzVIC
   references have none either.
 
+## C128 Z80 bus
+
+- The Z80 gets 2 T-states in every cycle BA leaves it the bus, with no
+  wait states for memory or I/O: each of the 1,868 `c128z80timing`
+  programs measures `T-states / 2` 1 MHz cycles with the screen blanked.
+  Pinned by `c128/z80/c128z80timing`. The timing rows can't pin where in
+  an I/O machine cycle the chips see an IN or OUT, since the timer starts
+  and stops through the same OUT: `Z80Turns::IO_DELAY` is 2 because
+  `c128modez80-23`'s IN at `$D700`, which reads open bus, passes at 1 or 2
+  and fails at 0, 3 and 4.
+- In C128 mode with CR bits 6-7 both 0, `$0000-$0FFF` reads the BIOS
+  (`$D000-$DFFF` of the KERNAL ROM), and a write, IN or OUT there reaches
+  the RAM at `$Dxxx` of bank 0. CR `$BF` (bank 2, which is bank 0 on a
+  128K machine) leaves the BIOS out, as does bank 1: `$0xxx` is RAM, common
+  RAM's or the bank's. `$D000-$DFFF` is RAM to the Z80's memory accesses.
+  Pinned by `c128modez80-15` to `-22` and `-25`, `outi/tstouti2` and
+  `mmu_zp_sp/tstz80bk` (x128 fails the last).
+- IN and OUT reach the chips at `$D000-$DFFF` whatever CR's I/O bit says,
+  in both modes. The MMU at `$D500` takes an OUT either way in C128 mode,
+  but answers an IN only with I/O on. Pinned by `c128modez80-10` (the IN)
+  and `tstz80bk`, which programs page relocation through OUT with CR
+  `$BF`.
+- While I/O is mapped in, the colour RAM the 8502 sees also answers at
+  `$1000-$13FF`, in memory and through IN and OUT. Pinned by
+  `c128modez80-02` to `-09` and `c64modez80-03` and `-05`.
+- In C64 mode the Z80's memory accesses decode as the 8502's do through
+  the PLA, with no BIOS. Pinned by `c64modez80-00` to `-06`.
+- Spec guard: [`z80_bus_spec.rb`](../spec/badline/c128/z80_bus_spec.rb).
+
 ## VIC-II NTSC
 
 The 6567R8 (`Region::NTSC`) and the 6567R56A (`Region::NTSC_OLD`) run
@@ -1507,7 +1537,7 @@ wasn't read.
     [`mechanism_spec.rb`](../spec/badline/drive1541/mechanism_spec.rb),
     and the `format/name-and-id`, `format/bam-free` and
     `format/trap-readable` rows of the `drive-scenarios` suite
-    ([`drive_scenarios.rb`](../test/drive_scenarios.rb)), which read the
+    ([`drive_scenarios.rb`](../test/support/drive_scenarios.rb)), which read the
     formatted disk back from its image.
 - The disk turns at 300 rpm whatever bit rate VIA 2's PB5-6 select: a
   turn is 200,000 drive cycles over every track and over a half track

data/exe/badline-ruby

@@ -39,7 +39,7 @@ if options.headless?
   console = if options.player_window?
               lambda do |input:, output:|
                 load_sdl
-                Badline::Frontend::PlayerWindow.new(input:, output:)
+                Badline::Frontend::PlayerController.new(input:, output:)
               end
             else
               Badline::Audio::Console.method(:new)

data/lib/badline/address_bus/saved_state.rb

@@ -17,15 +17,12 @@ module Badline
 
       # The 6510 port's direction and output registers, and the charge left
       # on its floating bits.
-      def port_state = [@port_ddr, @port_out, @port_floating]
+      def port_state = [@cpu_port.ddr, @cpu_port.data, @cpu_port.floating]
 
       # Sets the port as port_state reads it, as a snapshot restores it,
       # leaving the RAM under $00 and $01 alone.
       def restore_port(ddr, out, floating)
-        @port_ddr = ddr
-        @port_out = out
-        @port_floating = floating
-        update_port!
+        @cpu_port.restore(ddr, out, floating)
       end
 
       # The machine's memory and everything on the bus but the keyboard, the
@@ -33,7 +30,7 @@ module Badline
       # already in the port, built from its setup (Computer#load_state).
       def save_state(out)
         out.marker("BUS")
-        out.int(@port_ddr).int(@port_out).int(@port_floating)
+        out.int(@cpu_port.ddr).int(@cpu_port.data).int(@cpu_port.floating)
         @ram.save_state(out)
         @color_ram.save_state(out)
         @ram_expansion.save_state(out)
@@ -55,10 +52,7 @@ module Badline
         @ram_expansion.load_state(input)
         @cartridge&.load_state(input)
         @datasette.load_state(input)
-        @port_ddr = ddr
-        @port_out = port_out
-        @port_floating = floating
-        @io_port.value = port_value
+        @cpu_port.load(ddr, port_out, floating)
         update_overlays!
         @vic.load_state(input)
         @cia1.load_state(input)

data/lib/badline/address_bus.rb

@@ -52,9 +52,9 @@ module Badline
       def poke(_addr, _value); end
     end
 
+    # The 6510's port pins with pull-ups, and the floating ones (CPUPort).
     PORT_PULLUPS  = 0b0001_0111
     PORT_FLOATING = 0b1100_1000
-    TAPE_SENSE    = 0b0001_0000
 
     # RAM powers on in runs of $00 $00 $FF $FF $FF $FF $00 $00, inverted in
     # the second and fourth 16K: a C64C (ASSY 250469 R4) from
@@ -92,7 +92,7 @@ module Badline
 
       @datasette = Datasette.new
       @datasette.on_flag { @cia1.flag! }
-      @datasette.on_sense_change { @io_port.value = port_value }
+      @datasette.on_sense_change { @cpu_port.refresh }
 
       @color_ram = ColorMemory.new(@vic)
       @vic.vic_bank.connect(cia2: @cia2, color_ram: @color_ram)
@@ -100,10 +100,9 @@ module Badline
       @open_bus = OpenBus.new(@vic)
       @cpu_off_bus = false
 
-      @port_ddr = 0x00
-      @port_out = 0x00
-      @port_floating = 0x00
-      @io_port = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: port_value)
+      @cpu_port = CPUPort.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING)
+      @cpu_port.on_change { update_overlays! }
+      @io_port = @cpu_port.status
 
       @read_pages = Array.new(256)
       @write_pages = Array.new(256)
@@ -134,9 +133,7 @@ module Badline
     # their charge.
     def reset!
       @ram_expansion.reset!
-      @port_ddr = 0x00
-      @port_out = 0x00
-      update_port!
+      @cpu_port.reset!
     end
 
     def disable_overlays!
@@ -150,7 +147,7 @@ module Badline
     end
 
     def peek(addr)
-      return @port_ddr if addr.zero?
+      return @cpu_port.ddr if addr.zero?
       return @io_port.value if addr == 0x01
 
       @read_pages[addr >> 8].peek(addr)
@@ -162,8 +159,7 @@ module Badline
     def poke(addr, value)
       if addr < 0x02
         @ram.poke(addr, @vic.phi1_data)
-        addr.zero? ? @port_ddr = value : @port_out = value
-        update_port!
+        addr.zero? ? @cpu_port.write_ddr(value) : @cpu_port.write_data(value)
       elsif !@cpu_off_bus
         @write_pages[addr >> 8].poke(addr, value)
       end
@@ -185,21 +181,6 @@ module Badline
 
     private
 
-    def update_port!
-      driven = @port_ddr & PORT_FLOATING
-      @port_floating = (@port_floating & ~driven) | (@port_out & driven)
-      @io_port.value = port_value
-      # $01 bit 5 drives the motor through an inverter: low runs it.
-      @datasette.motor = !@io_port.tape_motor?
-      update_overlays!
-    end
-
-    def port_value
-      input = PORT_PULLUPS | (@port_floating & PORT_FLOATING)
-      input &= ~TAPE_SENSE if @datasette.sense_low?
-      (@port_out & @port_ddr) | (input & ~@port_ddr & 0xff)
-    end
-
     # Banking changes only on $01 writes and cartridge line/bank changes,
     # so reads and writes dispatch through per-page handler tables instead
     # of range checks.

data/lib/badline/audio/bare_player.rb

@@ -116,7 +116,7 @@ module Badline
         cycles
       end
 
-      def clock_hz = @tune.ntsc? ? NTSC_CLOCK_HZ : TimeOfDay::CLOCK_HZ
+      def clock_hz = @tune.ntsc? ? NTSC_CLOCK_HZ : Region::PAL.clock_hz
 
       private
 

data/lib/badline/c128/bus.rb

@@ -37,6 +37,8 @@ module Badline
       include AddressBus::PLA
       include AddressBus::ROMs
       include MMUPages
+      include IOPages
+      include Z80Pages
       include SavedState
 
       # The 8502's port has seven pins. P0-P5 are the 6510's, and P6 senses
@@ -45,7 +47,6 @@ module Badline
       PORT_PULLUPS  = 0b0001_0111
       PORT_FLOATING = 0b1000_1000
       CAPS_LOCK     = 0b0100_0000
-      TAPE_SENSE    = 0b0001_0000
 
       # The C64's power-on pattern (AddressBus::RAM_POWER_ON) in both 64K
       # banks. The C128's own DRAMs' pattern is unmeasured.
@@ -124,9 +125,6 @@ module Badline
       # KERNAL and the character ROM's C128 set.
       attr_reader :basic_low_rom, :basic_high_rom, :editor_rom, :c128_kernal_rom, :c128_character_rom
 
-      # Whether CAPS LOCK is down, holding P6 low.
-      attr_reader :caps_lock
-
       # The chips +model+, a Model::Profile, names, with the SID
       # +sid_model+. +mode+ is the mode the MMU resets into.
       def initialize(model, sid_model: model.sid_model, mode: :c64)
@@ -137,7 +135,6 @@ module Badline
         @mmu = MMU.new(mode)
         @cartridge = nil
         @debug_page = nil
-        @caps_lock = false
 
         load_roms
         load_c128_roms
@@ -148,19 +145,18 @@ module Badline
 
         @datasette = Datasette.new
         @datasette.on_flag { @cia1.flag! }
-        @datasette.on_sense_change { @io_port.value = port_value }
+        @datasette.on_sense_change { @cpu_port.refresh }
 
         @color_lines = ColorLines.new(@vic, @cia2, character_rom, @c128_character_rom)
         @color_ram = @color_lines.color_ram(1)
+        build_z80_pages
         @vic_writes = VICWrites.new(@vic, @control_ports)
         @open_bus = AddressBus::OpenBus.new(@vic)
         @configuration_reads = ConfigurationPage.new(@mmu, @open_bus)
         @configuration_writes = ConfigurationPage.new(@mmu, @open_bus)
 
-        @port_ddr = 0x00
-        @port_out = 0x00
-        @port_floating = 0x00
-        @io_port = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: port_value)
+        @cpu_port = CPUPort.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING, caps_lock: CAPS_LOCK)
+        @io_port = @cpu_port.status
 
         @read_pages = Array.new(256)
         @write_pages = Array.new(256)
@@ -168,6 +164,7 @@ module Badline
         @data = 0
         @io_mapped = false
         @mmu.on_change { update_overlays! }
+        @cpu_port.on_change { update_overlays! }
         update_overlays!
       end
 
@@ -188,19 +185,19 @@ module Badline
         @ram.clear!(RAM_POWER_ON)
       end
 
-      # The RES line clears the port's direction and output registers and
-      # resets the MMU. The port's floating bit keeps its charge.
+      # The RES line resets the MMU and clears the port's direction and
+      # output registers. The port's floating bit keeps its charge.
       def reset!
-        @port_ddr = 0x00
-        @port_out = 0x00
         @mmu.reset!
-        update_port!
+        @cpu_port.reset!
       end
 
+      # Whether CAPS LOCK is down, holding P6 low.
+      def caps_lock = @cpu_port.caps_lock
+
       # Holds CAPS LOCK down, or lets it up.
       def caps_lock=(down)
-        @caps_lock = down
-        @io_port.value = port_value
+        @cpu_port.caps_lock = down
       end
 
       # Calls the block whenever MCR bit 6 takes the machine into C64 mode or
@@ -233,7 +230,7 @@ module Badline
         @data = if addr > 0x01
                   @read_pages[addr >> 8].peek(addr)
                 else
-                  addr.zero? ? @port_ddr : @io_port.value
+                  addr.zero? ? @cpu_port.ddr : @io_port.value
                 end
       end
 
@@ -251,8 +248,7 @@ module Badline
         @data = value
         if addr < 0x02
           @write_pages[0].poke(addr, @vic.phi1_data)
-          addr.zero? ? @port_ddr = value : @port_out = value
-          update_port!
+          addr.zero? ? @cpu_port.write_ddr(value) : @cpu_port.write_data(value)
         else
           @write_pages[addr >> 8].poke(addr, value)
         end
@@ -291,21 +287,6 @@ module Badline
         @vdc = VDC.new(model: model.vdc_model, ram_kb: model.vdc_ram_kb, clock_hz: @region.clock_hz)
       end
 
-      def update_port!
-        driven = @port_ddr & PORT_FLOATING
-        @port_floating = (@port_floating & ~driven) | (@port_out & driven)
-        @io_port.value = port_value
-        @datasette.motor = !@io_port.tape_motor?
-        update_overlays!
-      end
-
-      def port_value
-        input = PORT_PULLUPS | (@port_floating & PORT_FLOATING)
-        input |= CAPS_LOCK unless @caps_lock
-        input &= ~TAPE_SENSE if @datasette.sense_low?
-        (@port_out & @port_ddr) | (input & ~@port_ddr & 0xff)
-      end
-
       def update_overlays!
         @ultimax = @cartridge ? @cartridge.ultimax? : false
         @phi1_ultimax = @cartridge ? @cartridge.phi1_ultimax? : false
@@ -318,6 +299,7 @@ module Badline
                                 romh: @cartridge&.romh)
         @color_ram = @color_lines.cpu_color_ram(c64_mode, port)
         c64_mode ? map_pla_pages : map_c128_pages
+        update_z80!
         mode_changed if c64_mode != @c64_mode
       end
 
@@ -325,23 +307,6 @@ module Badline
         @c64_mode = !@c64_mode
         @on_mode_change&.call
       end
-
-      def map_io_pages
-        @io_mapped = true
-        @read_pages.fill(@vic, 0xd0, 4)
-        @write_pages.fill(@vic_writes, 0xd0, 4)
-        @read_pages[0xd4] = @write_pages[0xd4] = @sid
-        @read_pages[0xd5] = @write_pages[0xd5] = @mmu.c64_mode? ? @open_bus : @mmu
-        @read_pages[0xd6] = @write_pages[0xd6] = @vdc
-        @read_pages[0xd7] = @write_pages[0xd7] = @debug_page || @open_bus
-        @read_pages.fill(@color_ram, 0xd8, 4)
-        @write_pages.fill(@color_ram, 0xd8, 4)
-        @read_pages[0xdc] = @write_pages[0xdc] = @cia1
-        @read_pages[0xdd] = @write_pages[0xdd] = @cia2
-        @read_pages.fill(@open_bus, 0xde, 2)
-        @write_pages.fill(@open_bus, 0xde, 2)
-        map_cartridge_io if @cartridge
-      end
     end
   end
 end

data/lib/badline/c128/bus_state.rb

@@ -11,7 +11,7 @@ module Badline
         # host holds. A cartridge is already in the port, built from its setup.
         def save_state(out)
           out.marker("C128 BUS")
-          out.int(@port_ddr).int(@port_out).int(@port_floating).int(@address).int(@data)
+          out.int(@cpu_port.ddr).int(@cpu_port.data).int(@cpu_port.floating).int(@address).int(@data)
           @mmu.save_state(out)
           @ram.save_state(out)
           @color_lines.color_ram(0).save_state(out)
@@ -27,9 +27,9 @@ module Badline
 
         def load_state(input)
           input.marker("C128 BUS")
-          @port_ddr = input.int
-          @port_out = input.int
-          @port_floating = input.int
+          ddr = input.int
+          data = input.int
+          floating = input.int
           @address = input.int
           @data = input.int
           @mmu.load_state(input)
@@ -38,7 +38,7 @@ module Badline
           @color_lines.color_ram(1).load_state(input)
           @cartridge&.load_state(input)
           @datasette.load_state(input)
-          @io_port.value = port_value
+          @cpu_port.load(ddr, data, floating)
           update_overlays!
           @vic.load_state(input)
           @control_ports.extra_rows = 0xf8 | @vic.extra_keyboard_lines